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- moved 3 char addressing modes to cpu_general.inl

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- moved 6502/6502c short-hand mnemonics to cpu_instructions.inl
This commit is contained in:
mpohoreski 2010-06-13 14:33:38 +00:00
parent d7801ca391
commit fe142e946d
3 changed files with 73 additions and 25 deletions
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26
AppleWin/source/CPU/cpu65d02.h
View File

@ -113,30 +113,6 @@ static DWORD Cpu65D02 (DWORD uTotalCycles)
//#define $ Store()
#define $ INV
// Tidy 3 char mnemonics to keep the table visually aligned, clean, and readable
#define abx ABSX
#define aby ABSY
#define idx INDX
#define idy INDY
#define izp IZPG
#define rol ROLA // Rotate Left
#define ror RORA // Rotate Rigth
#define asl ASLA // Arithmetic Shift Left
#define lsr LSRA // Logical Shift Right
#define zpx ZPGX
#define zpy ZPGY
// 0x6C // 65c02 IABSCMOS JMP // 6502 IABSNMOS JMP
// 0x7C IABSX
#define ADCc ADC_CMOS
#define ASLc ASL_CMOS
#define DECc DEC_CMOS
#define INCc INC_CMOS
#define LSRc LSR_CMOS
#define ROLc ROL_CMOS
#define RORc ROR_CMOS
#define SBCc SBC_CMOS
switch (iOpcode)
{
// TODO Optimization Note: ?? Move CYC(#) to array ??
@ -402,7 +378,7 @@ static DWORD Cpu65D02 (DWORD uTotalCycles)
case 0xFE: abx INC_CMOS CYC(6) break;
case 0xFF: INV NOP CYC(2) break;
*/
// Version 2 opcode: @ AM Instruction // @=DebugBreak AM=AddressingMode
// Version 2 opcode: $ AM Instruction // $=DebugBreak AM=AddressingMode
//! ! ! ! ! ! // Tab-Stops
case 0x00: BRK CYC(7) break;
case 0x01: idx ORA CYC(6) break;

32
AppleWin/source/CPU/cpu_general.inl
View File

@ -142,3 +142,35 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
#define ZPGX addr = ((*(mem+regs.pc++))+regs.x) & 0xFF;
#define ZPGY addr = ((*(mem+regs.pc++))+regs.y) & 0xFF;
// Tidy 3 char addressing modes to keep the opcode table visually aligned, clean, and readable.
#undef abx
#undef abx
#undef aby
#undef asl
#undef idx
#undef idy
#undef imm
#undef izp
#undef lsr
#undef rel
#undef rol
#undef ror
#undef zpx
#undef zpy
#define abx ABSX
#define aby ABSY
#define asl ASLA // Arithmetic Shift Left
#define idx INDX
#define idy INDY
#define imm IMM
#define izp IZPG
#define lsr LSRA // Logical Shift Right
#define rel REL
#define rol ROLA // Rotate Left
#define ror RORA // Rotate Right
#define zpx ZPGX
#define zpy ZPGY
// 0x6C // 65c02 IABSCMOS JMP // 6502 IABSNMOS JMP
// 0x7C IABSX

40
AppleWin/source/CPU/cpu_instructions.inl
View File

@ -137,6 +137,46 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// ==========
#undef ADCn
#undef ASLn
#undef DECn
#undef INCn
#undef LSRn
#undef ROLn
#undef RORn
#undef SBCn
#define ADCn ADC_NMOS
#define ASLn ASL_NMOS
#define DECn DEC_NMOS
#define INCn INC_NMOS
#define LSRn LSR_NMOS
#define ROLn ROL_NMOS
#define RORn ROR_NMOS
#define SBCn SBC_NMOS
// ==========
#undef ADCc
#undef ASLc
#undef DECc
#undef INCc
#undef LSRc
#undef ROLc
#undef RORc
#undef SBCc
#define ADCc ADC_CMOS
#define ASLc ASL_CMOS
#define DECc DEC_CMOS
#define INCc INC_CMOS
#define LSRc LSR_CMOS
#define ROLc ROL_CMOS
#define RORc ROR_CMOS
#define SBCc SBC_CMOS
// ==========
#define ADC_NMOS bSlowerOnPagecross = 1; \
temp = READ; \
if (regs.ps & AF_DECIMAL) { \