mirror of
https://github.com/AppleWin/AppleWin.git
synced 2024-08-18 20:29:01 +00:00
672 lines
18 KiB
C++
672 lines
18 KiB
C++
/*
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AppleWin : An Apple //e emulator for Windows
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Copyright (C) 1994-1996, Michael O'Brien
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Copyright (C) 1999-2001, Oliver Schmidt
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Copyright (C) 2002-2005, Tom Charlesworth
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Copyright (C) 2006-2010, Tom Charlesworth, Michael Pohoreski
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AppleWin is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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AppleWin is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with AppleWin; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/* Description: 6502/65C02 emulation
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*
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* Author: Various
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*/
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// TO DO:
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// . All these CPP macros need to be converted to inline funcs
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// TeaRex's Note about illegal opcodes:
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// ------------------------------------
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// . I've followed the names and descriptions given in
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// . "Extra Instructions Of The 65XX Series CPU"
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// . by Adam Vardy, dated Sept 27, 1996.
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// . The exception is, what he calls "SKB" and "SKW" I call "NOP",
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// . for consistency's sake. Several other naming conventions exist.
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// . Of course, only the 6502 has illegal opcodes, the 65C02 doesn't.
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// . Thus they're not emulated in Enhanced //e mode. Games relying on them
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// . don't run on a real Enhanced //e either. The old mixture of 65C02
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// . emulation and skipping the right number of bytes for illegal 6502
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// . opcodes, while working surprisingly well in practice, was IMHO
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// . ill-founded in theory and has thus been removed.
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// Note about bSlowerOnPagecross:
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// -------------------
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// . This is used to determine if a cycle needs to be added for a page-crossing.
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//
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// Modes that are affected:
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// . ABS,X; ABS,Y; (IND),Y
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//
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// The following opcodes (when indexed) add a cycle if page is crossed:
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// . ADC, AND, Bxx, CMP, EOR, LDA, LDX, LDY, ORA, SBC
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// . NB. Those opcode that DO NOT write to memory.
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// . 65C02: JMP (ABS-INDIRECT): 65C02 fixes JMP ($xxFF) bug but needs extra cycle in that case
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// . 65C02: JMP (ABS-INDIRECT,X): Probably. Currently unimplemented.
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//
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// The following opcodes (when indexed) DO NOT add a cycle if page is crossed:
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// . ASL, DEC, INC, LSR, ROL, ROR, STA, STX, STY
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// . NB. Those opcode that DO write to memory.
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//
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// What about these:
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// . 65C02: STZ?, TRB?, TSB?
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// . Answer: TRB & TSB don't have affected addressing modes
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// . STZ probably doesn't add a cycle since otherwise it would be slower than STA which doesn't make sense.
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//
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// NB. 'Zero-page indexed' opcodes wrap back to zero-page.
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// . The same goes for all the zero-page indirect modes.
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//
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// NB2. bSlowerOnPagecross can't be used for r/w detection, as these
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// . opcodes don't init this flag:
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// . $EC CPX ABS (since there's no addressing mode of CPY which has variable cycle number)
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// . $CC CPY ABS (same)
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//
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// 65C02 info:
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// . Read-modify-write instructions abs indexed in same page take 6 cycles (cf. 7 cycles for 6502)
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// . ASL, DEC, INC, LSR, ROL, ROR
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// . This should work now (but makes bSlowerOnPagecross even less useful for r/w detection)
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//
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// . Thanks to Scott Hemphill for the verified CMOS ADC and SBC algorithm! You rock.
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// . And thanks to the VICE team for the NMOS ADC and SBC algorithms as well as the
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// . algorithms for those illops which involve ADC or SBC. You rock too.
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#include "StdAfx.h"
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#include "AppleWin.h"
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#include "CPU.h"
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#include "Frame.h"
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#include "Memory.h"
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#include "Mockingboard.h"
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#include "MouseInterface.h"
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#ifdef USE_SPEECH_API
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#include "Speech.h"
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#endif
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#include "Video.h"
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#include "z80emu.h"
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#include "Z80VICE\z80.h"
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#include "Z80VICE\z80mem.h"
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#include "Debugger\Debug.h"
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#define AF_SIGN 0x80
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#define AF_OVERFLOW 0x40
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#define AF_RESERVED 0x20
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#define AF_BREAK 0x10
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#define AF_DECIMAL 0x08
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#define AF_INTERRUPT 0x04
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#define AF_ZERO 0x02
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#define AF_CARRY 0x01
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#define SHORTOPCODES 22
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#define BENCHOPCODES 33
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// What is this 6502 code?
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static BYTE benchopcode[BENCHOPCODES] = {0x06,0x16,0x24,0x45,0x48,0x65,0x68,0x76,
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0x84,0x85,0x86,0x91,0x94,0xA4,0xA5,0xA6,
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0xB1,0xB4,0xC0,0xC4,0xC5,0xE6,
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0x19,0x6D,0x8D,0x99,0x9D,0xAD,0xB9,0xBD,
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0xDD,0xED,0xEE};
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regsrec regs;
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unsigned __int64 g_nCumulativeCycles = 0;
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static ULONG g_nCyclesExecuted; // # of cycles executed up to last IO access
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//static signed long g_uInternalExecutedCycles;
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// TODO: Use IRQ_CHECK_TIMEOUT=128 when running at full-speed else with IRQ_CHECK_TIMEOUT=1
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// - What about when running benchmark?
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static const int IRQ_CHECK_TIMEOUT = 128;
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static signed int g_nIrqCheckTimeout = IRQ_CHECK_TIMEOUT;
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//
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// Assume all interrupt sources assert until the device is told to stop:
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// - eg by r/w to device's register or a machine reset
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static bool g_bCritSectionValid = false; // Deleting CritialSection when not valid causes crash on Win98
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static CRITICAL_SECTION g_CriticalSection; // To guard /g_bmIRQ/ & /g_bmNMI/
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static volatile UINT32 g_bmIRQ = 0;
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static volatile UINT32 g_bmNMI = 0;
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static volatile BOOL g_bNmiFlank = FALSE; // Positive going flank on NMI line
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#include "cpu/cpu_general.inl"
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#include "cpu/cpu_instructions.inl"
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void RequestDebugger()
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{
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// BUG: This causes DebugBegin to constantly be called.
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// It's as if the WM_KEYUP are auto-repeating?
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// FrameWndProc()
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// ProcessButtonClick()
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// DebugBegin()
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// PostMessage( g_hFrameWindow, WM_KEYDOWN, DEBUG_TOGGLE_KEY, 0 );
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// PostMessage( g_hFrameWindow, WM_KEYUP , DEBUG_TOGGLE_KEY, 0 );
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// Not a valid solution, since hitting F7 (to exit) debugger gets the debugger out of sync
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// due to EnterMessageLoop() calling ContinueExecution() after the mode has changed to DEBUG.
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// DebugBegin();
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FrameWndProc( g_hFrameWindow, WM_KEYDOWN, DEBUG_TOGGLE_KEY, 0 );
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FrameWndProc( g_hFrameWindow, WM_KEYUP , DEBUG_TOGGLE_KEY, 0 );
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}
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// Break into debugger on invalid opcodes
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#define INV IsDebugBreakOnInvalid(AM_1);
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/****************************************************************************
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*
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* OPCODE TABLE
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*
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***/
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#ifdef _DEBUG
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static unsigned __int64 g_nCycleIrqStart;
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static unsigned __int64 g_nCycleIrqEnd;
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static UINT g_nCycleIrqTime;
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static UINT g_nIdx = 0;
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static const UINT BUFFER_SIZE = 4096; // 80 secs
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static UINT g_nBuffer[BUFFER_SIZE];
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static UINT g_nMean = 0;
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static UINT g_nMin = 0xFFFFFFFF;
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static UINT g_nMax = 0;
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#endif
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static __forceinline void DoIrqProfiling(DWORD uCycles)
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{
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#ifdef _DEBUG
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if(regs.ps & AF_INTERRUPT)
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return; // Still in Apple's ROM
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g_nCycleIrqEnd = g_nCumulativeCycles + uCycles;
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g_nCycleIrqTime = (UINT) (g_nCycleIrqEnd - g_nCycleIrqStart);
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if(g_nCycleIrqTime > g_nMax) g_nMax = g_nCycleIrqTime;
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if(g_nCycleIrqTime < g_nMin) g_nMin = g_nCycleIrqTime;
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if(g_nIdx == BUFFER_SIZE)
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return;
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g_nBuffer[g_nIdx] = g_nCycleIrqTime;
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g_nIdx++;
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if(g_nIdx == BUFFER_SIZE)
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{
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UINT nTotal = 0;
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for(UINT i=0; i<BUFFER_SIZE; i++)
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nTotal += g_nBuffer[i];
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g_nMean = nTotal / BUFFER_SIZE;
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}
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#endif
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}
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//===========================================================================
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BYTE CpuRead(USHORT addr, ULONG uExecutedCycles)
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{
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return READ;
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}
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void CpuWrite(USHORT addr, BYTE a, ULONG uExecutedCycles)
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{
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WRITE(a);
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}
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//===========================================================================
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#ifdef USE_SPEECH_API
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const USHORT COUT = 0xFDED;
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const UINT OUTPUT_BUFFER_SIZE = 256;
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char g_OutputBuffer[OUTPUT_BUFFER_SIZE+1+1]; // +1 for EOL, +1 for NULL
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UINT OutputBufferIdx = 0;
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bool bEscMode = false;
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void CaptureCOUT(void)
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{
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const char ch = regs.a & 0x7f;
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if (ch == 0x07) // Bell
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{
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// Ignore
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}
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else if (ch == 0x08) // Backspace
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{
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if (OutputBufferIdx)
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OutputBufferIdx--;
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}
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else if (ch == 0x0A) // LF
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{
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// Ignore
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}
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else if (ch == 0x0D) // CR
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{
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if (bEscMode)
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{
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bEscMode = false;
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}
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else if (OutputBufferIdx)
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{
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g_OutputBuffer[OutputBufferIdx] = 0;
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g_Speech.Speak(g_OutputBuffer);
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#ifdef _DEBUG
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g_OutputBuffer[OutputBufferIdx] = '\n';
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g_OutputBuffer[OutputBufferIdx+1] = 0;
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OutputDebugString(g_OutputBuffer);
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#endif
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OutputBufferIdx = 0;
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}
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}
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else if (ch == 0x1B) // Escape
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{
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bEscMode = bEscMode ? false : true; // Toggle mode
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}
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else if (ch >= ' ' && ch <= '~')
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{
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if (OutputBufferIdx < OUTPUT_BUFFER_SIZE && !bEscMode)
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g_OutputBuffer[OutputBufferIdx++] = ch;
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}
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}
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#endif
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//===========================================================================
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//#define DBG_HDD_ENTRYPOINT
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#if defined(_DEBUG) && defined(DBG_HDD_ENTRYPOINT)
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// Output a debug msg whenever the HDD f/w is called or jump to.
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static void DebugHddEntrypoint(const USHORT PC)
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{
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static bool bOldPCAtC7xx = false;
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static WORD OldPC = 0;
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static UINT Count = 0;
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if ((PC >> 8) == 0xC7)
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{
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if (!bOldPCAtC7xx /*&& PC != 0xc70a*/)
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{
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Count++;
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char szDebug[100];
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sprintf(szDebug, "HDD Entrypoint: $%04X\n", PC);
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OutputDebugString(szDebug);
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}
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bOldPCAtC7xx = true;
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}
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else
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{
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bOldPCAtC7xx = false;
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}
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OldPC = PC;
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}
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#endif
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static __forceinline int Fetch(BYTE& iOpcode, ULONG uExecutedCycles)
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{
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const USHORT PC = regs.pc;
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#if defined(_DEBUG) && defined(DBG_HDD_ENTRYPOINT)
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DebugHddEntrypoint(PC);
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#endif
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iOpcode = ((PC & 0xF000) == 0xC000)
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? IORead[(PC>>4) & 0xFF](PC,PC,0,0,uExecutedCycles) // Fetch opcode from I/O memory, but params are still from mem[]
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: *(mem+PC);
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if (IsDebugBreakOpcode( iOpcode ))
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return 0;
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#ifdef USE_SPEECH_API
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if (PC == COUT && g_Speech.IsEnabled() && !g_bFullSpeed)
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CaptureCOUT();
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#endif
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regs.pc++;
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return 1;
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}
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//#define ENABLE_NMI_SUPPORT // Not used - so don't enable
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static __forceinline void NMI(ULONG& uExecutedCycles, UINT& uExtraCycles, BOOL& flagc, BOOL& flagn, BOOL& flagv, BOOL& flagz)
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{
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#ifdef ENABLE_NMI_SUPPORT
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if(g_bNmiFlank)
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{
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// NMI signals are only serviced once
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g_bNmiFlank = FALSE;
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#ifdef _DEBUG
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g_nCycleIrqStart = g_nCumulativeCycles + uExecutedCycles;
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#endif
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PUSH(regs.pc >> 8)
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PUSH(regs.pc & 0xFF)
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EF_TO_AF
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PUSH(regs.ps & ~AF_BREAK)
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regs.ps = regs.ps | AF_INTERRUPT & ~AF_DECIMAL;
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regs.pc = * (WORD*) (mem+0xFFFA);
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CYC(7)
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}
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#endif
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}
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static __forceinline void IRQ(ULONG& uExecutedCycles, UINT& uExtraCycles, BOOL& flagc, BOOL& flagn, BOOL& flagv, BOOL& flagz)
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{
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if(g_bmIRQ && !(regs.ps & AF_INTERRUPT))
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{
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// IRQ signals are deasserted when a specific r/w operation is done on device
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#ifdef _DEBUG
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g_nCycleIrqStart = g_nCumulativeCycles + uExecutedCycles;
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#endif
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PUSH(regs.pc >> 8)
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PUSH(regs.pc & 0xFF)
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EF_TO_AF
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PUSH(regs.ps & ~AF_BREAK)
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regs.ps = regs.ps | AF_INTERRUPT & ~AF_DECIMAL;
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regs.pc = * (WORD*) (mem+0xFFFE);
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CYC(7)
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}
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}
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static __forceinline void CheckInterruptSources(ULONG uExecutedCycles)
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{
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if (g_nIrqCheckTimeout < 0)
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{
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MB_UpdateCycles(uExecutedCycles);
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sg_Mouse.SetVBlank(VideoGetVbl(uExecutedCycles));
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g_nIrqCheckTimeout = IRQ_CHECK_TIMEOUT;
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}
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}
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//===========================================================================
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#include "cpu/cpu6502.h" // MOS 6502
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#include "cpu/cpu65C02.h" // WDC 65C02
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#include "cpu/cpu65d02.h" // Debug CPU Memory Visualizer
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//===========================================================================
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static DWORD InternalCpuExecute (DWORD uTotalCycles)
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{
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if (IS_APPLE2 || (g_Apple2Type == A2TYPE_APPLE2E))
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return Cpu6502(uTotalCycles); // Apple ][, ][+, //e
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else
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return Cpu65C02(uTotalCycles); // Enhanced Apple //e
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}
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//
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// ----- ALL GLOBALLY ACCESSIBLE FUNCTIONS ARE BELOW THIS LINE -----
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//
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//===========================================================================
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void CpuDestroy ()
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{
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if (g_bCritSectionValid)
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{
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DeleteCriticalSection(&g_CriticalSection);
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g_bCritSectionValid = false;
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}
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}
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//===========================================================================
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// Description:
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// Call this when an IO-reg is accessed & accurate cycle info is needed
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// NB. Safe to call multiple times from the same IO function handler (as 'nExecutedCycles - g_nCyclesExecuted' will be zero the 2nd time)
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// Pre:
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// nExecutedCycles = # of cycles executed by Cpu6502() or Cpu65C02() for this iteration of ContinueExecution()
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// Post:
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// g_nCyclesExecuted
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// g_nCumulativeCycles
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//
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void CpuCalcCycles(const ULONG nExecutedCycles)
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{
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// Calc # of cycles executed since this func was last called
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const ULONG nCycles = nExecutedCycles - g_nCyclesExecuted;
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_ASSERT( (LONG)nCycles >= 0 );
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g_nCumulativeCycles += nCycles;
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g_nCyclesExecuted = nExecutedCycles;
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}
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//===========================================================================
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// Old method with g_uInternalExecutedCycles runs faster!
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// Old vs New
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// - 68.0,69.0MHz vs 66.7, 67.2MHz (with check for VBL IRQ every opcode)
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// - 89.6,88.9MHz vs 87.2, 87.9MHz (without check for VBL IRQ)
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// - 75.9, 78.5MHz (with check for VBL IRQ every 128 cycles)
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// - 137.9,135.6MHz (with check for VBL IRQ & MB_Update every 128 cycles)
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#if 0 // TODO: Measure perf increase by using this new method
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ULONG CpuGetCyclesThisVideoFrame(ULONG) // Old func using g_uInternalExecutedCycles
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{
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CpuCalcCycles(g_uInternalExecutedCycles);
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return g_dwCyclesThisFrame + g_nCyclesExecuted;
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}
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#else
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ULONG CpuGetCyclesThisVideoFrame(const ULONG nExecutedCycles)
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{
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CpuCalcCycles(nExecutedCycles);
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return g_dwCyclesThisFrame + g_nCyclesExecuted;
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}
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#endif
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//---------------------------------------------------------------------------
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static DWORD g_dwEmulationTime_ms = 0;
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static void UpdateEmulationTime(const DWORD dwExecutedCycles)
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{
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static DWORD dwEmulationTimeFrac_clks = 0;
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const DWORD CLKS_PER_MS = (DWORD)g_fCurrentCLK6502 / 1000;
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dwEmulationTimeFrac_clks += dwExecutedCycles;
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if (dwEmulationTimeFrac_clks > CLKS_PER_MS)
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{
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g_dwEmulationTime_ms += dwEmulationTimeFrac_clks / CLKS_PER_MS;
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dwEmulationTimeFrac_clks %= CLKS_PER_MS;
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}
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}
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DWORD CpuGetEmulationTime_ms(void)
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{
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return g_dwEmulationTime_ms;
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}
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//===========================================================================
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DWORD CpuExecute(const DWORD uCycles)
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{
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g_nCyclesExecuted = 0;
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MB_StartOfCpuExecute();
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// uCycles:
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// =0 : Do single step
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// >0 : Do multi-opcode emulation
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const DWORD uExecutedCycles = InternalCpuExecute(uCycles);
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MB_UpdateCycles(uExecutedCycles); // Update 6522s (NB. Do this before updating g_nCumulativeCycles below)
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UpdateEmulationTime(uExecutedCycles);
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//
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const UINT nRemainingCycles = uExecutedCycles - g_nCyclesExecuted;
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g_nCumulativeCycles += nRemainingCycles;
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return uExecutedCycles;
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}
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//===========================================================================
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void CpuInitialize ()
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{
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CpuDestroy();
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regs.a = regs.x = regs.y = regs.ps = 0xFF;
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regs.sp = 0x01FF;
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CpuReset(); // Init's ps & pc. Updates sp
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InitializeCriticalSection(&g_CriticalSection);
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g_bCritSectionValid = true;
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CpuIrqReset();
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CpuNmiReset();
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z80mem_initialize();
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z80_reset();
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}
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//===========================================================================
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void CpuSetupBenchmark ()
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{
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regs.a = 0;
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regs.x = 0;
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regs.y = 0;
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regs.pc = 0x300;
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regs.sp = 0x1FF;
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// CREATE CODE SEGMENTS CONSISTING OF GROUPS OF COMMONLY-USED OPCODES
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{
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int addr = 0x300;
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int opcode = 0;
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do
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{
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*(mem+addr++) = benchopcode[opcode];
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*(mem+addr++) = benchopcode[opcode];
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if (opcode >= SHORTOPCODES)
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*(mem+addr++) = 0;
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if ((++opcode >= BENCHOPCODES) || ((addr & 0x0F) >= 0x0B))
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{
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*(mem+addr++) = 0x4C;
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*(mem+addr++) = (opcode >= BENCHOPCODES) ? 0x00 : ((addr >> 4)+1) << 4;
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*(mem+addr++) = 0x03;
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while (addr & 0x0F)
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++addr;
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}
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} while (opcode < BENCHOPCODES);
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}
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}
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//===========================================================================
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void CpuIrqReset()
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{
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_ASSERT(g_bCritSectionValid);
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if (g_bCritSectionValid) EnterCriticalSection(&g_CriticalSection);
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g_bmIRQ = 0;
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if (g_bCritSectionValid) LeaveCriticalSection(&g_CriticalSection);
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}
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void CpuIrqAssert(eIRQSRC Device)
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{
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_ASSERT(g_bCritSectionValid);
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if (g_bCritSectionValid) EnterCriticalSection(&g_CriticalSection);
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g_bmIRQ |= 1<<Device;
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if (g_bCritSectionValid) LeaveCriticalSection(&g_CriticalSection);
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}
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void CpuIrqDeassert(eIRQSRC Device)
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{
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_ASSERT(g_bCritSectionValid);
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if (g_bCritSectionValid) EnterCriticalSection(&g_CriticalSection);
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g_bmIRQ &= ~(1<<Device);
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if (g_bCritSectionValid) LeaveCriticalSection(&g_CriticalSection);
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}
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//===========================================================================
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void CpuNmiReset()
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{
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_ASSERT(g_bCritSectionValid);
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if (g_bCritSectionValid) EnterCriticalSection(&g_CriticalSection);
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g_bmNMI = 0;
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g_bNmiFlank = FALSE;
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if (g_bCritSectionValid) LeaveCriticalSection(&g_CriticalSection);
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}
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void CpuNmiAssert(eIRQSRC Device)
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{
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_ASSERT(g_bCritSectionValid);
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if (g_bCritSectionValid) EnterCriticalSection(&g_CriticalSection);
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if (g_bmNMI == 0) // NMI line is just becoming active
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g_bNmiFlank = TRUE;
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g_bmNMI |= 1<<Device;
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if (g_bCritSectionValid) LeaveCriticalSection(&g_CriticalSection);
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}
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void CpuNmiDeassert(eIRQSRC Device)
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{
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_ASSERT(g_bCritSectionValid);
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if (g_bCritSectionValid) EnterCriticalSection(&g_CriticalSection);
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g_bmNMI &= ~(1<<Device);
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if (g_bCritSectionValid) LeaveCriticalSection(&g_CriticalSection);
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}
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//===========================================================================
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void CpuReset()
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{
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// 7 cycles
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regs.ps = (regs.ps | AF_INTERRUPT) & ~AF_DECIMAL;
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regs.pc = * (WORD*) (mem+0xFFFC);
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regs.sp = 0x0100 | ((regs.sp - 3) & 0xFF);
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regs.bJammed = 0;
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g_ActiveCPU = CPU_6502;
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z80_reset();
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}
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//===========================================================================
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DWORD CpuGetSnapshot(SS_CPU6502* pSS)
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{
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pSS->A = regs.a;
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pSS->X = regs.x;
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pSS->Y = regs.y;
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pSS->P = regs.ps | AF_RESERVED | AF_BREAK;
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pSS->S = (BYTE) (regs.sp & 0xff);
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pSS->PC = regs.pc;
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pSS->g_nCumulativeCycles = g_nCumulativeCycles;
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return 0;
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}
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DWORD CpuSetSnapshot(SS_CPU6502* pSS)
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{
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regs.a = pSS->A;
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regs.x = pSS->X;
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regs.y = pSS->Y;
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regs.ps = pSS->P | AF_RESERVED | AF_BREAK;
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regs.sp = (USHORT)pSS->S | 0x100;
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regs.pc = pSS->PC;
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CpuIrqReset();
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CpuNmiReset();
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g_nCumulativeCycles = pSS->g_nCumulativeCycles;
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return 0;
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}
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