mirror of
https://github.com/AppleWin/AppleWin.git
synced 2024-12-24 07:30:24 +00:00
6051bc55d0
Changes to ease code compilation in GCC. Disk_t and HDD contain a std::string and for this reason they need a proper constructor, ZeroMemory is not guaranteed to work.
1271 lines
26 KiB
C++
1271 lines
26 KiB
C++
#include "stdafx.h"
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#include "../../source/Applewin.h"
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#include "../../source/CPU.h"
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#include "../../source/Memory.h"
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// From Applewin.cpp
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bool g_bFullSpeed = false;
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enum AppMode_e g_nAppMode = MODE_RUNNING;
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// From Memory.cpp
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LPBYTE memwrite[0x100]; // TODO: Init
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LPBYTE mem = NULL; // TODO: Init
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LPBYTE memdirty = NULL; // TODO: Init
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iofunction IORead[256] = {0}; // TODO: Init
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iofunction IOWrite[256] = {0}; // TODO: Init
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// From CPU.cpp
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#define AF_SIGN 0x80
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#define AF_OVERFLOW 0x40
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#define AF_RESERVED 0x20
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#define AF_BREAK 0x10
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#define AF_DECIMAL 0x08
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#define AF_INTERRUPT 0x04
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#define AF_ZERO 0x02
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#define AF_CARRY 0x01
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regsrec regs;
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static const int IRQ_CHECK_TIMEOUT = 128;
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static signed int g_nIrqCheckTimeout = IRQ_CHECK_TIMEOUT;
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static eCpuType g_ActiveCPU = CPU_65C02;
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eCpuType GetActiveCpu(void)
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{
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return g_ActiveCPU;
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}
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bool g_bStopOnBRK = false;
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static __forceinline int Fetch(BYTE& iOpcode, ULONG uExecutedCycles)
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{
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iOpcode = *(mem+regs.pc);
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regs.pc++;
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if (iOpcode == 0x00 && g_bStopOnBRK)
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return 0;
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return 1;
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}
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static __forceinline void DoIrqProfiling(DWORD uCycles)
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{
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}
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static __forceinline void CheckInterruptSources(ULONG uExecutedCycles)
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{
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}
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static __forceinline void NMI(ULONG& uExecutedCycles, BOOL& flagc, BOOL& flagn, BOOL& flagv, BOOL& flagz)
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{
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}
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static __forceinline void IRQ(ULONG& uExecutedCycles, BOOL& flagc, BOOL& flagn, BOOL& flagv, BOOL& flagz)
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{
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}
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// From z80.cpp
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DWORD z80_mainloop(ULONG uTotalCycles, ULONG uExecutedCycles)
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{
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return 0;
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}
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// From NTSC.cpp
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void NTSC_VideoUpdateCycles( long cycles6502 )
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{
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}
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//-------------------------------------
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#include "../../source/CPU/cpu_general.inl"
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#include "../../source/CPU/cpu_instructions.inl"
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#include "../../source/CPU/cpu6502.h" // MOS 6502
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#include "../../source/CPU/cpu65C02.h" // WDC 65C02
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void init(void)
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{
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mem = (LPBYTE)VirtualAlloc(NULL,64*1024,MEM_COMMIT,PAGE_READWRITE);
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for (UINT i=0; i<256; i++)
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memwrite[i] = mem+i*256;
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memdirty = new BYTE[256];
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}
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void reset(void)
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{
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regs.a = 0;
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regs.x = 0;
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regs.y = 0;
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regs.pc = 0x300;
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regs.sp = 0x1FF;
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regs.ps = 0;
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regs.bJammed = 0;
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}
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//-------------------------------------
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DWORD TestCpu6502(DWORD uTotalCycles)
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{
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return Cpu6502(uTotalCycles, true);
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}
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DWORD TestCpu65C02(DWORD uTotalCycles)
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{
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return Cpu65C02(uTotalCycles, true);
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}
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//-------------------------------------
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int GH264_test(void)
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{
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// No page-cross
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reset();
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regs.pc = 0x300;
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WORD abs = regs.pc+3;
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WORD dst = abs+2;
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mem[regs.pc+0] = 0x6c; // JMP (IND)
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mem[regs.pc+1] = abs&0xff;
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mem[regs.pc+2] = abs>>8;
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mem[regs.pc+3] = dst&0xff;
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mem[regs.pc+4] = dst>>8;
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DWORD cycles = TestCpu6502(0);
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if (cycles != 5) return 1;
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if (regs.pc != dst) return 1;
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reset();
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cycles = TestCpu65C02(0);
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if (cycles != 6) return 1;
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if (regs.pc != dst) return 1;
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// Page-cross
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reset();
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regs.pc = 0x3fc; // 3FC: JMP (abs)
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abs = regs.pc+3; // 3FF: lo(dst), hi(dst)
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dst = abs+2;
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mem[regs.pc+0] = 0x6c; // JMP (IND)
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mem[regs.pc+1] = abs&0xff;
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mem[regs.pc+2] = abs>>8;
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mem[regs.pc+3] = dst&0xff;
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mem[regs.pc+4] = mem[regs.pc & ~0xff] = dst>>8; // Allow for bug in 6502
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cycles = TestCpu6502(0);
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if (cycles != 5) return 1;
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if (regs.pc != dst) return 1;
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reset();
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regs.pc = 0x3fc;
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mem[regs.pc & ~0xff] = 0; // Test that 65C02 fixes the bug in the 6502
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cycles = TestCpu65C02(0);
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if (cycles != 7) return 1; // todo: is this 6 or 7?
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if (regs.pc != dst) return 1;
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return 0;
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}
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//-------------------------------------
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void ASL_ABSX(BYTE x, WORD base, BYTE d)
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{
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WORD addr = base+x;
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mem[addr] = d;
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reset();
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regs.x = x;
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mem[regs.pc+0] = 0x1e;
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mem[regs.pc+1] = base&0xff;
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mem[regs.pc+2] = base>>8;
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}
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void DEC_ABSX(BYTE x, WORD base, BYTE d)
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{
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WORD addr = base+x;
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mem[addr] = d;
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reset();
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regs.x = x;
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mem[regs.pc+0] = 0xde;
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mem[regs.pc+1] = base&0xff;
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mem[regs.pc+2] = base>>8;
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}
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void INC_ABSX(BYTE x, WORD base, BYTE d)
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{
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WORD addr = base+x;
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mem[addr] = d;
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reset();
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regs.x = x;
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mem[regs.pc+0] = 0xfe;
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mem[regs.pc+1] = base&0xff;
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mem[regs.pc+2] = base>>8;
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}
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int GH271_test(void)
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{
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// asl abs,x
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{
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const WORD base = 0x20ff;
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const BYTE d = 0x40;
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// no page-cross
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{
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const BYTE x = 0;
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ASL_ABSX(x, base, d);
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if (TestCpu6502(0) != 7) return 1;
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if (mem[base+x] != ((d<<1)&0xff)) return 1;
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ASL_ABSX(x, base, d);
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if (TestCpu65C02(0) != 6) return 1; // Non-PX case is optimised on 65C02
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if (mem[base+x] != ((d<<1)&0xff)) return 1;
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}
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// page-cross
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{
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const BYTE x = 1;
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ASL_ABSX(x, base, d);
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if (TestCpu6502(0) != 7) return 1;
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if (mem[base+x] != ((d<<1)&0xff)) return 1;
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ASL_ABSX(x, base, d);
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if (TestCpu65C02(0) != 7) return 1;
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if (mem[base+x] != ((d<<1)&0xff)) return 1;
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}
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}
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// dec abs,x
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{
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const WORD base = 0x20ff;
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const BYTE d = 0x40;
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// no page-cross
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{
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const BYTE x = 0;
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DEC_ABSX(x, base, d);
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if (TestCpu6502(0) != 7) return 1;
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if (mem[base+x] != ((d-1)&0xff)) return 1;
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DEC_ABSX(x, base, d);
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if (TestCpu65C02(0) != 7) return 1; // NB. Not optimised for 65C02
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if (mem[base+x] != ((d-1)&0xff)) return 1;
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}
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// page-cross
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{
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const BYTE x = 1;
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DEC_ABSX(x, base, d);
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if (TestCpu6502(0) != 7) return 1;
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if (mem[base+x] != ((d-1)&0xff)) return 1;
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DEC_ABSX(x, base, d);
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if (TestCpu65C02(0) != 7) return 1;
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if (mem[base+x] != ((d-1)&0xff)) return 1;
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}
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}
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// inc abs,x
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{
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const WORD base = 0x20ff;
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const BYTE d = 0x40;
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// no page-cross
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{
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const BYTE x = 0;
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INC_ABSX(x, base, d);
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if (TestCpu6502(0) != 7) return 1;
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if (mem[base+x] != ((d+1)&0xff)) return 1;
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INC_ABSX(x, base, d);
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if (TestCpu65C02(0) != 7) return 1; // NB. Not optimised for 65C02
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if (mem[base+x] != ((d+1)&0xff)) return 1;
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}
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// page-cross
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{
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const BYTE x = 1;
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INC_ABSX(x, base, d);
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if (TestCpu6502(0) != 7) return 1;
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if (mem[base+x] != ((d+1)&0xff)) return 1;
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INC_ABSX(x, base, d);
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if (TestCpu65C02(0) != 7) return 1;
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if (mem[base+x] != ((d+1)&0xff)) return 1;
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}
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}
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return 0;
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}
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//-------------------------------------
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enum {CYC_6502=0, CYC_6502_PX, CYC_65C02, CYC_65C02_PX};
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const BYTE g_OpcodeTimings[256][4] =
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{
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// 6502 (no page-cross), 6502 (page-cross), 65C02 (no page-cross), 65C02 (page-cross)
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{7,7,7,7}, // 00
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{6,6,6,6}, // 01
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{2,2,2,2}, // 02
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{8,8,1,1}, // 03
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{3,3,5,5}, // 04
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{3,3,3,3}, // 05
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{5,5,5,5}, // 06
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{5,5,1,1}, // 07
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{3,3,3,3}, // 08
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{2,2,2,2}, // 09
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{2,2,2,2}, // 0A
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{2,2,1,1}, // 0B
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{4,5,6,6}, // 0C
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{4,4,4,4}, // 0D
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{6,6,6,6}, // 0E
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{6,6,1,1}, // 0F
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{3,3,3,3}, // 10
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{5,6,5,6}, // 11
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{2,2,5,5}, // 12
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{8,8,1,1}, // 13
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{4,4,5,5}, // 14
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{4,4,4,4}, // 15
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{6,6,6,6}, // 16
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{6,6,1,1}, // 17
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{2,2,2,2}, // 18
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{4,5,4,5}, // 19
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{2,2,2,2}, // 1A
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{7,7,1,1}, // 1B
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{4,5,6,6}, // 1C
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{4,5,4,5}, // 1D
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{7,7,6,7}, // 1E
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{7,7,1,1}, // 1F
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{6,6,6,6}, // 20
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{6,6,6,6}, // 21
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{2,2,2,2}, // 22
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{8,8,1,1}, // 23
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{3,3,3,3}, // 24
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{3,3,3,3}, // 25
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{5,5,5,5}, // 26
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{5,5,1,1}, // 27
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{4,4,4,4}, // 28
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{2,2,2,2}, // 29
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{2,2,2,2}, // 2A
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{2,2,1,1}, // 2B
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{4,4,4,4}, // 2C
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{4,4,4,4}, // 2D
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{6,6,6,6}, // 2E
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{6,6,1,1}, // 2F
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{2,2,2,2}, // 30
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{5,6,5,6}, // 31
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{2,2,5,5}, // 32
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{8,8,1,1}, // 33
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{4,4,4,4}, // 34
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{4,4,4,4}, // 35
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{6,6,6,6}, // 36
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{6,6,1,1}, // 37
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{2,2,2,2}, // 38
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{4,5,4,5}, // 39
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{2,2,2,2}, // 3A
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{7,7,1,1}, // 3B
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{4,5,4,5}, // 3C
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{4,5,4,5}, // 3D
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{6,6,6,7}, // 3E
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{7,7,1,1}, // 3F
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{6,6,6,6}, // 40
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{6,6,6,6}, // 41
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{2,2,2,2}, // 42
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{8,8,1,1}, // 43
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{3,3,3,3}, // 44
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{3,3,3,3}, // 45
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{5,5,5,5}, // 46
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{5,5,1,1}, // 47
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{3,3,3,3}, // 48
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{2,2,2,2}, // 49
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{2,2,2,2}, // 4A
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{2,2,1,1}, // 4B
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{3,3,3,3}, // 4C
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{4,4,4,4}, // 4D
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{6,6,6,6}, // 4E
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{6,6,1,1}, // 4F
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{3,3,3,3}, // 50
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{5,6,5,6}, // 51
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{2,2,5,5}, // 52
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{8,8,1,1}, // 53
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{4,4,4,4}, // 54
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{4,4,4,4}, // 55
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{6,6,6,6}, // 56
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{6,6,1,1}, // 57
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{2,2,2,2}, // 58
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{4,5,4,5}, // 59
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{2,2,3,3}, // 5A
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{7,7,1,1}, // 5B
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{4,5,8,8}, // 5C
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{4,5,4,5}, // 5D
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{6,6,6,7}, // 5E
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{7,7,1,1}, // 5F
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{6,6,6,6}, // 60
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{6,6,6,6}, // 61
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{2,2,2,2}, // 62
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{8,8,1,1}, // 63
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{3,3,3,3}, // 64
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{3,3,3,3}, // 65
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{5,5,5,5}, // 66
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{5,5,1,1}, // 67
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{4,4,4,4}, // 68
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{2,2,2,2}, // 69
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{2,2,2,2}, // 6A
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{2,2,1,1}, // 6B
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{5,5,7,7}, // 6C
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{4,4,4,4}, // 6D
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{6,6,6,6}, // 6E
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{6,6,1,1}, // 6F
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{2,2,2,2}, // 70
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{5,6,5,6}, // 71
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{2,2,5,5}, // 72
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{8,8,1,1}, // 73
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{4,4,4,4}, // 74
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{4,4,4,4}, // 75
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{6,6,6,6}, // 76
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{6,6,1,1}, // 77
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{2,2,2,2}, // 78
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{4,5,4,5}, // 79
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{2,2,4,4}, // 7A
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{7,7,1,1}, // 7B
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{4,5,6,6}, // 7C
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{4,5,4,5}, // 7D
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{6,6,6,7}, // 7E
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{7,7,1,1}, // 7F
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{2,2,3,3}, // 80
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{6,6,6,6}, // 81
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{2,2,2,2}, // 82
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{6,6,1,1}, // 83
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{3,3,3,3}, // 84
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{3,3,3,3}, // 85
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{3,3,3,3}, // 86
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{3,3,1,1}, // 87
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{2,2,2,2}, // 88
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{2,2,2,2}, // 89
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{2,2,2,2}, // 8A
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{2,2,1,1}, // 8B
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{4,4,4,4}, // 8C
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{4,4,4,4}, // 8D
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{4,4,4,4}, // 8E
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{4,4,1,1}, // 8F
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{3,3,3,3}, // 90
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{6,6,6,6}, // 91
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{2,2,5,5}, // 92
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{6,6,1,1}, // 93
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{4,4,4,4}, // 94
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{4,4,4,4}, // 95
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{4,4,4,4}, // 96
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{4,4,1,1}, // 97
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{2,2,2,2}, // 98
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{5,5,5,5}, // 99
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{2,2,2,2}, // 9A
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{5,5,1,1}, // 9B
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{5,5,4,4}, // 9C
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{5,5,5,5}, // 9D
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{5,5,5,5}, // 9E
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{5,5,1,1}, // 9F
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{2,2,2,2}, // A0
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{6,6,6,6}, // A1
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{2,2,2,2}, // A2
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{6,6,1,1}, // A3
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{3,3,3,3}, // A4
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{3,3,3,3}, // A5
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{3,3,3,3}, // A6
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{3,3,1,1}, // A7
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{2,2,2,2}, // A8
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{2,2,2,2}, // A9
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{2,2,2,2}, // AA
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{2,2,1,1}, // AB
|
|
{4,4,4,4}, // AC
|
|
{4,4,4,4}, // AD
|
|
{4,4,4,4}, // AE
|
|
{4,4,1,1}, // AF
|
|
{2,2,2,2}, // B0
|
|
{5,6,5,6}, // B1
|
|
{2,2,5,5}, // B2
|
|
{5,6,1,1}, // B3
|
|
{4,4,4,4}, // B4
|
|
{4,4,4,4}, // B5
|
|
{4,4,4,4}, // B6
|
|
{4,4,1,1}, // B7
|
|
{2,2,2,2}, // B8
|
|
{4,5,4,5}, // B9
|
|
{2,2,2,2}, // BA
|
|
{4,5,1,1}, // BB
|
|
{4,5,4,5}, // BC
|
|
{4,5,4,5}, // BD
|
|
{4,5,4,5}, // BE
|
|
{4,5,1,1}, // BF
|
|
{2,2,2,2}, // C0
|
|
{6,6,6,6}, // C1
|
|
{2,2,2,2}, // C2
|
|
{8,8,1,1}, // C3
|
|
{3,3,3,3}, // C4
|
|
{3,3,3,3}, // C5
|
|
{5,5,5,5}, // C6
|
|
{5,5,1,1}, // C7
|
|
{2,2,2,2}, // C8
|
|
{2,2,2,2}, // C9
|
|
{2,2,2,2}, // CA
|
|
{2,2,1,1}, // CB
|
|
{4,4,4,4}, // CC
|
|
{4,4,4,4}, // CD
|
|
{6,6,6,6}, // CE
|
|
{6,6,1,1}, // CF
|
|
{3,3,3,3}, // D0
|
|
{5,6,5,6}, // D1
|
|
{2,2,5,5}, // D2
|
|
{8,8,1,1}, // D3
|
|
{4,4,4,4}, // D4
|
|
{4,4,4,4}, // D5
|
|
{6,6,6,6}, // D6
|
|
{6,6,1,1}, // D7
|
|
{2,2,2,2}, // D8
|
|
{4,5,4,5}, // D9
|
|
{2,2,3,3}, // DA
|
|
{7,7,1,1}, // DB
|
|
{4,5,4,4}, // DC
|
|
{4,5,4,5}, // DD
|
|
{7,7,7,7}, // DE
|
|
{7,7,1,1}, // DF
|
|
{2,2,2,2}, // E0
|
|
{6,6,6,6}, // E1
|
|
{2,2,2,2}, // E2
|
|
{8,8,1,1}, // E3
|
|
{3,3,3,3}, // E4
|
|
{3,3,3,3}, // E5
|
|
{5,5,5,5}, // E6
|
|
{5,5,1,1}, // E7
|
|
{2,2,2,2}, // E8
|
|
{2,2,2,2}, // E9
|
|
{2,2,2,2}, // EA
|
|
{2,2,1,1}, // EB
|
|
{4,4,4,4}, // EC
|
|
{4,4,4,4}, // ED
|
|
{6,6,6,6}, // EE
|
|
{6,6,1,1}, // EF
|
|
{2,2,2,2}, // F0
|
|
{5,6,5,6}, // F1
|
|
{2,2,5,5}, // F2
|
|
{8,8,1,1}, // F3
|
|
{4,4,4,4}, // F4
|
|
{4,4,4,4}, // F5
|
|
{6,6,6,6}, // F6
|
|
{6,6,1,1}, // F7
|
|
{2,2,2,2}, // F8
|
|
{4,5,4,5}, // F9
|
|
{2,2,4,4}, // FA
|
|
{7,7,1,1}, // FB
|
|
{4,5,4,4}, // FC
|
|
{4,5,4,5}, // FD
|
|
{7,7,7,7}, // FE
|
|
{7,7,1,1}, // FF
|
|
};
|
|
|
|
int GH278_Bcc_Sub(BYTE op, BYTE ps_not_taken, BYTE ps_taken, WORD pc)
|
|
{
|
|
mem[pc+0] = op;
|
|
mem[pc+1] = 0x01;
|
|
const WORD dst_not_taken = pc+2;
|
|
const WORD dst_taken = pc+2 + mem[pc+1];
|
|
|
|
const int pagecross = (((pc+2) ^ dst_taken) >> 8) & 1;
|
|
|
|
// 6502
|
|
|
|
reset();
|
|
regs.pc = pc;
|
|
regs.ps = ps_not_taken;
|
|
if (TestCpu6502(0) != 2) return 1;
|
|
if (regs.pc != dst_not_taken) return 1;
|
|
|
|
reset();
|
|
regs.pc = pc;
|
|
regs.ps = ps_taken;
|
|
if (TestCpu6502(0) != 3+pagecross) return 1;
|
|
if (regs.pc != dst_taken) return 1;
|
|
|
|
// 65C02
|
|
|
|
reset();
|
|
regs.pc = pc;
|
|
regs.ps = ps_not_taken;
|
|
if (TestCpu65C02(0) != 2) return 1;
|
|
if (regs.pc != dst_not_taken) return 1;
|
|
|
|
reset();
|
|
regs.pc = pc;
|
|
regs.ps = ps_taken;
|
|
if (TestCpu65C02(0) != 3+pagecross) return 1;
|
|
if (regs.pc != dst_taken) return 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int GH278_Bcc(BYTE op, BYTE ps_not_taken, BYTE ps_taken)
|
|
{
|
|
if (GH278_Bcc_Sub(op, ps_not_taken, ps_taken, 0x300)) return 1; // no page cross
|
|
if (GH278_Bcc_Sub(op, ps_not_taken, ps_taken, 0x3FD)) return 1; // page cross
|
|
|
|
return 0;
|
|
}
|
|
|
|
int GH278_BRA(void)
|
|
{
|
|
// No page-cross
|
|
{
|
|
WORD pc = 0x300;
|
|
mem[pc+0] = 0x80; // BRA
|
|
mem[pc+1] = 0x01;
|
|
const WORD dst_taken = pc+2 + mem[pc+1];
|
|
|
|
reset();
|
|
regs.pc = pc;
|
|
if (TestCpu65C02(0) != 3) return 1;
|
|
if (regs.pc != dst_taken) return 1;
|
|
}
|
|
|
|
// Page-cross
|
|
{
|
|
WORD pc = 0x3FD;
|
|
mem[pc+0] = 0x80; // BRA
|
|
mem[pc+1] = 0x01;
|
|
const WORD dst_taken = pc+2 + mem[pc+1];
|
|
|
|
reset();
|
|
regs.pc = pc;
|
|
if (TestCpu65C02(0) != 4) return 1;
|
|
if (regs.pc != dst_taken) return 1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int GH278_JMP_INDX(void)
|
|
{
|
|
// No page-cross
|
|
reset();
|
|
regs.pc = 0x300;
|
|
WORD abs = regs.pc+3;
|
|
WORD dst = abs+2;
|
|
mem[regs.pc+0] = 0x7c; // JMP (IND,X)
|
|
mem[regs.pc+1] = abs&0xff;
|
|
mem[regs.pc+2] = abs>>8;
|
|
mem[regs.pc+3] = dst&0xff;
|
|
mem[regs.pc+4] = dst>>8;
|
|
|
|
DWORD cycles = TestCpu65C02(0);
|
|
if (cycles != 6) return 1;
|
|
if (regs.pc != dst) return 1;
|
|
|
|
// Page-cross (case 1)
|
|
reset();
|
|
regs.pc = 0x3fc;
|
|
abs = regs.pc+3;
|
|
dst = abs+2;
|
|
mem[regs.pc+0] = 0x7c; // JMP (IND,X)
|
|
mem[regs.pc+1] = abs&0xff;
|
|
mem[regs.pc+2] = abs>>8;
|
|
mem[regs.pc+3] = dst&0xff;
|
|
mem[regs.pc+4] = dst>>8;
|
|
|
|
cycles = TestCpu65C02(0);
|
|
if (cycles != 6) return 1; // todo: is this 6 or 7?
|
|
if (regs.pc != dst) return 1;
|
|
|
|
// Page-cross (case 2)
|
|
reset();
|
|
regs.x = 1;
|
|
regs.pc = 0x3fa;
|
|
abs = regs.pc+3;
|
|
dst = abs+2 + regs.x;
|
|
mem[regs.pc+0] = 0x7c; // JMP (IND,X)
|
|
mem[regs.pc+1] = abs&0xff;
|
|
mem[regs.pc+2] = abs>>8;
|
|
mem[regs.pc+3] = 0xcc; // unused
|
|
mem[regs.pc+4] = dst&0xff;
|
|
mem[regs.pc+5] = dst>>8;
|
|
|
|
cycles = TestCpu65C02(0);
|
|
if (cycles != 6) return 1; // todo: is this 6 or 7?
|
|
if (regs.pc != dst) return 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int GH278_ADC_SBC(UINT op)
|
|
{
|
|
const WORD base = 0x20ff;
|
|
reset();
|
|
mem[regs.pc+0] = op;
|
|
mem[regs.pc+1] = base&0xff;
|
|
mem[regs.pc+2] = base>>8;
|
|
mem[0xff] = 0xff; mem[0x00] = 0x00; // For: OPCODE (zp),Y
|
|
|
|
// No page-cross
|
|
reset();
|
|
regs.ps = AF_DECIMAL;
|
|
DWORD cycles = TestCpu6502(0);
|
|
if (g_OpcodeTimings[op][CYC_6502] != cycles) return 1;
|
|
|
|
reset();
|
|
regs.ps = AF_DECIMAL;
|
|
cycles = TestCpu65C02(0);
|
|
if (g_OpcodeTimings[op][CYC_65C02]+1 != cycles) return 1; // CMOS is +1 cycles in decimal mode
|
|
|
|
// Page-cross
|
|
reset();
|
|
regs.ps = AF_DECIMAL;
|
|
regs.x = 1;
|
|
regs.y = 1;
|
|
cycles = TestCpu6502(0);
|
|
if (g_OpcodeTimings[op][CYC_6502_PX] != cycles) return 1;
|
|
|
|
reset();
|
|
regs.ps = AF_DECIMAL;
|
|
regs.x = 1;
|
|
regs.y = 1;
|
|
cycles = TestCpu65C02(0);
|
|
if (g_OpcodeTimings[op][CYC_65C02_PX]+1 != cycles) return 1; // CMOS is +1 cycles in decimal mode
|
|
|
|
return 0;
|
|
}
|
|
|
|
int GH278_ADC(void)
|
|
{
|
|
const BYTE adc[] = {0x61,0x65,0x69,0x6D,0x71,0x72,0x75,0x79,0x7D};
|
|
|
|
for (UINT i = 0; i<sizeof(adc); i++)
|
|
{
|
|
if (GH278_ADC_SBC(adc[i])) return 1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int GH278_SBC(void)
|
|
{
|
|
const BYTE sbc[] = {0xE1,0xE5,0xE9,0xED,0xF1,0xF2,0xF5,0xF9,0xFD};
|
|
|
|
for (UINT i = 0; i<sizeof(sbc); i++)
|
|
{
|
|
if (GH278_ADC_SBC(sbc[i])) return 1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int GH278_test(void)
|
|
{
|
|
int variant = 0;
|
|
|
|
//
|
|
// 6502
|
|
//
|
|
|
|
// No page-cross
|
|
for (UINT op=0; op<256; op++)
|
|
{
|
|
reset();
|
|
WORD base = 0x20ff;
|
|
mem[regs.pc+0] = op;
|
|
mem[regs.pc+1] = base&0xff;
|
|
mem[regs.pc+2] = base>>8;
|
|
DWORD cycles = TestCpu6502(0);
|
|
if (g_OpcodeTimings[op][variant] != cycles) return 1;
|
|
}
|
|
|
|
variant++;
|
|
|
|
// Page-cross
|
|
for (UINT op=0; op<256; op++)
|
|
{
|
|
reset();
|
|
regs.x = 1;
|
|
regs.y = 1;
|
|
WORD base = 0x20ff;
|
|
mem[regs.pc+0] = op;
|
|
mem[regs.pc+1] = base&0xff;
|
|
mem[regs.pc+2] = base>>8;
|
|
mem[0xff] = 0xff; mem[0x00] = 0x00; // For: OPCODE (zp),Y
|
|
DWORD cycles = TestCpu6502(0);
|
|
if (g_OpcodeTimings[op][variant] != cycles) return 1;
|
|
}
|
|
|
|
variant++;
|
|
|
|
//
|
|
// 65C02
|
|
//
|
|
|
|
// No page-cross
|
|
for (UINT op=0; op<256; op++)
|
|
{
|
|
reset();
|
|
WORD base = 0x20ff;
|
|
mem[regs.pc+0] = op;
|
|
mem[regs.pc+1] = base&0xff;
|
|
mem[regs.pc+2] = base>>8;
|
|
DWORD cycles = TestCpu65C02(0);
|
|
if (g_OpcodeTimings[op][variant] != cycles) return 1;
|
|
}
|
|
|
|
variant++;
|
|
|
|
// Page-cross
|
|
for (UINT op=0; op<256; op++)
|
|
{
|
|
reset();
|
|
regs.x = 1;
|
|
regs.y = 1;
|
|
WORD base = 0x20ff;
|
|
mem[regs.pc+0] = op;
|
|
mem[regs.pc+1] = base&0xff;
|
|
mem[regs.pc+2] = base>>8;
|
|
mem[0xff] = 0xff; mem[0x00] = 0x00; // For: OPCODE (zp),Y
|
|
DWORD cycles = TestCpu65C02(0);
|
|
if (g_OpcodeTimings[op][variant] != cycles) return 1;
|
|
}
|
|
|
|
//
|
|
// Bcc
|
|
//
|
|
|
|
if (GH278_Bcc(0x10, AF_SIGN, 0)) return 1; // BPL
|
|
if (GH278_Bcc(0x30, 0, AF_SIGN)) return 1; // BMI
|
|
if (GH278_Bcc(0x50, AF_OVERFLOW, 0)) return 1; // BVC
|
|
if (GH278_Bcc(0x70, 0, AF_OVERFLOW)) return 1; // BVS
|
|
if (GH278_Bcc(0x90, AF_CARRY, 0)) return 1; // BCC
|
|
if (GH278_Bcc(0xB0, 0, AF_CARRY)) return 1; // BCS
|
|
if (GH278_Bcc(0xD0, AF_ZERO, 0)) return 1; // BNE
|
|
if (GH278_Bcc(0xF0, 0, AF_ZERO)) return 1; // BEQ
|
|
if (GH278_BRA()) return 1; // BRA
|
|
|
|
//
|
|
// JMP (IND) and JMP (IND,X)
|
|
// . NB. GH264_test() tests JMP (IND)
|
|
//
|
|
|
|
if (GH278_JMP_INDX()) return 1;
|
|
|
|
//
|
|
// ADC/SBC CMOS decimal mode is +1 cycles
|
|
//
|
|
|
|
if (GH278_ADC()) return 1;
|
|
if (GH278_SBC()) return 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
//-------------------------------------
|
|
|
|
DWORD AXA_ZPY(BYTE a, BYTE x, BYTE y, WORD base)
|
|
{
|
|
reset();
|
|
mem[0xfe] = base&0xff;
|
|
mem[0xff] = base>>8;
|
|
regs.a = a;
|
|
regs.x = x;
|
|
regs.y = y;
|
|
mem[regs.pc+0] = 0x93;
|
|
mem[regs.pc+1] = 0xfe;
|
|
return TestCpu6502(0);
|
|
}
|
|
|
|
DWORD AXA_ABSY(BYTE a, BYTE x, BYTE y, WORD base)
|
|
{
|
|
reset();
|
|
regs.a = a;
|
|
regs.x = x;
|
|
regs.y = y;
|
|
mem[regs.pc+0] = 0x9f;
|
|
mem[regs.pc+1] = base&0xff;
|
|
mem[regs.pc+2] = base>>8;
|
|
return TestCpu6502(0);
|
|
}
|
|
|
|
DWORD SAY_ABSX(BYTE a, BYTE x, BYTE y, WORD base)
|
|
{
|
|
reset();
|
|
regs.a = a;
|
|
regs.x = x;
|
|
regs.y = y;
|
|
mem[regs.pc+0] = 0x9c;
|
|
mem[regs.pc+1] = base&0xff;
|
|
mem[regs.pc+2] = base>>8;
|
|
return TestCpu6502(0);
|
|
}
|
|
|
|
DWORD TAS_ABSY(BYTE a, BYTE x, BYTE y, WORD base)
|
|
{
|
|
reset();
|
|
regs.a = a;
|
|
regs.x = x;
|
|
regs.y = y;
|
|
mem[regs.pc+0] = 0x9b;
|
|
mem[regs.pc+1] = base&0xff;
|
|
mem[regs.pc+2] = base>>8;
|
|
return TestCpu6502(0);
|
|
}
|
|
|
|
DWORD XAS_ABSY(BYTE a, BYTE x, BYTE y, WORD base)
|
|
{
|
|
reset();
|
|
regs.a = a;
|
|
regs.x = x;
|
|
regs.y = y;
|
|
mem[regs.pc+0] = 0x9e;
|
|
mem[regs.pc+1] = base&0xff;
|
|
mem[regs.pc+2] = base>>8;
|
|
return TestCpu6502(0);
|
|
}
|
|
|
|
int GH282_test(void)
|
|
{
|
|
// axa (zp),y
|
|
{
|
|
WORD base = 0x20ff, addr = 0x20ff;
|
|
mem[addr] = 0xcc;
|
|
BYTE a = 0xea, x = 0xff, y = 0;
|
|
DWORD cycles = AXA_ZPY(a, x, y, base);
|
|
if (cycles != 6) return 1;
|
|
if (mem[addr] != (a & x & ((base>>8)+1))) return 1;
|
|
}
|
|
|
|
// axa (zp),y (page-cross)
|
|
{
|
|
WORD base = 0x20ff, addr = 0x2000;
|
|
mem[addr] = 0xcc;
|
|
BYTE a = 0xea, x = 0xff, y = 1;
|
|
DWORD cycles = AXA_ZPY(a, x, y, base);
|
|
if (cycles != 6) return 1;
|
|
if (mem[addr] != (a & x & ((base>>8)+1))) return 1;
|
|
}
|
|
|
|
//
|
|
|
|
// axa abs,y
|
|
{
|
|
WORD base = 0x20ff, addr = 0x20ff;
|
|
mem[addr] = 0xcc;
|
|
BYTE a = 0xea, x = 0xff, y = 0;
|
|
DWORD cycles = AXA_ABSY(a, x, y, base);
|
|
if (cycles != 5) return 1;
|
|
if (mem[addr] != (a & x & ((base>>8)+1))) return 1;
|
|
}
|
|
|
|
// axa abs,y (page-cross)
|
|
{
|
|
WORD base = 0x20ff, addr = 0x2000;
|
|
mem[addr] = 0xcc;
|
|
BYTE a = 0xea, x = 0xff, y = 1;
|
|
DWORD cycles = AXA_ABSY(a, x, y, base);
|
|
if (cycles != 5) return 1;
|
|
if (mem[addr] != (a & x & ((base>>8)+1))) return 1;
|
|
}
|
|
|
|
//
|
|
|
|
// say abs,x
|
|
{
|
|
WORD base = 0x20ff, addr = 0x20ff;
|
|
mem[addr] = 0xcc;
|
|
BYTE a = 0xea, x = 0, y=0x20;
|
|
DWORD cycles = SAY_ABSX(a, x, y, base);
|
|
if (cycles != 5) return 1;
|
|
if (mem[addr] != (y & ((base>>8)+1))) return 1;
|
|
}
|
|
|
|
// say abs,x (page-cross)
|
|
{
|
|
WORD base = 0x20ff, addr = 0x2000;
|
|
mem[addr] = 0xcc;
|
|
BYTE a = 0xea, x = 1, y=0x20;
|
|
DWORD cycles = SAY_ABSX(a, x, y, base);
|
|
if (cycles != 5) return 1;
|
|
if (mem[addr] != (y & ((base>>8)+1))) return 1;
|
|
}
|
|
|
|
//
|
|
|
|
// tas abs,y
|
|
{
|
|
WORD base = 0x20ff, addr = 0x20ff;
|
|
mem[addr] = 0xcc;
|
|
BYTE a = 0xea, x = 0xff, y = 0;
|
|
DWORD cycles = TAS_ABSY(a, x, y, base);
|
|
if (cycles != 5) return 1;
|
|
if (mem[addr] != (a & x & ((base>>8)+1))) return 1;
|
|
if (regs.sp != (0x100 | (a & x))) return 1;
|
|
}
|
|
|
|
// tas abs,y (page-cross)
|
|
{
|
|
WORD base = 0x20ff, addr = 0x2000;
|
|
mem[addr] = 0xcc;
|
|
BYTE a = 0xea, x = 0xff, y = 1;
|
|
DWORD cycles = TAS_ABSY(a, x, y, base);
|
|
if (cycles != 5) return 1;
|
|
if (mem[addr] != (a & x & ((base>>8)+1))) return 1;
|
|
if (regs.sp != (0x100 | (a & x))) return 1;
|
|
}
|
|
|
|
//
|
|
|
|
// xas abs,y
|
|
{
|
|
WORD base = 0x20ff, addr = 0x20ff;
|
|
mem[addr] = 0xcc;
|
|
BYTE a = 0xea, x = 0x20, y = 0;
|
|
DWORD cycles = XAS_ABSY(a, x, y, base);
|
|
if (cycles != 5) return 1;
|
|
if (mem[addr] != (x & ((base>>8)+1))) return 1;
|
|
}
|
|
|
|
// xas abs,y (page-cross)
|
|
{
|
|
WORD base = 0x20ff, addr = 0x2000;
|
|
mem[addr] = 0xcc;
|
|
BYTE a = 0xea, x = 0x20, y = 1;
|
|
DWORD cycles = XAS_ABSY(a, x, y, base);
|
|
if (cycles != 5) return 1;
|
|
if (mem[addr] != (x & ((base>>8)+1))) return 1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
//-------------------------------------
|
|
|
|
int g_fn_C000_count = 0;
|
|
|
|
BYTE __stdcall fn_C000(WORD, WORD, BYTE, BYTE, ULONG)
|
|
{
|
|
g_fn_C000_count++;
|
|
return 42;
|
|
}
|
|
|
|
int GH292_test(void)
|
|
{
|
|
// Undocumented 65C02 NOPs: 1 cycle & 1 byte
|
|
for (UINT op=0; op<256; op+=0x10)
|
|
{
|
|
reset();
|
|
WORD base=regs.pc;
|
|
|
|
mem[regs.pc] = op+0x03; if (TestCpu65C02(0) != 1 || regs.pc != base+1) return 1;
|
|
mem[regs.pc] = op+0x07; if (TestCpu65C02(0) != 1 || regs.pc != base+2) return 1;
|
|
mem[regs.pc] = op+0x0B; if (TestCpu65C02(0) != 1 || regs.pc != base+3) return 1;
|
|
mem[regs.pc] = op+0x0F; if (TestCpu65C02(0) != 1 || regs.pc != base+4) return 1;
|
|
}
|
|
|
|
//
|
|
|
|
// Undocumented 65C02 NOP: LDD - LoaD and Discard
|
|
IORead[0] = fn_C000;
|
|
|
|
reset();
|
|
WORD base = regs.pc;
|
|
mem[regs.pc+0] = 0xDC;
|
|
mem[regs.pc+1] = 0x00;
|
|
mem[regs.pc+2] = 0xC0;
|
|
if (TestCpu65C02(0) != 4 || regs.pc != base+3 || g_fn_C000_count != 1 || regs.a != 0) return 1;
|
|
|
|
reset();
|
|
base = regs.pc;
|
|
mem[regs.pc+0] = 0xFC;
|
|
mem[regs.pc+1] = 0x00;
|
|
mem[regs.pc+2] = 0xC0;
|
|
if (TestCpu65C02(0) != 4 || regs.pc != base+3 || g_fn_C000_count != 2 || regs.a != 0) return 1;
|
|
|
|
IORead[0] = NULL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
//-------------------------------------
|
|
|
|
const BYTE g_GH321_code[] =
|
|
{
|
|
// org $f156
|
|
0xA9, 0x00, // lda #0
|
|
0x8D, 0x7E, 0xF7, // sta $f77e
|
|
0xA9, 0x7F, // lda #$7f
|
|
0x85, 0x0B, // sta $0b
|
|
|
|
// f15f:
|
|
0xA9, 0x00, // lda #0
|
|
0x85, 0x0C, // sta $0c
|
|
0xA5, 0x0B, // lda $0b ; 0x7F
|
|
0xCD, 0x19, 0xC0, // l1: cmp $c019
|
|
0x10, 0xFB, // bpl l1
|
|
0xA5, 0x0B, // lda $0b
|
|
0xCD, 0x19, 0xC0, // l2: cmp $c019
|
|
0x30, 0xFB, // bmi l2
|
|
0xEE, 0x7E, 0xF7, // l3: inc $f77e
|
|
0xA2, 0x09, // ldx #9
|
|
0xCA, // l4: dex
|
|
0xD0, 0xFD, // bne l4
|
|
0xA5, 0x0B, // lda $0b
|
|
0xA5, 0x0B, // lda $0b
|
|
0xCD, 0x19, 0xC0, // cmp $c019
|
|
0x10, 0xEF, // bpl l3
|
|
0xAD, 0x7E, 0xF7, // lda $f77e
|
|
0xC9, 0x47, // cmp #$47 ; 262-191 = 71 = 0x47
|
|
0xB0, 0x07, // bcs l5
|
|
0xA9, 0x01, // lda #1 ; NTSC
|
|
0x85, 0x0A, // sta $0a
|
|
0x4C, 0x94, 0xF1, // jmp $f194
|
|
0xA9, 0x00, // l5: lda #0 ; PAL
|
|
0x85, 0x0A, // sta $0a
|
|
|
|
// f194:
|
|
0x00
|
|
};
|
|
|
|
DWORD g_dwCyclesThisFrame = 0; // # cycles executed in frame before Cpu65C02() was called
|
|
|
|
ULONG CpuGetCyclesThisVideoFrame(ULONG nExecutedCycles)
|
|
{
|
|
return g_dwCyclesThisFrame + nExecutedCycles;
|
|
}
|
|
|
|
// video scanner constants
|
|
int const kHBurstClock = 53; // clock when Color Burst starts
|
|
int const kHBurstClocks = 4; // clocks per Color Burst duration
|
|
int const kHClock0State = 0x18; // H[543210] = 011000
|
|
int const kHClocks = 65; // clocks per horizontal scan (including HBL)
|
|
int const kHPEClock = 40; // clock when HPE (horizontal preset enable) goes low
|
|
int const kHPresetClock = 41; // clock when H state presets
|
|
int const kHSyncClock = 49; // clock when HSync starts
|
|
int const kHSyncClocks = 4; // clocks per HSync duration
|
|
int const kNTSCScanLines = 262; // total scan lines including VBL (NTSC)
|
|
int const kNTSCVSyncLine = 224; // line when VSync starts (NTSC)
|
|
int const kPALScanLines = 312; // total scan lines including VBL (PAL)
|
|
int const kPALVSyncLine = 264; // line when VSync starts (PAL)
|
|
int const kVLine0State = 0x100; // V[543210CBA] = 100000000
|
|
int const kVPresetLine = 256; // line when V state presets
|
|
int const kVSyncLines = 4; // lines per VSync duration
|
|
|
|
bool bVideoScannerNTSC = true;
|
|
|
|
// Derived from VideoGetScannerAddress()
|
|
bool VideoGetVbl(const DWORD uExecutedCycles)
|
|
{
|
|
// get video scanner position
|
|
//
|
|
int nCycles = CpuGetCyclesThisVideoFrame(uExecutedCycles);
|
|
|
|
// calculate video parameters according to display standard
|
|
//
|
|
int nScanLines = bVideoScannerNTSC ? kNTSCScanLines : kPALScanLines;
|
|
int nScanCycles = nScanLines * kHClocks;
|
|
nCycles %= nScanCycles;
|
|
|
|
// calculate vertical scanning state
|
|
//
|
|
int nVLine = nCycles / kHClocks; // which vertical scanning line
|
|
int nVState = kVLine0State + nVLine; // V state bits
|
|
if ((nVLine >= kVPresetLine)) // check for previous vertical state preset
|
|
{
|
|
nVState -= nScanLines; // compensate for preset
|
|
}
|
|
int v_3 = (nVState >> 6) & 1;
|
|
int v_4 = (nVState >> 7) & 1;
|
|
|
|
// update VBL' state
|
|
//
|
|
if (v_4 & v_3) // VBL?
|
|
{
|
|
return false; // Y: VBL' is false
|
|
}
|
|
else
|
|
{
|
|
return true; // N: VBL' is true
|
|
}
|
|
}
|
|
|
|
BYTE __stdcall fn_C010(WORD nPC, WORD nAddr, BYTE nWriteFlag, BYTE nWriteValue, ULONG uExecutedCycles)
|
|
{
|
|
if (nAddr != 0xC019)
|
|
return 0;
|
|
|
|
if (nWriteFlag)
|
|
return 0;
|
|
|
|
return VideoGetVbl(uExecutedCycles) ? 0x80 : 0;
|
|
}
|
|
|
|
int GH321_test()
|
|
{
|
|
const UINT org = 0xf156;
|
|
memcpy(mem+org, g_GH321_code, sizeof(g_GH321_code));
|
|
reset();
|
|
|
|
IORead[1] = fn_C010;
|
|
g_bStopOnBRK = true;
|
|
|
|
// 65C02 - CMP; CYC(4) : Fails every 7th cycle, ie: 6, 13, 20, ...
|
|
// 65C02 - CYC(4); CMP : Fails every 7th cycle, ie: 2, 9, 16, ...
|
|
// 65C02 - CYC(3); CMP; CYC(1) : Fails every 7th cycle, ie: 3, 10, 17, ...
|
|
BYTE res[kHClocks] = {0xFF};
|
|
|
|
UINT startCycle = 0;
|
|
for (; startCycle < kHClocks; startCycle++)
|
|
{
|
|
g_dwCyclesThisFrame = startCycle;
|
|
|
|
regs.pc = org;
|
|
ULONG uExecutedCycles = TestCpu65C02(2 * kNTSCScanLines * kHClocks);
|
|
|
|
res[startCycle] = mem[0x000a];
|
|
//if (mem[0x000a] == 0)
|
|
// break;
|
|
}
|
|
|
|
//
|
|
|
|
IORead[1] = NULL;
|
|
g_bStopOnBRK = false;
|
|
|
|
return mem[0x000a] == 0 ? 1 : 0;
|
|
}
|
|
|
|
//-------------------------------------
|
|
|
|
int _tmain(int argc, _TCHAR* argv[])
|
|
{
|
|
int res = 1;
|
|
init();
|
|
reset();
|
|
|
|
// res = GH321_test();
|
|
// if (res) return res;
|
|
|
|
res = GH264_test();
|
|
if (res) return res;
|
|
|
|
res = GH271_test();
|
|
if (res) return res;
|
|
|
|
res = GH278_test();
|
|
if (res) return res;
|
|
|
|
res = GH282_test();
|
|
if (res) return res;
|
|
|
|
res = GH292_test();
|
|
if (res) return res;
|
|
|
|
return 0;
|
|
}
|