diff --git a/A2Mac.xcodeproj/project.pbxproj b/A2Mac.xcodeproj/project.pbxproj index d933866..dcd9bc4 100644 --- a/A2Mac.xcodeproj/project.pbxproj +++ b/A2Mac.xcodeproj/project.pbxproj @@ -13,6 +13,7 @@ 323D042E248980600086A901 /* Preferences.storyboard in Resources */ = {isa = PBXBuildFile; fileRef = 323D042D248980600086A901 /* Preferences.storyboard */; }; 323D043024898AB70086A901 /* PreferencesViewController.swift in Sources */ = {isa = PBXBuildFile; fileRef = 323D042F24898AB70086A901 /* PreferencesViewController.swift */; }; 323D04332489BFD80086A901 /* PreferencesWindowController.swift in Sources */ = {isa = PBXBuildFile; fileRef = 323D04312489BFD80086A901 /* PreferencesWindowController.swift */; }; + 323D0437248B6BEA0086A901 /* 6502.c in Sources */ = {isa = PBXBuildFile; fileRef = 32439F7422ECD8AD0077AAE0 /* 6502.c */; }; 323E2DCE245531E600156805 /* Apple2e_Enhanced.rom in Resources */ = {isa = PBXBuildFile; fileRef = 323E2DCC245531E500156805 /* Apple2e_Enhanced.rom */; }; 323E2DCF245531E600156805 /* Apple2e_Enhanced.rom in Resources */ = {isa = PBXBuildFile; fileRef = 323E2DCC245531E500156805 /* Apple2e_Enhanced.rom */; }; 323E2DD0245531E600156805 /* Apple2e.rom in Resources */ = {isa = PBXBuildFile; fileRef = 323E2DCD245531E500156805 /* Apple2e.rom */; }; @@ -30,7 +31,6 @@ 32440B80247CB66C000F9DA1 /* Merlin Assembler (early version, 40-column, DOS 3.3) side A.woz in Resources */ = {isa = PBXBuildFile; fileRef = 32440B7E247CB66C000F9DA1 /* Merlin Assembler (early version, 40-column, DOS 3.3) side A.woz */; }; 32440B81247CB66C000F9DA1 /* Merlin Assembler (early version, 40-column, DOS 3.3) side B.woz in Resources */ = {isa = PBXBuildFile; fileRef = 32440B7F247CB66C000F9DA1 /* Merlin Assembler (early version, 40-column, DOS 3.3) side B.woz */; }; 32440B83247CC4C0000F9DA1 /* Wavy Navy (4am crack).woz in Resources */ = {isa = PBXBuildFile; fileRef = 32440B82247CC4C0000F9DA1 /* Wavy Navy (4am crack).woz */; }; - 32440B84247E27D3000F9DA1 /* 6502.c in Sources */ = {isa = PBXBuildFile; fileRef = 32439F7422ECD8AD0077AAE0 /* 6502.c */; }; 32440B85247E27D7000F9DA1 /* 6502.c in Sources */ = {isa = PBXBuildFile; fileRef = 32439F7422ECD8AD0077AAE0 /* 6502.c */; }; 32440B8F247F86D6000F9DA1 /* Apple II+ Dealer Diagnostics.woz in Resources */ = {isa = PBXBuildFile; fileRef = 32440B86247F86D4000F9DA1 /* Apple II+ Dealer Diagnostics.woz */; }; 32440B90247F86D6000F9DA1 /* XPS Diagnostic IIe 1.0.5.woz in Resources */ = {isa = PBXBuildFile; fileRef = 32440B87247F86D5000F9DA1 /* XPS Diagnostic IIe 1.0.5.woz */; }; @@ -154,6 +154,7 @@ 323D042D248980600086A901 /* Preferences.storyboard */ = {isa = PBXFileReference; lastKnownFileType = file.storyboard; path = Preferences.storyboard; sourceTree = ""; }; 323D042F24898AB70086A901 /* PreferencesViewController.swift */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.swift; path = PreferencesViewController.swift; sourceTree = ""; }; 323D04312489BFD80086A901 /* PreferencesWindowController.swift */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.swift; path = PreferencesWindowController.swift; sourceTree = ""; }; + 323D0435248B20F20086A901 /* 6502_instr_undoc.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = 6502_instr_undoc.h; sourceTree = ""; }; 323E2DCC245531E500156805 /* Apple2e_Enhanced.rom */ = {isa = PBXFileReference; lastKnownFileType = file; path = Apple2e_Enhanced.rom; sourceTree = ""; }; 323E2DCD245531E500156805 /* Apple2e.rom */ = {isa = PBXFileReference; lastKnownFileType = file; path = Apple2e.rom; sourceTree = ""; }; 32439F7222ECD8AC0077AAE0 /* A2Mac-Bridging-Header.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = "A2Mac-Bridging-Header.h"; sourceTree = ""; }; @@ -338,6 +339,7 @@ 32439F7622ECD8AD0077AAE0 /* 6502_instr_set_clr.h */, 32439F7722ECD8AD0077AAE0 /* 6502_instr_stack.h */, 32439F7822ECD8AD0077AAE0 /* 6502_instr_logic.h */, + 323D0435248B20F20086A901 /* 6502_instr_undoc.h */, 32439F7922ECD8AD0077AAE0 /* 6502_instr_shift_rotate.h */, 32439F7A22ECD8AD0077AAE0 /* 6502_instr_inc_dec.h */, 32439F7B22ECD8AD0077AAE0 /* 6502_instr_compare_test.h */, @@ -970,12 +972,12 @@ files = ( 325EB63623F8F78300C6B4A4 /* disk.c in Sources */, 325EB63923F9E48100C6B4A4 /* common.c in Sources */, + 323D0437248B6BEA0086A901 /* 6502.c in Sources */, 32A9F74A2467B60B004902A1 /* speaker.c in Sources */, 32BFFB5D22EACC630003B53F /* ViewController.swift in Sources */, 325EB69323FE6C6200C6B4A4 /* HiRes.swift in Sources */, 32C4532E233345430000EBA1 /* MonitorView.swift in Sources */, 32440BA32480D5C0000F9DA1 /* LoRes.swift in Sources */, - 32440B84247E27D3000F9DA1 /* 6502.c in Sources */, 325EB62F23F8856F00C6B4A4 /* woz.c in Sources */, 323D04332489BFD80086A901 /* PreferencesWindowController.swift in Sources */, 32BFFB5B22EACC630003B53F /* AppDelegate.swift in Sources */, diff --git a/src/cpu/6502.c b/src/cpu/6502.c index 0fdf1ee..3e845dd 100644 --- a/src/cpu/6502.c +++ b/src/cpu/6502.c @@ -405,105 +405,105 @@ INLINE int m6502_Step() { switch ( fetch() ) { case 0x00: BRK(); return 7; // BRK case 0x01: ORA( src_X_ind() ); return 6; // ORA X,ind -// case 0x02: // t jams -// case 0x03: // SLO* (undocumented) -// case 0x04: // NOP* (undocumented) + case 0x02: KIL(); return 0; // KIL - Hangs the CPU // t jams + case 0x03: SLO( addr_zp_X() ); return 8; // SLO* zpg,X (undocumented) + case 0x04: NOP2( src_zp() ); return 3; // NOP* zpg (undocumented) case 0x05: ORA( src_zp() ); return 3; // ORA zpg case 0x06: ASL( addr_zp() ); return 5; // ASL zpg -// case 0x07: // SLO* (undocumented) + case 0x07: SLO( addr_zp() ); return 5; // SLO* zpg (undocumented) case 0x08: PHP(); return 3; // PHP case 0x09: ORA( imm() ); return 2; // ORA imm case 0x0A: ASLA(); return 2; // ASL A -// case 0x0B: // ANC** (undocumented) -// case 0x0C: // NOP* (undocumented) + case 0x0B: ANC( imm() ); return 2; // ANC** imm (undocumented) + case 0x0C: NOP2( src_abs() ); return 4; // NOP* (undocumented) case 0x0D: ORA( src_abs() ); return 4; // ORA abs case 0x0E: ASL( addr_abs() ); return 6; // ASL abs -// case 0x0F: // SLO* (undocumented) + case 0x0F: SLO( addr_abs() ); return 6; // SLO* (undocumented) case 0x10: BPL( rel_addr() ); return 3; // BPL rel case 0x11: ORA( src_ind_Y() ); return 5; // ORA ind,Y -// case 0x12: // t jams -// case 0x13: // SLO* (undocumented) -// case 0x14: // NOP* (undocumented) + case 0x12: KIL(); return 0; // KIL - Hangs the CPU // t jams + case 0x13: SLO( addr_zp_Y() ); return 8; // SLO* zpg,Y (undocumented) + case 0x14: NOP2( addr_zp_X() ); return 4; // NOP* zpg,X (undocumented) case 0x15: ORA( src_zp_X() ); return 4; // ORA zpg,X case 0x16: ASL( addr_zp_X() ); return 6; // ASL zpg,X -// case 0x17: // SLO* (undocumented) + case 0x17: SLO( addr_zp_X() ); return 6; // SLO* zpg,X (undocumented) case 0x18: CLC(); return 2; // CLC case 0x19: ORA( src_abs_Y() ); return 4; // ORA abs,Y -// case 0x1A: // NOP* (undocumented) -// case 0x1B: // SLO* (undocumented) -// case 0x1C: // NOP* (undocumented) + case 0x1A: NOP(); return 2; // NOP* (undocumented) + case 0x1B: SLO( addr_abs_Y() ); return 7; // SLO* abs,Y (undocumented) + case 0x1C: NOP2( src_abs_X() ); return 4; // NOP* (undocumented) case 0x1D: ORA( src_abs_X() ); return 4; // ORA abs,X case 0x1E: ASL( addr_abs_X() ); return 7; // ASL abs,X -// case 0x1F: // SLO* (undocumented) + case 0x1F: SLO( addr_abs_X() ); return 7; // SLO* abs,X (undocumented) case 0x20: JSR( abs_addr() ); return 6; // JSR abs case 0x21: AND( src_X_ind() ); return 6; // AND X,ind -// case 0x22: KIL -// case 0x23: RLA izx 8 + case 0x22: KIL(); return 0; // KIL - Hangs the CPU + case 0x23: RLA( addr_ind_X() ); return 8; // RLA* ind,X 8 (undocumented) case 0x24: BIT( src_zp() ); return 3; // BIT zpg case 0x25: AND( src_zp() ); return 3; // AND zpg case 0x26: ROL( addr_zp() ); return 5; // ROL zpg -// case 0x27: RLA zp 5 + case 0x27: RLA( addr_zp() ); return 5; // RLA* zpg 5 (undocumented) case 0x28: PLP(); return 4; // PLP case 0x29: AND( imm() ); return 2; // AND imm case 0x2A: ROLA(); return 2; // ROL A -// case 0x2B: ANC imm 2 + case 0x2B: ANC( imm() ); return 2; // ANC* imm 2 (undocumented) case 0x2C: BIT( src_abs() ); return 4; // BIT abs case 0x2D: AND( src_abs() ); return 4; // AND abs case 0x2E: ROL( addr_abs() ); return 6; // ROL abs -// case 0x2F: RLA abs 6 + case 0x2F: RLA( addr_abs() ); return 6; // RLA* abs 6 (undocumented) case 0x30: BMI( rel_addr() ); return 3; // BMI rel case 0x31: AND( src_ind_Y() ); return 5; // AND ind,Y -// case 0x32: KIL -// case 0x33: RLA izy 8 -// case 0x34: NOP zpx 4 + case 0x32: KIL(); return 0; // KIL - Hangs the CPU + case 0x33: RLA( addr_ind_Y() ); return 8; // RLA* izy 8 (undocumented) + case 0x34: NOP2( src_zp_X() ); return 4; // NOP* zpx 4 (undocumented) case 0x35: AND( src_zp_X() ); return 4; // AND zpg,X case 0x36: ROL( addr_zp_X() ); return 6; // ROL zpg,X -// case 0x37: RLA zpx 6 + case 0x37: RLA( addr_zp_X() ); return 6; // RLA* zpx 6 (undocumented) case 0x38: SEC(); return 2; // SEC case 0x39: AND( src_abs_Y() ); return 4; // AND abs,Y -// case 0x3A: NOP 2 -// case 0x3B: RLA aby 7 -// case 0x3C: NOP abx 4 + case 0x3A: NOP(); return 2; // NOP* 2 (undocumented) + case 0x3B: RLA( addr_abs_Y() ); return 7; // RLA* aby 7 (undocumented) + case 0x3C: NOP2( src_abs_X() ); return 4; // NOP* abx 4 (undocumented) case 0x3D: AND( src_abs_X() ); return 4; // AND abs,X case 0x3E: ROL( addr_abs_X() ); return 7; // ROL abs,X -// case 0x3F: RLA abx 7 + case 0x3F: RLA( addr_abs_X() ); return 7; // RLA* abx 7 (undocumented) case 0x40: RTI(); return 6; // RTI case 0x41: EOR( src_X_ind() ); return 6; // EOR X,ind -// case 0x42: KIL -// case 0x43: SRE izx 8 -// case 0x44: NOP zp 3 + case 0x42: KIL(); return 0; // KIL - Hangs the CPU + case 0x43: SRE( addr_ind_X() ); return 8; // SRE* izx 8 (undocumented) + case 0x44: NOP(); return 3; // NOP* zp 3 (undocumented) case 0x45: EOR( src_zp() ); return 3; // EOR zpg case 0x46: LSR( addr_zp() ); return 5; // LSR zpg -// case 0x47: SRE zp 5 + case 0x47: SRE( addr_zp() ); return 5; // SRE* zp 5 (undocumented) case 0x48: PHA(); return 3; // PHA case 0x49: EOR( imm() ); return 2; // EOR imm case 0x4A: LSRA(); return 2; // LSR A -// case 0x4B: ALR imm 2 + case 0x4B: ASR( imm() ); return 2; // ASR* imm 2 (undocumented) case 0x4C: JMP( abs_addr() ); return 3; // JMP abs case 0x4D: EOR( src_abs() ); return 4; // EOR abs case 0x4E: LSR( addr_abs() ); return 6; // LSR abs -// case 0x4F: SRE abs 6 + case 0x4F: SRE( abs_addr() ); return 6; // SRE* abs 6 (undocumented) case 0x50: BVC( rel_addr() ); return 3; // BVC rel case 0x51: EOR( src_ind_Y() ); return 5; // EOR ind,Y -// case 0x52: KIL -// case 0x53: SRE izy 8 -// case 0x54: NOP zpx 4 + case 0x52: KIL(); return 0; // KIL - Hangs the CPU + case 0x53: SRE( addr_ind_Y() ); return 8; // SRE* izy 8 (undocumented) + case 0x54: NOP2( src_zp_X() ); return 4; // NOP* zpx 4 (undocumented) case 0x55: EOR( src_zp_X() ); return 4; // AND zpg,X case 0x56: LSR( addr_zp_X() ); return 6; // LSR zpg,X -// case 0x57: SRE zpx 6 + case 0x57: SRE( addr_ind_X() ); return 6; // SRE* zpx 6 (undocumented) case 0x58: CLI(); return 2; // CLI case 0x59: EOR( src_abs_Y() ); return 4; // EOR abs,Y -// case 0x5A: NOP 2 -// case 0x5B: SRE aby 7 -// case 0x5C: NOP abx 4 + case 0x5A: NOP(); return 2; // NOP* 2 (undocumented) + case 0x5B: SRE( addr_abs_Y() ); return 7; // SRE* aby 7 (undocumented) + case 0x5C: NOP2( src_abs_X() ); return 4; // NOP* abx 4 (undocumented) case 0x5D: EOR( src_abs_X() ); return 4; // EOR abs,X case 0x5E: LSR( addr_abs_X() ); return 7; // LSR abs,X -// case 0x5F: SRE abx 7 + case 0x5F: SRE( addr_abs_X() ); return 7; // SRE* abx 7 (undocumented) case 0x60: RTS(); return 6; // RTS case 0x61: ADC( src_X_ind() ); return 6; // ADC X,ind -// case 0x62: KIL + case 0x62: KIL(); return 0; // KIL - Hangs the CPU // case 0x63: RRA izx 8 -// case 0x64: NOP zp 3 + case 0x64: NOP(); return 3; // NOP* zp 3 (undocumented) case 0x65: ADC( src_zp() ); return 3; // ADC zpg case 0x66: ROR( addr_zp() ); return 5; // ROR zpg // case 0x67: RRA zp 5 @@ -532,7 +532,7 @@ INLINE int m6502_Step() { case 0x7E: ROR( addr_abs_X() ); return 7; // ROR abs,X // case 0x7F: // case 0x80: - case 0x81: STA( addr_X_ind() ) ; return 6; // STA X,ind + case 0x81: STA( addr_ind_X() ) ; return 6; // STA X,ind // case 0x82: // case 0x83: case 0x84: STY( addr_zp() ); return 3; // STY zpg diff --git a/src/cpu/6502_vanilla.c b/src/cpu/6502_vanilla.c index cdc5381..c4e6b3b 100644 --- a/src/cpu/6502_vanilla.c +++ b/src/cpu/6502_vanilla.c @@ -41,6 +41,8 @@ unsigned long long MHz_6502 = default_MHz_6502; unsigned long long clk_6502_per_frm = default_MHz_6502 / fps; unsigned long long clk_6502_per_frm_set = default_MHz_6502 / fps; unsigned long long clk_6502_per_frm_max = 0; +unsigned long long clk_6502_per_frm_max_sound = 4 * default_MHz_6502 / fps; + unsigned long long tick_per_sec = G; @@ -531,7 +533,7 @@ INLINE int m6502_Step() { case 0x7E: ROR( addr_abs_X() ); return 7; // ROR abs,X // case 0x7F: // case 0x80: - case 0x81: STA( addr_X_ind() ) ; return 6; // STA X,ind + case 0x81: STA( addr_ind_X() ) ; return 6; // STA X,ind // case 0x82: // case 0x83: case 0x84: STY( addr_zp() ); return 3; // STY zpg diff --git a/src/cpu/instructions/6502_instr_arithmetic.h b/src/cpu/instructions/6502_instr_arithmetic.h index a48a529..2d73cc2 100644 --- a/src/cpu/instructions/6502_instr_arithmetic.h +++ b/src/cpu/instructions/6502_instr_arithmetic.h @@ -29,15 +29,12 @@ (indirect,X) ADC (oper,X) 61 2 6 (indirect),Y ADC (oper),Y 71 2 5* **/ -INLINE void ADC( uint8_t src ) { - dbgPrintf("ADC(%02X) ", src); - disPrintf(disassembly.inst, "ADC"); - +INLINE void _ADC( uint8_t src ) { uint16_t tmp; - + // V = C7 != C6 m6502.V = ((m6502.A & 0x7F) + (src & 0x7F) + (m6502.C != 0)) > 0x7F; - + if ( m6502.D ) { if ( (tmp = (m6502.A & 0x0F) + (src & 0x0F) + (m6502.C != 0)) > 0x09 ) { tmp += 0x06; @@ -53,19 +50,25 @@ INLINE void ADC( uint8_t src ) { set_flags_NZ( m6502.A = tmp ); m6502.C = tmp > 0xFF; m6502.V ^= m6502.C; - -// // this is good but slow: -// uint16_t tmp = (uint16_t)m6502.A + src + m6502.C; -// m6502.V = ( !((m6502.A ^ src) & 0x80)) && ( (m6502.A ^ tmp) & 0x80); -// m6502.C = tmp > 0xFF; -// set_flags_NZ( m6502.A = tmp ); - -// // this is good but slow: -// uint16_t tmp = (uint16_t)m6502.A + src + m6502.C; -// m6502.V = ( ((m6502.A ^ src) ^ (m6502.A ^ tmp)) & 0x80 ) != 0; -// m6502.C = tmp > 0xFF; -// set_flags_NZ( m6502.A = tmp ); + // // this is good but slow: + // uint16_t tmp = (uint16_t)m6502.A + src + m6502.C; + // m6502.V = ( !((m6502.A ^ src) & 0x80)) && ( (m6502.A ^ tmp) & 0x80); + // m6502.C = tmp > 0xFF; + // set_flags_NZ( m6502.A = tmp ); + + // // this is good but slow: + // uint16_t tmp = (uint16_t)m6502.A + src + m6502.C; + // m6502.V = ( ((m6502.A ^ src) ^ (m6502.A ^ tmp)) & 0x80 ) != 0; + // m6502.C = tmp > 0xFF; + // set_flags_NZ( m6502.A = tmp ); + +} +INLINE void ADC( uint8_t src ) { + dbgPrintf("ADC(%02X) ", src); + disPrintf(disassembly.inst, "ADC"); + + _ADC(src); } /** diff --git a/src/cpu/instructions/6502_instr_misc.h b/src/cpu/instructions/6502_instr_misc.h index 504bd1e..5c2f13b 100644 --- a/src/cpu/instructions/6502_instr_misc.h +++ b/src/cpu/instructions/6502_instr_misc.h @@ -33,6 +33,22 @@ INLINE int BRK() { return 7; } +/** + KIL Kills the CPU - Well, it hangs it untill the next power cycle + **/ +INLINE int KIL() { + dbgPrintf("KIL "); + disPrintf(disassembly.inst, "KIL"); + PUSH_addr(m6502.PC -1); // PC, however, fetch already incremented it by 1 + // B flag should be set before pushing flags onto the stack + m6502.B = 1; + PUSH( getFlags().SR ); + m6502.I = 1; + m6502.PC = memread16(IRQ_VECTOR); + + return 7; +} + /** NOP No Operation diff --git a/src/cpu/instructions/6502_instr_shift_rotate.h b/src/cpu/instructions/6502_instr_shift_rotate.h index 8a230d8..366c46e 100644 --- a/src/cpu/instructions/6502_instr_shift_rotate.h +++ b/src/cpu/instructions/6502_instr_shift_rotate.h @@ -109,14 +109,17 @@ INLINE void ROLA() { absolute ROR oper 6E 3 6 absolute,X ROR oper,X 7E 3 7 **/ -INLINE void ROR( uint16_t addr ) { - dbgPrintf("ROR "); - disPrintf(disassembly.inst, "ROR"); +INLINE void _ROR( uint16_t addr ) { uint8_t C = m6502.C != 0; m6502.C = WRLOMEM[addr] & 1; WRLOMEM[addr] >>= 1; set_flags_NZ( WRLOMEM[addr] |= C << 7 ); } +INLINE void ROR( uint16_t addr ) { + dbgPrintf("ROR "); + disPrintf(disassembly.inst, "ROR"); + _ROR(addr); +} INLINE void RORA() { dbgPrintf("ROR "); disPrintf(disassembly.inst, "ROR"); diff --git a/src/cpu/instructions/6502_instr_undoc.h b/src/cpu/instructions/6502_instr_undoc.h new file mode 100644 index 0000000..674a1a3 --- /dev/null +++ b/src/cpu/instructions/6502_instr_undoc.h @@ -0,0 +1,142 @@ +// +// main.c +// 6502 +// +// Created by Tamas Rudnai on 7/14/19. +// Copyright © 2019 GameAlloy. All rights reserved. +// + +#ifndef __6502_INSTR_UNDOC_H__ +#define __6502_INSTR_UNDOC_H__ + + +/** +ANC - "AND" Memory with Accumulator + THEN Copy Bit 7 of Result into Carry + + (M "AND" A) -> A + THEN msb(A) -> C +**/ +INLINE void ANC ( uint8_t src ) { + disPrintf(disassembly.inst, "ANC"); + + set_flags_NZ( m6502.A &= src ); + m6502.C = m6502.A >> 7; +} + + +/** + ASR - "AND" Memory with Accumulator + THEN Shift Accumulator One Bit Right + + (M "AND" A) -> A + THEN LSR A + **/ +INLINE void ASR ( uint8_t src ) { + disPrintf(disassembly.inst, "ASR"); + + // AND + m6502.A &= src; + + // LSR A + m6502.C = m6502.A & 1; + set_flags_NZ( m6502.A >>= 1 ); +} + + +/** + NOP No Operation + + --- N Z C I D V + - - - - - - + + addressing assembler opc bytes cyles + -------------------------------------------- + implied NOP EA ? ? + **/ +INLINE void NOP2( uint8_t src ) { + disPrintf(disassembly.inst, "NOP2"); +} + + + +/** + RLA - Rotate Memory One Bit Left + THEN "AND" Memory with Accumulator + + ROL M + AND M +**/ +INLINE void RLA ( uint16_t addr ) { + disPrintf(disassembly.inst, "RLA"); + + // ROL M + uint8_t C = m6502.C != 0; + m6502.C = WRLOMEM[addr] & 0x80; + WRLOMEM[addr] <<= 1; + WRLOMEM[addr] |= C; + + // AND M + set_flags_NZ( m6502.A &= WRLOMEM[addr] ); + +} + + +/** + RRA - Rotate Memory One Bit Right + THEN Add Memory to Accumulator with Carry + + ROR M + ADC M + **/ +INLINE void RRA ( uint16_t addr ) { + disPrintf(disassembly.inst, "RRA"); + _ROR(addr); + _ADC(WRLOMEM[addr]); +} + + +/** + SLO - Shift Memory One Bit Left + THEN "OR" Memory with Accumulator + into Accumulator and Memory + + ASL M + ORA M + -> A,M +**/ + +INLINE void SLO ( uint16_t addr ) { + disPrintf(disassembly.inst, "SLO"); + + m6502.C = WRLOMEM[addr] & 0x80; + WRLOMEM[addr] <<= 1; // ASL M -> M + m6502.A ^= WRLOMEM[addr]; // EOR M -> A + set_flags_NZ( WRLOMEM[addr] = m6502.A ); // A -> M +} + + +/** + SRE - Shift Memory One Bit Right + THEN "OR" Memory with Accumulator + + LSR M + ORA M + **/ + +INLINE void SRE ( uint16_t addr ) { + disPrintf(disassembly.inst, "SRE"); + + // LSR + m6502.C = WRLOMEM[addr] & 1; + set_flags_NZ( WRLOMEM[addr] >>= 1 ); + + // EOR M + set_flags_NZ( m6502.A |= WRLOMEM[addr] ); + +} + + + +#endif // __6502_INSTR_UNDOC_H__ + diff --git a/src/cpu/instructions/6502_instructions.h b/src/cpu/instructions/6502_instructions.h index e2191e3..e0ff849 100644 --- a/src/cpu/instructions/6502_instructions.h +++ b/src/cpu/instructions/6502_instructions.h @@ -22,6 +22,7 @@ #include "6502_instr_call_ret_jump.h" #include "6502_instr_set_clr.h" #include "6502_instr_misc.h" +#include "6502_instr_undoc.h" #endif // __6502_INSTRUCTIONS_H__