mirror of
https://github.com/trudnai/Steve2.git
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Instruction BugFixes
This commit is contained in:
parent
d644057a13
commit
5ad28e911e
@ -15,6 +15,7 @@
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32BFFB6222EACC660003B53F /* Main.storyboard in Resources */ = {isa = PBXBuildFile; fileRef = 32BFFB6022EACC660003B53F /* Main.storyboard */; };
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32BFFB6E22EACC660003B53F /* A2MacTests.swift in Sources */ = {isa = PBXBuildFile; fileRef = 32BFFB6D22EACC660003B53F /* A2MacTests.swift */; };
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32BFFB7922EACC660003B53F /* A2MacUITests.swift in Sources */ = {isa = PBXBuildFile; fileRef = 32BFFB7822EACC660003B53F /* A2MacUITests.swift */; };
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32EDB7A223272CA80073AF2D /* fail1.txt in Resources */ = {isa = PBXBuildFile; fileRef = 32EDB7A123272CA80073AF2D /* fail1.txt */; };
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/* End PBXBuildFile section */
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/* Begin PBXContainerItemProxy section */
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@ -68,6 +69,7 @@
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32BFFB7422EACC660003B53F /* A2MacUITests.xctest */ = {isa = PBXFileReference; explicitFileType = wrapper.cfbundle; includeInIndex = 0; path = A2MacUITests.xctest; sourceTree = BUILT_PRODUCTS_DIR; };
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32BFFB7822EACC660003B53F /* A2MacUITests.swift */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.swift; path = A2MacUITests.swift; sourceTree = "<group>"; };
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32BFFB7A22EACC660003B53F /* Info.plist */ = {isa = PBXFileReference; lastKnownFileType = text.plist.xml; path = Info.plist; sourceTree = "<group>"; };
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32EDB7A123272CA80073AF2D /* fail1.txt */ = {isa = PBXFileReference; lastKnownFileType = text; path = fail1.txt; sourceTree = "<group>"; };
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/* End PBXFileReference section */
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/* Begin PBXFrameworksBuildPhase section */
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@ -147,6 +149,7 @@
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32439F8622ECD8AD0077AAE0 /* common.h */,
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32BFFB5A22EACC630003B53F /* AppDelegate.swift */,
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32BFFB5C22EACC630003B53F /* ViewController.swift */,
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32EDB7A123272CA80073AF2D /* fail1.txt */,
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32BFFB5E22EACC660003B53F /* Assets.xcassets */,
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32BFFB6022EACC660003B53F /* Main.storyboard */,
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32BFFB6322EACC660003B53F /* Info.plist */,
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@ -279,6 +282,7 @@
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isa = PBXResourcesBuildPhase;
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buildActionMask = 2147483647;
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files = (
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32EDB7A223272CA80073AF2D /* fail1.txt in Resources */,
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32BFFB5F22EACC660003B53F /* Assets.xcassets in Resources */,
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32439F8822ECD8AD0077AAE0 /* apple.rom in Resources */,
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32BFFB6222EACC660003B53F /* Main.storyboard in Resources */,
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28
A2Mac/6502.c
28
A2Mac/6502.c
@ -73,15 +73,15 @@ static inline int m6502_step() {
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// case 0x1A: // NOP* (undocumented)
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// case 0x1B: // SLO* (undocumented)
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// case 0x1C: // NOP* (undocumented)
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case 0x1D: ORA( memread( fetch16() + m6502.X ) ); return 4; // ORA abs,X
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case 0x1E: ASL( & RAM[ fetch16() + m6502.X ] ); return 7; // ASL abs,X
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case 0x1D: ORA( src_abs_X() ); return 4; // ORA abs,X
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case 0x1E: ASL( dest_abs_X() ); return 7; // ASL abs,X
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// case 0x1F: // SLO* (undocumented)
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case 0x20: JSR( fetch16() ); return 6; // JSR abs
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case 0x21: AND( memread( addr_X_ind() ) ); return 6; // AND X,ind
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case 0x20: JSR( abs_addr() ); return 6; // JSR abs
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case 0x21: AND( src_X_ind() ); return 6; // AND X,ind
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// case 0x22:
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// case 0x23:
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case 0x24: BIT( memread_zp( fetch() ) ); return 3; // BIT zpg
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case 0x25: AND( memread_zp( fetch() ) ); return 3; // AND zpg
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case 0x24: BIT( src_zp() ); return 3; // BIT zpg
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case 0x25: AND( src_zp() ); return 3; // AND zpg
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case 0x26: ROL( & RAM[ fetch() ] ); return 5; // ROL zpg
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// case 0x27:
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case 0x28: PLP(); return 4; // PLP
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@ -89,7 +89,7 @@ static inline int m6502_step() {
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case 0x2A: ROL( & m6502.A ); return 2; // ROL A
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// case 0x2B:
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case 0x2C: BIT( memread( fetch16() ) ); return 4; // BIT abs
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case 0x2D: AND( fetch16() ); return 4; // AND abs
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case 0x2D: AND( memread( fetch16() ) ); return 4; // AND abs
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case 0x2E: ROL( & RAM[ fetch16() ] ); return 6; // ROL abs
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// case 0x2F:
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case 0x30: BMI( (int8_t)fetch() ); return 2; // BMI rel
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@ -121,7 +121,7 @@ static inline int m6502_step() {
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case 0x4A: LSR( & m6502.A ); return 2; // LSR A
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// case 0x4B:
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case 0x4C: JMP( fetch16() ); return 3; // JMP abs
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case 0x4D: EOR( fetch16() ); return 4; // EOR abs
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case 0x4D: EOR( memread( fetch16() ) ); return 4; // EOR abs
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case 0x4E: LSR( & RAM[ fetch16() ] ); return 6; // LSR abs
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// case 0x4F:
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case 0x50: BVC( (int8_t)fetch() ); return 2; // BVC rel
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@ -234,7 +234,7 @@ static inline int m6502_step() {
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// case 0xBB:
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case 0xBC: LDY( memread( addr_abs_X() ) ); return 4; // LDY abs,X
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case 0xBD: LDA( memread( addr_abs_X() ) ); return 4; // LDA abs,X
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case 0xBE: LDX( memread( addr_abs_X() ) ); return 4; // LDX abs,Y
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case 0xBE: LDX( memread( addr_abs_Y() ) ); return 4; // LDX abs,Y
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// case 0xBF:
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case 0xC0: CPY( fetch() ); break; // CPY imm
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case 0xC1: CMP( memread( addr_X_ind() ) ) ; break; // LDA X,ind
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@ -249,7 +249,7 @@ static inline int m6502_step() {
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case 0xCA: DEX(); return 2; // DEX
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// case 0xCB:
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case 0xCC: CPY( memread( fetch16() ) ); return 4; // CPY abs
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case 0xCD: CMP( fetch16() ); return 4; // CMP abs
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case 0xCD: CMP( memread( fetch16() ) ); return 4; // CMP abs
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case 0xCE: DEC( & RAM[ fetch16() ] ); return 4; // DEC abs
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// case 0xCF:
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case 0xD0: BNE( (int8_t)fetch() ); return 2; // BNE rel
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@ -269,7 +269,7 @@ static inline int m6502_step() {
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case 0xDE: DEC( & RAM[ addr_abs_X() ] ); return 7; // DEC abs,X
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// case 0xDF:
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case 0xE0: CPX( fetch() ); return 2; // CPX imm
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case 0xE1: SBC( memread( addr_X_ind() ) ) ; return 6; // SBC (ind,X)
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case 0xE1: SBC( memread( addr_X_ind() ) ) ; return 6; // SBC (X,ind)
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// case 0xE2:
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// case 0xE3:
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case 0xE4: CPX( memread_zp( fetch() ) ); return 3; // CPX zpg
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@ -330,9 +330,9 @@ static inline void m6502_run() {
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// unsigned long long s = rdtsc();
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unsigned long long e = (unsigned long long)-1LL;
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// for ( unsigned long long int i = 0; i < iterations ; i++ ) {
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for ( unsigned long long int i = 0; i < iterations ; i++ ) {
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// for ( ; m6502.pc ; ) {
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for ( ; ; ) {
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// for ( ; ; ) {
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if ( m6502.interrupt_flag ) {
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switch (m6502.interrupt) {
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case NMI:
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@ -395,7 +395,7 @@ void init() {
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// reset vector
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m6502.pc = memread16( 0xFFFC );
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m6502.sp = 0x01FF;
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m6502.sp = 0xFF;
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uint8_t counter[] = {
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@ -48,7 +48,7 @@ typedef struct m6502_s {
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} flags; // Status Register
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};
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uint16_t pc; // Program Counter
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uint16_t sp; // Stack Pointer
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uint8_t sp; // Stack Pointer ( stack addr = 0x01 + sp )
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unsigned clk; // Clock Counter
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union {
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@ -217,6 +217,12 @@ static inline uint16_t addr_zp_ind( uint8_t addr ) {
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static inline uint16_t addr_X_ind() {
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return addr_zp_ind( fetch() + m6502.X );
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}
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static inline uint8_t src_X_ind() {
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return memread( addr_X_ind() );
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}
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static inline uint8_t * dest_X_ind() {
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return & RAM[ addr_X_ind() ];
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}
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/**
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ind,Y .... indirect, Y-indexed OPC ($LL),Y
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@ -236,6 +242,17 @@ static inline uint16_t addr_ind_Y() {
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static inline uint16_t addr_abs_X() {
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return fetch16() + m6502.X;
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}
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static inline uint8_t src_abs_X() {
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return memread( addr_abs_X() );
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}
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static inline uint8_t * dest_abs_X() {
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return & RAM[ addr_abs_X() ];
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}
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static inline uint16_t abs_addr() {
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return fetch16();
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}
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/**
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abs,Y .... absolute, Y-indexed OPC $LLHH,Y
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@ -244,6 +261,12 @@ static inline uint16_t addr_abs_X() {
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static inline uint16_t addr_abs_Y() {
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return fetch16() + m6502.Y;
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}
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static inline uint8_t src_abs_Y() {
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return memread(addr_abs_Y());
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}
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static inline uint8_t * dest_abs_Y() {
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return & RAM[ addr_abs_Y() ];
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}
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/**
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zpg .... zeropage OPC $LL
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@ -252,6 +275,12 @@ static inline uint16_t addr_abs_Y() {
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static inline uint16_t addr_zp() {
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return fetch();
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}
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static inline uint8_t src_zp() {
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return memread_zp(addr_zp());
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}
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static inline uint8_t * dest_zp() {
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return & RAM[ addr_zp() ];
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}
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/**
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zpg,X .... zeropage, X-indexed OPC $LL,X
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@ -11,10 +11,16 @@ import Cocoa
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class ViewController: NSViewController {
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@IBOutlet weak var display: NSTextFieldCell!
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// static let charConvStr : String =
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// "@🄰🄱🄲🄳🄴🄵🄶🄷🄸🄹🄺🄻🄼🄽🄾🄿🅀🅁🅂🅃🅄🅅🅆🅇🅈🅉[\\]^_ !\"#$%&'()*+,-./0123456789:;<=>?" +
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// "@🅰🅱🅲🅳🅴🅵🅶🅷🅸🅹🅺🅻🅼🅽🅾🅿🆀🆁🆂🆃🆄🆅🆆🆇🆈🆉[\\]^_⬛︎!\"#$%&'()*+,-./0123456789:;<=>?" + // FL
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// "@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\\]^_ !\"#$%&'()*+,-./0123456789:;<=>?" +
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// "@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\\]^_`abcdefghijklmnopqrstuvwxyz{|}~?"
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static let charConvStr : String =
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"@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\\]^_ !\"#$%&'()*+,-./0123456789:;<=>?" +
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"@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\\]^_ !\"#$%&'()*+,-./0123456789:;<=>?" +
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"@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\\]^_░!\"#$%&'()*+,-./0123456789:;<=>?" + // FL
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"@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\\]^_ !\"#$%&'()*+,-./0123456789:;<=>?" +
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"@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\\]^_`abcdefghijklmnopqrstuvwxyz{|}~?"
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@ -57,9 +63,9 @@ class ViewController: NSViewController {
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print( "\ncharacter = " + (event.characters ?? ""))
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if let chars = event.characters {
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let char = chars[chars.startIndex]
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let char = chars.uppercased()[chars.startIndex]
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if let code = char.asciiValue {
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var A2code = code + 0x60
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var A2code = code | 0x80
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if ( code == 13 ) {
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A2code = 141
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@ -43,14 +43,22 @@ union {
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static inline void set_flags_N( uint8_t test ) {
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m6502.flags.N = BITTEST(test, 7);
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dbgPrintf("%c", m6502.flags.N ? 'N' : 'n');
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}
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static inline void set_flags_V( uint8_t test ) {
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m6502.flags.V = BITTEST(test, 6);
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dbgPrintf("%c", m6502.flags.V ? 'V' : 'v');
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}
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static inline void set_flags_Z( uint8_t test ) {
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m6502.flags.Z = test == 0;
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dbgPrintf("%c", m6502.flags.Z ? 'Z' : 'z');
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}
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static inline void set_flags_C( int test ) {
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m6502.flags.C = test >= 0;
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dbgPrintf("%c", m6502.flags.C ? 'C' : 'c');
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}
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static inline void set_flags_NZ( uint8_t test ) {
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@ -65,7 +73,7 @@ static inline void set_flags_NVZ( uint8_t test ) {
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static inline void set_flags_NZC( int test ) {
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set_flags_NZ(test);
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m6502.flags.C = test >= 0;
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set_flags_C(test);
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}
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static inline void set_flags_NZCV( int test ) {
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0
A2Mac/fail1.txt
Normal file
0
A2Mac/fail1.txt
Normal file
@ -30,9 +30,10 @@
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(indirect),Y ADC (oper),Y 71 2 5*
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**/
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static inline void ADC( uint8_t imm ) {
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dbgPrintf("ADC ");
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dbgPrintf("ADC(%02X) A:%02X + %02X ", imm, m6502.A, imm);
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m6502.A += imm + m6502.flags.C;
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set_flags_NZCV( m6502.A );
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dbgPrintf("-> A:%02X ", m6502.A);
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}
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/**
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@ -53,6 +54,7 @@ static inline void ADC( uint8_t imm ) {
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(indirect),Y SBC (oper),Y F1 2 5*
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**/
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static inline void SBC( uint8_t imm ) {
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dbgPrintf("SBC(%02X) ", imm);
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ADC( ~imm );
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}
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@ -9,7 +9,7 @@
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#ifndef __6502_INSTR_BRANCH_H__
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#define __6502_INSTR_BRANCH_H__
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static inline void BR( int8_t reladdr ) {
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static inline void BRA( int8_t reladdr ) {
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m6502.pc += reladdr;
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}
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@ -17,7 +17,7 @@ static inline void BR( int8_t reladdr ) {
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BCC Branch on Carry Clear
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branch on C = 0 N Z C I D V
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- - - - - -
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- - - - - -
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addressing assembler opc bytes cyles
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--------------------------------------------
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@ -26,14 +26,14 @@ static inline void BR( int8_t reladdr ) {
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static inline void BCC( int8_t reladdr ) {
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dbgPrintf("BCC ");
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if ( m6502.flags.C == 0 )
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BR( reladdr );
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BRA( reladdr );
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}
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/**
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BCS Branch on Carry Set
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branch on C = 1 N Z C I D V
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- - - - - -
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- - - - - -
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addressing assembler opc bytes cyles
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--------------------------------------------
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@ -42,14 +42,14 @@ static inline void BCC( int8_t reladdr ) {
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static inline void BCS( int8_t reladdr ) {
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dbgPrintf("BCS ");
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if ( m6502.flags.C == 1 )
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BR( reladdr );
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BRA( reladdr );
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}
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/**
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BNE Branch on Result not Zero
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branch on Z = 0 N Z C I D V
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- - - - - -
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- - - - - -
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addressing assembler opc bytes cyles
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--------------------------------------------
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@ -58,14 +58,14 @@ static inline void BCS( int8_t reladdr ) {
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static inline void BNE( int8_t reladdr ) {
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dbgPrintf("BNE ");
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if ( m6502.flags.Z == 0 )
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BR( reladdr );
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BRA( reladdr );
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}
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/**
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BEQ Branch on Result Zero
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branch on Z = 1 N Z C I D V
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- - - - - -
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- - - - - -
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addressing assembler opc bytes cyles
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--------------------------------------------
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@ -74,14 +74,14 @@ static inline void BNE( int8_t reladdr ) {
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static inline void BEQ( int8_t reladdr ) {
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dbgPrintf("BEQ ");
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if ( m6502.flags.Z == 1 )
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BR( reladdr );
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BRA( reladdr );
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}
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/**
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BPL Branch on Result Plus
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branch on N = 0 N Z C I D V
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- - - - - -
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- - - - - -
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addressing assembler opc bytes cyles
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--------------------------------------------
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@ -90,14 +90,14 @@ static inline void BEQ( int8_t reladdr ) {
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static inline void BPL( int8_t reladdr ) {
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dbgPrintf("BPL ");
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if ( m6502.flags.N == 0 )
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BR( reladdr );
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BRA( reladdr );
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}
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/**
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BMI Branch on Result Minus
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branch on N = 1 N Z C I D V
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- - - - - -
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- - - - - -
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addressing assembler opc bytes cyles
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--------------------------------------------
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@ -106,14 +106,14 @@ static inline void BPL( int8_t reladdr ) {
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static inline void BMI( int8_t reladdr ) {
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dbgPrintf("BMI ");
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if ( m6502.flags.N == 1 )
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BR( reladdr );
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BRA( reladdr );
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}
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/**
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BVC Branch on Overflow Clear
|
||||
|
||||
branch on V = 0 N Z C I D V
|
||||
- - - - - -
|
||||
- - - - - -
|
||||
|
||||
addressing assembler opc bytes cyles
|
||||
--------------------------------------------
|
||||
@ -122,14 +122,14 @@ static inline void BMI( int8_t reladdr ) {
|
||||
static inline void BVC( int8_t reladdr ) {
|
||||
dbgPrintf("BVC ");
|
||||
if ( m6502.flags.V == 0 )
|
||||
BR( reladdr );
|
||||
BRA( reladdr );
|
||||
}
|
||||
|
||||
/**
|
||||
BVS Branch on Overflow Set
|
||||
|
||||
branch on V = 1 N Z C I D V
|
||||
- - - - - -
|
||||
- - - - - -
|
||||
|
||||
addressing assembler opc bytes cyles
|
||||
--------------------------------------------
|
||||
@ -138,7 +138,7 @@ static inline void BVC( int8_t reladdr ) {
|
||||
static inline void BVS( int8_t reladdr ) {
|
||||
dbgPrintf("BVS ");
|
||||
if ( m6502.flags.V == 1 )
|
||||
BR( reladdr );
|
||||
BRA( reladdr );
|
||||
}
|
||||
|
||||
#endif // __6502_INSTR_BRANCH_H__
|
||||
|
@ -47,7 +47,7 @@ static inline void JSR( uint16_t addr ) {
|
||||
RTS Return from Subroutine
|
||||
|
||||
pull PC, PC+1 -> PC N Z C I D V
|
||||
- - - - - -
|
||||
- - - - - -
|
||||
|
||||
addressing assembler opc bytes cyles
|
||||
--------------------------------------------
|
||||
|
@ -16,7 +16,7 @@
|
||||
the zeroflag is set to the result of operand AND accumulator.
|
||||
|
||||
A AND M, M7 -> N, M6 -> V N Z C I D V
|
||||
M7 + - - - M6
|
||||
M7 + - - - M6
|
||||
|
||||
addressing assembler opc bytes cyles
|
||||
--------------------------------------------
|
||||
@ -25,17 +25,18 @@
|
||||
|
||||
**/
|
||||
static inline void BIT( uint8_t imm ) {
|
||||
dbgPrintf("BIT ");
|
||||
m6502.flags.N = BITTEST(imm, 7);
|
||||
m6502.flags.V = BITTEST(imm, 6);
|
||||
m6502.flags.Z = ( m6502.A & imm ) == 0;
|
||||
dbgPrintf("BIT(%02X) ", imm);
|
||||
uint8_t m = m6502.A & imm;
|
||||
m6502.flags.N = BITTEST(m, 7);
|
||||
m6502.flags.V = BITTEST(m, 6);
|
||||
m6502.flags.Z = m == 0;
|
||||
}
|
||||
|
||||
/**
|
||||
CMP Compare Memory with Accumulator
|
||||
|
||||
A - M N Z C I D V
|
||||
+ + + - - -
|
||||
+ + + - - -
|
||||
|
||||
addressing assembler opc bytes cyles
|
||||
--------------------------------------------
|
||||
@ -49,7 +50,7 @@ static inline void BIT( uint8_t imm ) {
|
||||
(indirect),Y CMP (oper),Y D1 2 5*
|
||||
**/
|
||||
static inline void CMP( uint8_t imm ) {
|
||||
dbgPrintf("CMP ");
|
||||
dbgPrintf("CMP(%02X) ", imm);
|
||||
set_flags_NZC( (int)m6502.A - imm );
|
||||
}
|
||||
|
||||
@ -57,7 +58,7 @@ static inline void CMP( uint8_t imm ) {
|
||||
CPX Compare Memory and Index X
|
||||
|
||||
X - M N Z C I D V
|
||||
+ + + - - -
|
||||
+ + + - - -
|
||||
|
||||
addressing assembler opc bytes cyles
|
||||
--------------------------------------------
|
||||
@ -66,7 +67,7 @@ static inline void CMP( uint8_t imm ) {
|
||||
absolute CPX oper EC 3 4
|
||||
**/
|
||||
static inline void CPX( uint8_t imm ) {
|
||||
dbgPrintf("CPX ");
|
||||
dbgPrintf("CPX(%02X) ", imm);
|
||||
set_flags_NZC( (int)m6502.X - imm );
|
||||
}
|
||||
|
||||
@ -83,7 +84,7 @@ static inline void CPX( uint8_t imm ) {
|
||||
absolute CPY oper CC 3 4
|
||||
**/
|
||||
static inline void CPY( uint8_t imm ) {
|
||||
dbgPrintf("CPY ");
|
||||
dbgPrintf("CPY(%02X) ", imm);
|
||||
set_flags_NZC( (int)m6502.Y - imm );
|
||||
}
|
||||
|
||||
|
@ -24,9 +24,9 @@
|
||||
absolute,X INC oper,X FE 3 7
|
||||
**/
|
||||
static inline void INC( uint8_t * dst ) {
|
||||
dbgPrintf("INC ");
|
||||
(*dst)++;
|
||||
set_flags_NZ(*dst);
|
||||
dbgPrintf("INC %02X -> ", *dst);
|
||||
set_flags_NZ( ++(*dst) );
|
||||
dbgPrintf("%02X ", *dst);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -40,9 +40,9 @@ static inline void INC( uint8_t * dst ) {
|
||||
implied INX E8 1 2
|
||||
**/
|
||||
static inline void INX() {
|
||||
dbgPrintf("INX ");
|
||||
m6502.X++;
|
||||
set_flags_NZ(m6502.X);
|
||||
dbgPrintf("INX %02X -> ", m6502.X);
|
||||
set_flags_NZ( ++m6502.X );
|
||||
dbgPrintf("%02X ", m6502.X);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -57,7 +57,7 @@ static inline void INX() {
|
||||
**/
|
||||
static inline void INY() {
|
||||
dbgPrintf("INY %02X -> ", m6502.Y);
|
||||
set_flags_NZ(++m6502.Y);
|
||||
set_flags_NZ( ++m6502.Y );
|
||||
dbgPrintf("%02X ", m6502.Y);
|
||||
}
|
||||
|
||||
@ -75,9 +75,9 @@ static inline void INY() {
|
||||
absolute,X DEC oper,X DE 3 7
|
||||
**/
|
||||
static inline void DEC( uint8_t * dst ) {
|
||||
dbgPrintf("DEC ");
|
||||
(*dst)--;
|
||||
set_flags_NZ(*dst);
|
||||
dbgPrintf("DEC %02X -> ", *dst);
|
||||
set_flags_NZ( --(*dst) );
|
||||
dbgPrintf("%02X ", *dst);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -91,9 +91,9 @@ static inline void DEC( uint8_t * dst ) {
|
||||
implied DEC CA 1 2
|
||||
**/
|
||||
static inline void DEX() {
|
||||
dbgPrintf("DEX ");
|
||||
m6502.X--;
|
||||
set_flags_NZ(m6502.X);
|
||||
dbgPrintf("DEX %02X -> ", m6502.X);
|
||||
set_flags_NZ( --m6502.X );
|
||||
dbgPrintf("%02X ", m6502.X);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -107,9 +107,9 @@ static inline void DEX() {
|
||||
implied DEC 88 1 2
|
||||
**/
|
||||
static inline void DEY() {
|
||||
dbgPrintf("DEY ");
|
||||
m6502.Y--;
|
||||
set_flags_NZ(m6502.Y);
|
||||
dbgPrintf("DEY %02X -> ", m6502.Y);
|
||||
set_flags_NZ( --m6502.Y );
|
||||
dbgPrintf("%02X ", m6502.Y);
|
||||
}
|
||||
|
||||
#endif // __6502_INSTR_INC_DEC_H__
|
||||
|
@ -70,7 +70,7 @@ static inline void LDX( uint8_t imm ) {
|
||||
absolute,X LDY oper,X BC 3 4*
|
||||
**/
|
||||
static inline void LDY( uint8_t imm ) {
|
||||
dbgPrintf("LDY ");
|
||||
dbgPrintf("LDY(%02X) ", imm);
|
||||
m6502.Y = imm;
|
||||
set_flags_NZ(imm);
|
||||
}
|
||||
@ -95,6 +95,10 @@ static inline void STR( uint8_t * dst, uint8_t imm ) {
|
||||
// uint16_t v = dst - RAM;
|
||||
// if ( ( v >= 0x400 ) && ( v < 0x800 ) ) {
|
||||
// char c = charConv[imm];
|
||||
// if ( c == '?' ) {
|
||||
// printf("? SYNTAX ERROR\n");
|
||||
// }
|
||||
|
||||
// if (( imm > ' ' ) && ( c < 0x7F ))
|
||||
// printf("%04X: t:%02X '%c'\n", v, imm, isprint(c) ? c : ' ');
|
||||
// }
|
||||
|
@ -28,7 +28,7 @@
|
||||
(indirect),Y ORA (oper),Y 11 2 5*
|
||||
**/
|
||||
static inline void ORA( uint8_t imm ) {
|
||||
dbgPrintf("ORA ");
|
||||
dbgPrintf("ORA(%02X) ", imm);
|
||||
m6502.A |= imm;
|
||||
set_flags_NZ( m6502.A );
|
||||
}
|
||||
@ -51,7 +51,7 @@ static inline void ORA( uint8_t imm ) {
|
||||
(indirect),Y AND (oper),Y 31 2 5*
|
||||
**/
|
||||
static inline void AND( uint8_t imm ) {
|
||||
dbgPrintf("AND ");
|
||||
dbgPrintf("AND(%02X) ", imm);
|
||||
m6502.A &= imm;
|
||||
set_flags_NZ( m6502.A );
|
||||
}
|
||||
@ -74,7 +74,7 @@ static inline void AND( uint8_t imm ) {
|
||||
(indirect),Y EOR (oper),Y 51 2 5*
|
||||
**/
|
||||
static inline void EOR( uint8_t imm ) {
|
||||
dbgPrintf("EOR ");
|
||||
dbgPrintf("EOR(%02X) ", imm);
|
||||
m6502.A ^= imm;
|
||||
set_flags_NZ( m6502.A );
|
||||
}
|
||||
|
@ -26,7 +26,7 @@
|
||||
**/
|
||||
static inline void ASL( uint8_t * dst ) {
|
||||
dbgPrintf("ASL ");
|
||||
m6502.flags.C = (*dst & (1<<7)) >> 7;
|
||||
m6502.flags.C = *dst >> 7;
|
||||
*dst <<= 1;
|
||||
set_flags_NZ( *dst );
|
||||
}
|
||||
@ -69,7 +69,7 @@ static inline void LSR( uint8_t * dst ) {
|
||||
static inline void ROL( uint8_t * dst ) {
|
||||
dbgPrintf("ROL ");
|
||||
uint8_t C = m6502.flags.C;
|
||||
m6502.flags.C = (*dst & (1<<7)) >> 7;
|
||||
m6502.flags.C = *dst >> 7;
|
||||
*dst <<= 1;
|
||||
*dst |= C;
|
||||
set_flags_NZ( *dst );
|
||||
@ -92,7 +92,7 @@ static inline void ROL( uint8_t * dst ) {
|
||||
static inline void ROR( uint8_t * dst ) {
|
||||
dbgPrintf("ROR ");
|
||||
uint8_t C = m6502.flags.C << 7;
|
||||
m6502.flags.C = *dst;
|
||||
m6502.flags.C = *dst & 1;
|
||||
*dst >>= 1;
|
||||
*dst |= C;
|
||||
set_flags_NZ( *dst );
|
||||
|
@ -11,11 +11,11 @@
|
||||
|
||||
|
||||
static inline void PUSH( uint8_t n ) {
|
||||
memwrite( m6502.sp--, n );
|
||||
RAM[ 0x100 + m6502.sp-- ] = n;
|
||||
}
|
||||
|
||||
static inline uint8_t POP() {
|
||||
return memread( ++m6502.sp );
|
||||
return RAM[ 0x100 + (++m6502.sp) ];
|
||||
}
|
||||
|
||||
static inline void PUSH_addr( uint16_t addr ) {
|
||||
@ -56,6 +56,7 @@ static inline void PHA() {
|
||||
static inline void PLA() {
|
||||
dbgPrintf("PLA ");
|
||||
m6502.A = POP();
|
||||
set_flags_NZ(m6502.A);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -14,7 +14,7 @@
|
||||
TAX Transfer Accumulator to Index X
|
||||
|
||||
A -> X N Z C I D V
|
||||
+ + - - - -
|
||||
+ + - - - -
|
||||
|
||||
addressing assembler opc bytes cyles
|
||||
--------------------------------------------
|
||||
@ -30,7 +30,7 @@ static inline void TAX() {
|
||||
TXA Transfer Index X to Accumulator
|
||||
|
||||
X -> A N Z C I D V
|
||||
+ + - - - -
|
||||
+ + - - - -
|
||||
|
||||
addressing assembler opc bytes cyles
|
||||
--------------------------------------------
|
||||
@ -47,7 +47,7 @@ static inline void TXA() {
|
||||
TAY Transfer Accumulator to Index Y
|
||||
|
||||
A -> Y N Z C I D V
|
||||
+ + - - - -
|
||||
+ + - - - -
|
||||
|
||||
addressing assembler opc bytes cyles
|
||||
--------------------------------------------
|
||||
@ -63,7 +63,7 @@ static inline void TAY() {
|
||||
TYA Transfer Index Y to Accumulator
|
||||
|
||||
Y -> A N Z C I D V
|
||||
+ + - - - -
|
||||
+ + - - - -
|
||||
|
||||
addressing assembler opc bytes cyles
|
||||
--------------------------------------------
|
||||
@ -79,7 +79,7 @@ static inline void TYA() {
|
||||
TSX Transfer Stack Pointer to Index X
|
||||
|
||||
SP -> X N Z C I D V
|
||||
+ + - - - -
|
||||
+ + - - - -
|
||||
|
||||
addressing assembler opc bytes cyles
|
||||
--------------------------------------------
|
||||
@ -95,7 +95,7 @@ static inline void TSX() {
|
||||
TXS Transfer Index X to Stack Register
|
||||
|
||||
X -> SP N Z C I D V
|
||||
- - - - - -
|
||||
- - - - - -
|
||||
|
||||
addressing assembler opc bytes cyles
|
||||
--------------------------------------------
|
||||
|
Loading…
Reference in New Issue
Block a user