mirror of
https://github.com/trudnai/Steve2.git
synced 2025-01-21 21:32:51 +00:00
- Speed Enhancement of Disk II reading
- Precise Clock calculation to determine disk rotation for the CPU cycles - Memory Page Tables - Language Card Emulation -- needs some more work on it
This commit is contained in:
Tamas Rudnai
parent
cea4eed922
commit
e33c1dc34b
@ -9,6 +9,8 @@
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/* Begin PBXBuildFile section */
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32439F8722ECD8AD0077AAE0 /* 6502.c in Sources */ = {isa = PBXBuildFile; fileRef = 32439F7422ECD8AD0077AAE0 /* 6502.c */; };
|
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32439F8822ECD8AD0077AAE0 /* apple.rom in Resources */ = {isa = PBXBuildFile; fileRef = 32439F8422ECD8AD0077AAE0 /* apple.rom */; };
|
||||
3262F37623E169F8008BDB95 /* spk_dn.wav in Resources */ = {isa = PBXBuildFile; fileRef = 3262F37423E169F8008BDB95 /* spk_dn.wav */; };
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3262F37723E169F8008BDB95 /* spk_up.wav in Resources */ = {isa = PBXBuildFile; fileRef = 3262F37523E169F8008BDB95 /* spk_up.wav */; };
|
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326ED2EF232D7A0000A41337 /* 6502_functional_test.bin in Resources */ = {isa = PBXBuildFile; fileRef = 326ED2EE232D7A0000A41337 /* 6502_functional_test.bin */; };
|
||||
32BFFB5B22EACC630003B53F /* AppDelegate.swift in Sources */ = {isa = PBXBuildFile; fileRef = 32BFFB5A22EACC630003B53F /* AppDelegate.swift */; };
|
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32BFFB5D22EACC630003B53F /* ViewController.swift in Sources */ = {isa = PBXBuildFile; fileRef = 32BFFB5C22EACC630003B53F /* ViewController.swift */; };
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@ -82,6 +84,8 @@
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32439F8422ECD8AD0077AAE0 /* apple.rom */ = {isa = PBXFileReference; lastKnownFileType = file; path = apple.rom; sourceTree = "<group>"; };
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32439F8522ECD8AD0077AAE0 /* 6502.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = 6502.h; sourceTree = "<group>"; };
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32439F8622ECD8AD0077AAE0 /* common.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = common.h; sourceTree = "<group>"; };
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3262F37423E169F8008BDB95 /* spk_dn.wav */ = {isa = PBXFileReference; lastKnownFileType = audio.wav; path = spk_dn.wav; sourceTree = "<group>"; };
|
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3262F37523E169F8008BDB95 /* spk_up.wav */ = {isa = PBXFileReference; lastKnownFileType = audio.wav; path = spk_up.wav; sourceTree = "<group>"; };
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3264261023284F6F008B615F /* Apple2_mmio_8bit_ioaddr.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = Apple2_mmio_8bit_ioaddr.h; sourceTree = "<group>"; };
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326426112328ADF4008B615F /* Apple_II_ROM.s */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.asm; path = Apple_II_ROM.s; sourceTree = "<group>"; };
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326C50802383CC0B00A05420 /* woz.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = woz.h; sourceTree = "<group>"; };
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@ -173,6 +177,15 @@
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path = instructions;
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sourceTree = "<group>";
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};
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3262F37823E17013008BDB95 /* Resources */ = {
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isa = PBXGroup;
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children = (
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3262F37423E169F8008BDB95 /* spk_dn.wav */,
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3262F37523E169F8008BDB95 /* spk_up.wav */,
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);
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path = Resources;
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sourceTree = "<group>";
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};
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32BFFB4E22EACC630003B53F = {
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isa = PBXGroup;
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children = (
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@ -201,6 +214,7 @@
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32BFFB5922EACC630003B53F /* A2Mac */ = {
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isa = PBXGroup;
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children = (
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3262F37823E17013008BDB95 /* Resources */,
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32439F7522ECD8AD0077AAE0 /* instructions */,
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32439F8522ECD8AD0077AAE0 /* 6502.h */,
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32439F7422ECD8AD0077AAE0 /* 6502.c */,
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@ -389,10 +403,12 @@
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buildActionMask = 2147483647;
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files = (
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32EDB7A223272CA80073AF2D /* fail1.txt in Resources */,
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3262F37723E169F8008BDB95 /* spk_up.wav in Resources */,
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32C4533123335E560000EBA1 /* Main.storyboard in Resources */,
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32BFFB5F22EACC660003B53F /* Assets.xcassets in Resources */,
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32439F8822ECD8AD0077AAE0 /* apple.rom in Resources */,
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326ED2EF232D7A0000A41337 /* 6502_functional_test.bin in Resources */,
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3262F37623E169F8008BDB95 /* spk_dn.wav in Resources */,
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);
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runOnlyForDeploymentPostprocessing = 0;
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};
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@ -644,7 +660,11 @@
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CODE_SIGN_STYLE = Automatic;
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COMBINE_HIDPI_IMAGES = YES;
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DEVELOPMENT_TEAM = W6TFQTZ4DA;
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GCC_ENABLE_CPP_EXCEPTIONS = YES;
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GCC_ENABLE_CPP_RTTI = YES;
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GCC_ENABLE_OBJC_EXCEPTIONS = YES;
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GCC_FAST_MATH = YES;
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GCC_UNROLL_LOOPS = NO;
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INFOPLIST_FILE = A2Mac/Info.plist;
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LD_RUNPATH_SEARCH_PATHS = (
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"$(inherited)",
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@ -674,8 +694,12 @@
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CODE_SIGN_STYLE = Automatic;
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COMBINE_HIDPI_IMAGES = YES;
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DEVELOPMENT_TEAM = W6TFQTZ4DA;
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GCC_ENABLE_CPP_EXCEPTIONS = YES;
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GCC_ENABLE_CPP_RTTI = YES;
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GCC_ENABLE_OBJC_EXCEPTIONS = YES;
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GCC_FAST_MATH = YES;
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GCC_OPTIMIZATION_LEVEL = fast;
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GCC_UNROLL_LOOPS = NO;
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INFOPLIST_FILE = A2Mac/Info.plist;
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LD_RUNPATH_SEARCH_PATHS = (
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"$(inherited)",
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33
A2Mac/6502.c
33
A2Mac/6502.c
@ -27,11 +27,16 @@ woz_chunk_header_t woz_chunk_header;
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woz_tmap_t woz_tmap;
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woz_trks_t woz_trks;
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uint64_t clklast = 0;
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uint64_t clkelpased = 0;
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uint16_t trackOffset = 0;
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uint8_t bitOffset = 0;
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FILE * outdev = NULL;
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void ViewController_spk_up_play(void);
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void ViewController_spk_dn_play(void);
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#ifdef DEBUG
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#define INLINE
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@ -66,15 +71,18 @@ INLINE unsigned long long rdtsc(void)
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return ( (unsigned long long)lo) | ( ((unsigned long long)hi) << 32 );
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}
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m6502_t m6502 = {
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0, // A
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0, // X
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0, // Y
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0, // SR
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0, // PC
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0, // SP
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0, // clk
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// 0, // clk
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0, // clktime
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0, // trace
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0, // step
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0, // brk
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@ -156,10 +164,6 @@ void hires_Update () {
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**/
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#include "6502_instructions.h"
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/////
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//#ifdef SPEEDTEST
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unsigned long long int clktime = 0;
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//#endif
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INLINE int m6502_Step() {
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@ -734,9 +738,7 @@ void m6502_Run() {
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#endif // INTERRUPT_CHECK_PER_STEP
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// dbgPrintf("%llu %04X: ", clktime, m6502.PC);
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//#ifdef SPEEDTEST
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clktime +=
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//#endif
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m6502.clktime +=
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clk = m6502_Step();
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printDisassembly( outdev );
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@ -789,7 +791,7 @@ void m6502_Run() {
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// mhz = clktime / (execution_time * M);
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}
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void read_rom( const char * filename, const uint16_t addr ) {
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void read_rom( const char * filename, const uint8_t * rom, const uint16_t addr ) {
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FILE * f = fopen(filename, "rb");
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if (f == NULL) {
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perror("Failed: ");
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@ -800,7 +802,7 @@ void read_rom( const char * filename, const uint16_t addr ) {
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uint16_t flen = ftell(f);
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fseek(f, 0L, SEEK_SET);
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fread( RAM + addr, 1, flen, f);
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fread( rom + addr, 1, flen, f);
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fclose(f);
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}
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@ -897,10 +899,11 @@ void m6502_ColdReset() {
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m6502.PC = 0x400;
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#else
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// Apple ][e ROM
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read_rom("/Users/trudnai/Library/Containers/com.gamealloy.A2Mac/Data/Apple2Plus.rom", 0xD000);
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// Apple ][+ ROM
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read_rom("/Users/trudnai/Library/Containers/com.gamealloy.A2Mac/Data/Apple2Plus.rom", Apple2_12K_ROM, 0);
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memcpy(Apple2_64K_RAM + 0xD000, Apple2_12K_ROM, sizeof(Apple2_12K_ROM));
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// Disk ][ ROM in Slot 6
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read_rom("/Users/trudnai/Library/Containers/com.gamealloy.A2Mac/Data/DISK_II_C600.ROM", 0xC600);
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read_rom("/Users/trudnai/Library/Containers/com.gamealloy.A2Mac/Data/DISK_II_C600.ROM", Apple2_64K_RAM, 0xC600);
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// WOZ DISK
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// read_woz("/Users/trudnai/Library/Containers/com.gamealloy.A2Mac/Data/DOS 3.3 System Master.woz");
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@ -1050,7 +1053,7 @@ void tst6502() {
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double execution_time = (double)elapsed / tick_per_sec;
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double mips = inst_cnt / (execution_time * M);
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double mhz = clktime / (execution_time * M);
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double mhz = m6502.clktime / (execution_time * M);
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printf("clk:%llu Elpased time: (%llu / %u / %llu), %.3lfs (%.3lf MIPS, %.3lf MHz)\n", iterations *3, tick_per_sec, MHz_6502, tick_6502_per_sec, execution_time, mips, mhz);
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// printf(" dd:%llu ee:%llu nn:%llu\n", dd, ee, ee - dd);
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#endif
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@ -71,13 +71,17 @@ typedef struct m6502_s {
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};
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uint16_t PC; // Program Counter
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uint8_t SP; // Stack Pointer ( stack addr = 0x01 + sp )
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unsigned clk; // Clock Counter
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// unsigned clk; // Clock Counter
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uint64_t clktime;
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debugLevel_t dbgLevel; // 0: No Debug, 1: Disassembly Only, 2: Run till BRK, 3: StepByStep
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union {
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unsigned int IF; // interrut flag
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interrupt_t interrupt;
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};
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} m6502_t;
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@ -24,11 +24,149 @@ typedef union {
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uint16_t shift16;
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} WOZread_t;
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uint8_t Apple2_64K_RAM[ 64 * KB ] = {0};
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uint8_t * RAM = Apple2_64K_RAM;
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WOZread_t WOZread = {0};
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typedef union address16_u {
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uint16_t addr;
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struct {
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uint8_t offs;
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uint8_t page;
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};
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} address16_t;
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uint8_t Apple2_Dummy_Page[ 1 * PG ]; // Dummy Page for discarding data
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uint8_t Apple2_512_AUX[ 2 * PG ] = {0}; // Auxiliary bank for page 0 and 1
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uint8_t Apple2_12K_ROM[ 12 * KB ] = {0}; // ROM D0, D8, E0, E8, F0, F8
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uint8_t Apple2_16K_RAM[ 16 * KB ] = {0}; // 16K Memory Expansion Card
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uint8_t Apple2_64K_RAM[ 64 * KB ] = {0}; // Main Memory
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uint8_t * RAM = Apple2_64K_RAM; // Pointer to the main memory so we can use this from Swift
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#define DEF_RAM_PAGE(mem,pg) \
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(mem) + ((pg) << 8)
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#define DEF_RAM_PAGE16(mem,pg) \
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DEF_RAM_PAGE(mem, (pg) + 0x00), \
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DEF_RAM_PAGE(mem, (pg) + 0x01), \
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DEF_RAM_PAGE(mem, (pg) + 0x02), \
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DEF_RAM_PAGE(mem, (pg) + 0x03), \
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DEF_RAM_PAGE(mem, (pg) + 0x04), \
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DEF_RAM_PAGE(mem, (pg) + 0x05), \
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DEF_RAM_PAGE(mem, (pg) + 0x06), \
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DEF_RAM_PAGE(mem, (pg) + 0x07), \
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DEF_RAM_PAGE(mem, (pg) + 0x08), \
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DEF_RAM_PAGE(mem, (pg) + 0x09), \
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DEF_RAM_PAGE(mem, (pg) + 0x0A), \
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DEF_RAM_PAGE(mem, (pg) + 0x0B), \
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DEF_RAM_PAGE(mem, (pg) + 0x0C), \
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DEF_RAM_PAGE(mem, (pg) + 0x0D), \
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DEF_RAM_PAGE(mem, (pg) + 0x0E), \
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DEF_RAM_PAGE(mem, (pg) + 0x0F)
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#define SWITCH_RAM_PAGE16( tbl,tpg, mem,mpg ) \
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(tbl)[ (tpg) + 0x00 ] = DEF_RAM_PAGE(mem, (mpg) + 0x00); \
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(tbl)[ (tpg) + 0x01 ] = DEF_RAM_PAGE(mem, (mpg) + 0x01); \
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(tbl)[ (tpg) + 0x02 ] = DEF_RAM_PAGE(mem, (mpg) + 0x02); \
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(tbl)[ (tpg) + 0x03 ] = DEF_RAM_PAGE(mem, (mpg) + 0x03); \
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(tbl)[ (tpg) + 0x04 ] = DEF_RAM_PAGE(mem, (mpg) + 0x04); \
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(tbl)[ (tpg) + 0x05 ] = DEF_RAM_PAGE(mem, (mpg) + 0x05); \
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(tbl)[ (tpg) + 0x06 ] = DEF_RAM_PAGE(mem, (mpg) + 0x06); \
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(tbl)[ (tpg) + 0x07 ] = DEF_RAM_PAGE(mem, (mpg) + 0x07); \
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(tbl)[ (tpg) + 0x08 ] = DEF_RAM_PAGE(mem, (mpg) + 0x08); \
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(tbl)[ (tpg) + 0x09 ] = DEF_RAM_PAGE(mem, (mpg) + 0x09); \
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(tbl)[ (tpg) + 0x0A ] = DEF_RAM_PAGE(mem, (mpg) + 0x0A); \
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(tbl)[ (tpg) + 0x0B ] = DEF_RAM_PAGE(mem, (mpg) + 0x0B); \
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(tbl)[ (tpg) + 0x0C ] = DEF_RAM_PAGE(mem, (mpg) + 0x0C); \
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(tbl)[ (tpg) + 0x0D ] = DEF_RAM_PAGE(mem, (mpg) + 0x0D); \
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(tbl)[ (tpg) + 0x0E ] = DEF_RAM_PAGE(mem, (mpg) + 0x0E); \
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(tbl)[ (tpg) + 0x0F ] = DEF_RAM_PAGE(mem, (mpg) + 0x0F);
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#define DEF_RAM_DUMMY16 \
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Apple2_Dummy_Page, \
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Apple2_Dummy_Page, \
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Apple2_Dummy_Page, \
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Apple2_Dummy_Page, \
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Apple2_Dummy_Page, \
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Apple2_Dummy_Page, \
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Apple2_Dummy_Page, \
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Apple2_Dummy_Page, \
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Apple2_Dummy_Page, \
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Apple2_Dummy_Page, \
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Apple2_Dummy_Page, \
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Apple2_Dummy_Page, \
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Apple2_Dummy_Page, \
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Apple2_Dummy_Page, \
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Apple2_Dummy_Page, \
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Apple2_Dummy_Page
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#define DEF_RAM_NULL16 \
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NULL, \
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NULL, \
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NULL, \
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NULL, \
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NULL, \
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NULL, \
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NULL, \
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NULL, \
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NULL, \
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NULL, \
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NULL, \
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NULL, \
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NULL, \
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NULL, \
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NULL, \
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NULL
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uint8_t * RAM_PG_RD_TBL[256] = {
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// 48K main memory
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DEF_RAM_PAGE16( Apple2_64K_RAM, 0x00),
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DEF_RAM_PAGE16( Apple2_64K_RAM, 0x10),
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DEF_RAM_PAGE16( Apple2_64K_RAM, 0x20),
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DEF_RAM_PAGE16( Apple2_64K_RAM, 0x30),
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DEF_RAM_PAGE16( Apple2_64K_RAM, 0x40),
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DEF_RAM_PAGE16( Apple2_64K_RAM, 0x50),
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DEF_RAM_PAGE16( Apple2_64K_RAM, 0x60),
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DEF_RAM_PAGE16( Apple2_64K_RAM, 0x70),
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DEF_RAM_PAGE16( Apple2_64K_RAM, 0x80),
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DEF_RAM_PAGE16( Apple2_64K_RAM, 0x90),
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DEF_RAM_PAGE16( Apple2_64K_RAM, 0xA0),
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DEF_RAM_PAGE16( Apple2_64K_RAM, 0xB0),
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// I/O Addresses
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DEF_RAM_PAGE16( Apple2_64K_RAM, 0xC0),
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// Reading from the ROM
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DEF_RAM_PAGE16( Apple2_12K_ROM, 0x00), // D0
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DEF_RAM_PAGE16( Apple2_12K_ROM, 0x10), // E0
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DEF_RAM_PAGE16( Apple2_12K_ROM, 0x20) // F0
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};
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uint8_t * RAM_PG_WR_TBL[256] = {
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// 48K main memory
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DEF_RAM_PAGE16( Apple2_64K_RAM, 0x00),
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DEF_RAM_PAGE16( Apple2_64K_RAM, 0x10),
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DEF_RAM_PAGE16( Apple2_64K_RAM, 0x20),
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DEF_RAM_PAGE16( Apple2_64K_RAM, 0x30),
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DEF_RAM_PAGE16( Apple2_64K_RAM, 0x40),
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DEF_RAM_PAGE16( Apple2_64K_RAM, 0x50),
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DEF_RAM_PAGE16( Apple2_64K_RAM, 0x60),
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DEF_RAM_PAGE16( Apple2_64K_RAM, 0x70),
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DEF_RAM_PAGE16( Apple2_64K_RAM, 0x80),
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DEF_RAM_PAGE16( Apple2_64K_RAM, 0x90),
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DEF_RAM_PAGE16( Apple2_64K_RAM, 0xA0),
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DEF_RAM_PAGE16( Apple2_64K_RAM, 0xB0),
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// I/O Addresses
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DEF_RAM_PAGE16( Apple2_64K_RAM, 0xC0),
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// NO Writing to the ROM
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DEF_RAM_DUMMY16,
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DEF_RAM_DUMMY16,
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DEF_RAM_DUMMY16,
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};
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enum slot {
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SLOT0 = 0x00,
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SLOT1 = 0x10,
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@ -41,10 +179,22 @@ enum slot {
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};
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// Memory Config
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struct MEMcfg_s {
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uint8_t RAM_16K : 1;
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uint8_t RAM_128K : 1;
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uint8_t RD_RAM : 1;
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uint8_t WR_RAM : 1;
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||||
uint8_t RAM_BANK_2 : 1;
|
||||
uint8_t AUX_BANK : 1;
|
||||
} MEMcfg = { 1, 0, 0, 0, 0 };
|
||||
|
||||
enum mmio {
|
||||
io_KBD = 0xC000,
|
||||
io_KBDSTRB = 0xC010,
|
||||
|
||||
|
||||
io_SPKR = 0xC030,
|
||||
|
||||
io_DISK_PHASE0_OFF = 0xC080,
|
||||
io_DISK_PHASE0_ON = 0xC081,
|
||||
io_DISK_PHASE1_OFF = 0xC082,
|
||||
@ -61,7 +211,15 @@ enum mmio {
|
||||
io_DISK_WRITE = 0xC08D,
|
||||
io_DISK_CLEAR = 0xC08E,
|
||||
io_DISK_SHIFT = 0xC08F,
|
||||
|
||||
|
||||
io_MEM_RDRAM_NOWR_2 = 0xC080,
|
||||
io_MEM_RDROM_WRAM_2 = 0xC081,
|
||||
io_MEM_RDROM_NOWR_2 = 0xC082,
|
||||
io_MEM_RDRAM_WRAM_2 = 0xC083,
|
||||
io_MEM_RDRAM_NOWR_1 = 0xC088,
|
||||
io_MEM_RDROM_WRAM_1 = 0xC089,
|
||||
io_MEM_RDROM_NOWR_1 = 0xC08A,
|
||||
io_MEM_RDRAM_WRAM_1 = 0xC08B,
|
||||
};
|
||||
|
||||
|
||||
@ -106,14 +264,6 @@ enum mmio {
|
||||
|
||||
//uint8_t ( * mmio_read [ 64 * KB ] )( uint16_t addr );
|
||||
|
||||
typedef union address16_u {
|
||||
uint16_t addr;
|
||||
struct {
|
||||
uint8_t offs;
|
||||
uint8_t page;
|
||||
};
|
||||
} address16_t;
|
||||
|
||||
|
||||
#define CASE_DISKII(x) \
|
||||
case io_DISK_PHASE0_OFF + SLOT##x: \
|
||||
@ -259,6 +409,9 @@ INLINE void diskII_phase() {
|
||||
printf(", p:%d d:%d l:%d: ph:%u trk:%u)", position, direction, lastPosition, phase.count, woz_tmap.phase[phase.count]);
|
||||
|
||||
}
|
||||
else {
|
||||
// invalid magnet config
|
||||
}
|
||||
|
||||
printf("\n");
|
||||
}
|
||||
@ -268,6 +421,7 @@ INLINE uint8_t ioRead( uint16_t addr ) {
|
||||
dbgPrintf("mmio read:%04X\n", addr);
|
||||
|
||||
uint8_t currentMagnet = 0;
|
||||
int clk = 0;
|
||||
|
||||
switch (addr) {
|
||||
case io_KBD:
|
||||
@ -279,7 +433,89 @@ INLINE uint8_t ioRead( uint16_t addr ) {
|
||||
// printf("io_KBDSTRB\n");
|
||||
return RAM[io_KBD] &= 0x7F;
|
||||
|
||||
case io_SPKR:
|
||||
// TODO: This is very slow!
|
||||
// printf("io_KBDSTRB\n");
|
||||
|
||||
//ViewController_spk_up_play();
|
||||
|
||||
return RAM[io_SPKR];
|
||||
|
||||
// CASE_DISKII(6)
|
||||
|
||||
case io_MEM_RDRAM_NOWR_2:
|
||||
case io_MEM_RDROM_WRAM_2:
|
||||
case io_MEM_RDROM_NOWR_2:
|
||||
case io_MEM_RDRAM_WRAM_2:
|
||||
case io_MEM_RDRAM_NOWR_1:
|
||||
case io_MEM_RDROM_WRAM_1:
|
||||
case io_MEM_RDROM_NOWR_1:
|
||||
case io_MEM_RDRAM_WRAM_1:
|
||||
if ( MEMcfg.RAM_16K || MEMcfg.RAM_128K ) {
|
||||
uint8_t * RAM_BANK = Apple2_16K_RAM;
|
||||
|
||||
// RAM Bank 1 or 2?
|
||||
switch (addr) {
|
||||
case io_MEM_RDRAM_NOWR_2:
|
||||
case io_MEM_RDROM_WRAM_2:
|
||||
case io_MEM_RDROM_NOWR_2:
|
||||
case io_MEM_RDRAM_WRAM_2:
|
||||
MEMcfg.RAM_BANK_2 = 1;
|
||||
RAM_BANK = Apple2_16K_RAM + 0x30;
|
||||
break;
|
||||
|
||||
default:
|
||||
MEMcfg.RAM_BANK_2 = 0;
|
||||
RAM_BANK = Apple2_16K_RAM;
|
||||
break;
|
||||
}
|
||||
|
||||
// is RAM to read or ROM?
|
||||
switch (addr) {
|
||||
case io_MEM_RDRAM_NOWR_2:
|
||||
case io_MEM_RDRAM_WRAM_2:
|
||||
case io_MEM_RDRAM_NOWR_1:
|
||||
case io_MEM_RDRAM_WRAM_1:
|
||||
MEMcfg.RD_RAM = 1;
|
||||
// set the RAM extension to read on the upper memory area
|
||||
SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0xD0, RAM_BANK, 0x00 );
|
||||
SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0xE0, Apple2_16K_RAM, 0x10 );
|
||||
SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0xF0, Apple2_16K_RAM, 0x20 );
|
||||
break;
|
||||
|
||||
default:
|
||||
MEMcfg.RD_RAM = 0;
|
||||
// set the ROM to read on the upper memory area
|
||||
SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0xD0, Apple2_12K_ROM, 0x00 );
|
||||
SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0xE0, Apple2_12K_ROM, 0x10 );
|
||||
SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0xF0, Apple2_12K_ROM, 0x20 );
|
||||
break;
|
||||
}
|
||||
|
||||
// is RAM Writeable?
|
||||
switch (addr) {
|
||||
case io_MEM_RDROM_WRAM_2:
|
||||
case io_MEM_RDRAM_WRAM_2:
|
||||
case io_MEM_RDROM_WRAM_1:
|
||||
case io_MEM_RDRAM_WRAM_1:
|
||||
MEMcfg.WR_RAM = 1;
|
||||
// set the RAM extension to read from the upper memory area
|
||||
SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0xD0, RAM_BANK, 0x00 );
|
||||
SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0xE0, Apple2_16K_RAM, 0x10 );
|
||||
SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0xF0, Apple2_16K_RAM, 0x20 );
|
||||
break;
|
||||
|
||||
default:
|
||||
MEMcfg.WR_RAM = 0;
|
||||
// set the ROM to read on the upper memory area
|
||||
SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0xD0, Apple2_Dummy_Page, 0 );
|
||||
SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0xE0, Apple2_Dummy_Page, 0 );
|
||||
SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0xF0, Apple2_Dummy_Page, 0 );
|
||||
break;
|
||||
}
|
||||
|
||||
} // if there is RAM expansion card installed
|
||||
break;
|
||||
|
||||
// TODO: Make code "card insertable to slot" / aka slot independent and dynamically add/remove
|
||||
case io_DISK_PHASE0_OFF + SLOT6:
|
||||
@ -326,16 +562,29 @@ INLINE uint8_t ioRead( uint16_t addr ) {
|
||||
int track = woz_tmap.phase[phase.count];
|
||||
if (outdev) fprintf(outdev, "track: %d (%d) ", track, phase.count);
|
||||
if ( track >= 40 ) {
|
||||
printf("TRCK TOO HIGH!\n");
|
||||
dbgPrintf("TRCK TOO HIGH!\n");
|
||||
return rand();
|
||||
}
|
||||
|
||||
clkelpased = m6502.clktime - clklast;
|
||||
clklast = m6502.clktime;
|
||||
|
||||
if ( clkelpased > 100 ) {
|
||||
bitOffset = (clkelpased % 32) / 4;
|
||||
trackOffset += (clkelpased / 32) % WOZ_TRACK_BYTE_COUNT;
|
||||
WOZread.latch = woz_trks[track].data[trackOffset];
|
||||
}
|
||||
|
||||
// to avoid infinite loop and to search for bit 7 high
|
||||
for ( int i = 0; i < WOZ_TRACK_BYTE_COUNT * 8; i++ ) {
|
||||
if ( ++bitOffset >= 8 ) {
|
||||
bitOffset = 0;
|
||||
if ( ++trackOffset >= WOZ_TRACK_BYTE_COUNT ) {
|
||||
trackOffset = 0;
|
||||
}
|
||||
// if ( ++trackOffset >= WOZ_TRACK_BYTE_COUNT ) {
|
||||
// trackOffset = 0;
|
||||
// }
|
||||
trackOffset++;
|
||||
trackOffset %= WOZ_TRACK_BYTE_COUNT;
|
||||
|
||||
// printf("offs:%u\n", trackOffset);
|
||||
WOZread.latch = woz_trks[track].data[trackOffset];
|
||||
}
|
||||
@ -367,9 +616,11 @@ INLINE uint8_t ioRead( uint16_t addr ) {
|
||||
|
||||
|
||||
default:
|
||||
return RAM[addr];
|
||||
//printf("mmio read:%04X\n", addr);
|
||||
break;
|
||||
}
|
||||
|
||||
return RAM[addr];
|
||||
}
|
||||
|
||||
|
||||
@ -414,53 +665,23 @@ INLINE void ioWrite( uint16_t addr, uint8_t val ) {
|
||||
Naive implementation of RAM read from address
|
||||
**/
|
||||
|
||||
INLINE uint8_t memread_zp( uint8_t addr ) {
|
||||
return RAM[ addr ];
|
||||
}
|
||||
|
||||
/**
|
||||
Naive implementation of RAM read from address
|
||||
**/
|
||||
INLINE uint8_t memread8( uint16_t addr ) {
|
||||
// if ( addr == 0xD2AD ) {
|
||||
// dbgPrintf("OUT OF MEMORY!\n");
|
||||
// }
|
||||
|
||||
|
||||
return RAM[ addr ];
|
||||
return * ( RAM_PG_RD_TBL[addr >> 8] + (addr & 0xFF) );
|
||||
// return RAM[ addr ];
|
||||
}
|
||||
/**
|
||||
Naive implementation of RAM read from address
|
||||
**/
|
||||
INLINE uint16_t memread16( uint16_t addr ) {
|
||||
return * (uint16_t*) (& RAM[ addr ]);
|
||||
return * (uint16_t*) ( RAM_PG_RD_TBL[addr >> 8] + (addr & 0xFF) );
|
||||
// return * (uint16_t*) (& RAM[ addr ]);
|
||||
}
|
||||
|
||||
INLINE uint8_t memread( uint16_t addr ) {
|
||||
// switch ( ((address16_t)addr).page ) {
|
||||
// case 0xC0:
|
||||
// case 0xC1:
|
||||
// case 0xC2:
|
||||
// case 0xC3:
|
||||
// case 0xC4:
|
||||
// case 0xC5:
|
||||
// case 0xC6:
|
||||
// case 0xC7:
|
||||
// case 0xC8:
|
||||
// case 0xC9:
|
||||
// case 0xCA:
|
||||
// case 0xCB:
|
||||
// case 0xCC:
|
||||
// case 0xCD:
|
||||
// case 0xCE:
|
||||
// case 0xCF:
|
||||
// return ioRead(addr);
|
||||
//
|
||||
// defaut:
|
||||
// break;
|
||||
// }
|
||||
|
||||
if ( (addr >= 0xC000) && (addr < 0xC0FF) ) {
|
||||
if ( (addr >= 0xC000) && (addr <= 0xC0FF) ) {
|
||||
return ioRead(addr);
|
||||
}
|
||||
|
||||
@ -478,9 +699,9 @@ INLINE uint8_t memread( uint16_t addr ) {
|
||||
/**
|
||||
Naive implementation of RAM write to address
|
||||
**/
|
||||
static void memwrite_zp( uint8_t addr, uint8_t byte ) {
|
||||
RAM[ addr ] = byte;
|
||||
}
|
||||
//static void memwrite_zp( uint8_t addr, uint8_t byte ) {
|
||||
// RAM[ addr ] = byte;
|
||||
//}
|
||||
|
||||
|
||||
/**
|
||||
@ -534,7 +755,8 @@ INLINE uint8_t src_abs() {
|
||||
return memread( addr_abs() );
|
||||
}
|
||||
INLINE uint8_t * dest_abs() {
|
||||
return & RAM[ addr_abs() ];
|
||||
uint16_t addr = addr_abs();
|
||||
return ( RAM_PG_WR_TBL[addr >> 8] + (addr & 0xFF) );
|
||||
}
|
||||
|
||||
|
||||
@ -565,7 +787,8 @@ INLINE uint8_t src_abs_X() {
|
||||
return memread( addr_abs_X() );
|
||||
}
|
||||
INLINE uint8_t * dest_abs_X() {
|
||||
return & RAM[ addr_abs_X() ];
|
||||
uint16_t addr = addr_abs_X();
|
||||
return ( RAM_PG_WR_TBL[addr >> 8] + (addr & 0xFF) );
|
||||
}
|
||||
|
||||
|
||||
@ -582,7 +805,8 @@ INLINE uint8_t src_abs_Y() {
|
||||
return memread(addr_abs_Y());
|
||||
}
|
||||
INLINE uint8_t * dest_abs_Y() {
|
||||
return & RAM[ addr_abs_Y() ];
|
||||
uint16_t addr = addr_abs_Y();
|
||||
return ( RAM_PG_WR_TBL[addr >> 8] + (addr & 0xFF) );
|
||||
}
|
||||
|
||||
INLINE uint16_t imm() {
|
||||
@ -601,10 +825,11 @@ INLINE uint8_t addr_zp() {
|
||||
return fetch();
|
||||
}
|
||||
INLINE uint8_t src_zp() {
|
||||
return memread_zp(addr_zp());
|
||||
return memread8(addr_zp());
|
||||
}
|
||||
INLINE uint8_t * dest_zp() {
|
||||
return & RAM[ addr_zp() ];
|
||||
uint16_t addr = addr_zp();
|
||||
return ( RAM_PG_WR_TBL[addr >> 8] + (addr & 0xFF) );
|
||||
}
|
||||
|
||||
/**
|
||||
@ -632,7 +857,8 @@ INLINE uint8_t src_X_ind() {
|
||||
return memread( addr_X_ind() );
|
||||
}
|
||||
INLINE uint8_t * dest_X_ind() {
|
||||
return & RAM[ addr_X_ind() ];
|
||||
uint16_t addr = addr_X_ind();
|
||||
return ( RAM_PG_WR_TBL[addr >> 8] + (addr & 0xFF) );
|
||||
}
|
||||
|
||||
/**
|
||||
@ -652,12 +878,7 @@ INLINE uint8_t src_ind_Y() {
|
||||
}
|
||||
INLINE uint8_t * dest_ind_Y() {
|
||||
uint16_t addr = addr_ind_Y();
|
||||
// if ( (addr >= 0xC000) && (addr <= 0xC0FF) ) {
|
||||
// addr = 0xC111;
|
||||
// }
|
||||
// return & RAM[ addr_abs_Y() ];
|
||||
return & RAM[ addr ];
|
||||
// return & RAM[ addr_ind_Y() ];
|
||||
return ( RAM_PG_WR_TBL[addr >> 8] + (addr & 0xFF) );
|
||||
}
|
||||
|
||||
/**
|
||||
@ -670,10 +891,11 @@ INLINE uint8_t addr_zp_X() {
|
||||
return fetch() + m6502.X;
|
||||
}
|
||||
INLINE uint8_t src_zp_X() {
|
||||
return memread_zp(addr_zp_X());
|
||||
return memread8(addr_zp_X());
|
||||
}
|
||||
INLINE uint8_t * dest_zp_X() {
|
||||
return & RAM[ addr_zp_X() ];
|
||||
uint16_t addr = addr_zp_X();
|
||||
return ( RAM_PG_WR_TBL[addr >> 8] + (addr & 0xFF) );
|
||||
}
|
||||
|
||||
/**
|
||||
@ -686,10 +908,11 @@ INLINE uint8_t addr_zp_Y() {
|
||||
return fetch() + m6502.Y;
|
||||
}
|
||||
INLINE uint8_t src_zp_Y() {
|
||||
return memread_zp(addr_zp_Y());
|
||||
return memread8(addr_zp_Y());
|
||||
}
|
||||
INLINE uint8_t * dest_zp_Y() {
|
||||
return & RAM[ addr_zp_Y() ];
|
||||
uint16_t addr = addr_zp_Y();
|
||||
return ( RAM_PG_WR_TBL[addr >> 8] + (addr & 0xFF) );
|
||||
}
|
||||
|
||||
|
||||
|
||||
BIN
A2Mac/Resources/spk_dn.wav
Normal file
BIN
A2Mac/Resources/spk_dn.wav
Normal file
Binary file not shown.
BIN
A2Mac/Resources/spk_up.wav
Normal file
BIN
A2Mac/Resources/spk_up.wav
Normal file
Binary file not shown.
@ -8,6 +8,8 @@
|
||||
|
||||
|
||||
import Cocoa
|
||||
import AVFoundation
|
||||
|
||||
|
||||
let K : Double = 1000.0
|
||||
let M : Double = (K * K)
|
||||
@ -20,6 +22,24 @@ let GB : Double = (MB * KB)
|
||||
let TB : Double = (GB * KB)
|
||||
|
||||
|
||||
var spk_up: AVAudioPlayer?
|
||||
var spk_dn: AVAudioPlayer?
|
||||
|
||||
@_cdecl("ViewController_spk_up_play")
|
||||
func spk_up_play() {
|
||||
spk_up?.stop()
|
||||
spk_dn?.stop()
|
||||
spk_up?.play()
|
||||
}
|
||||
|
||||
@_cdecl("ViewController_spk_dn_play")
|
||||
func spk_dn_play() {
|
||||
spk_up?.stop()
|
||||
spk_dn?.stop()
|
||||
spk_dn?.play()
|
||||
}
|
||||
|
||||
|
||||
#if METAL_YES
|
||||
import Metal
|
||||
#endif
|
||||
@ -74,6 +94,8 @@ class ViewController: NSViewController {
|
||||
|
||||
var workItem : DispatchWorkItem? = nil;
|
||||
@IBAction func Power(_ sender: Any) {
|
||||
|
||||
|
||||
#if SPEEDTEST
|
||||
if ( workItem != nil ) {
|
||||
workItem!.cancel();
|
||||
@ -336,9 +358,32 @@ class ViewController: NSViewController {
|
||||
|
||||
let upd = RepeatingTimer(timeInterval: 1/Double(fps))
|
||||
|
||||
|
||||
override func viewDidLoad() {
|
||||
super.viewDidLoad()
|
||||
|
||||
|
||||
let spk_up_path = Bundle.main.path(forResource: "spk_up", ofType:"wav")!
|
||||
let spk_up_url = URL(fileURLWithPath: spk_up_path)
|
||||
do {
|
||||
spk_up = try AVAudioPlayer(contentsOf: spk_up_url)
|
||||
// spk_up?.play()
|
||||
} catch {
|
||||
// couldn't load file :(
|
||||
}
|
||||
|
||||
let spk_dn_path = Bundle.main.path(forResource: "spk_dn", ofType:"wav")!
|
||||
let spk_dn_url = URL(fileURLWithPath: spk_dn_path)
|
||||
do {
|
||||
spk_dn = try AVAudioPlayer(contentsOf: spk_dn_url)
|
||||
// spk_up?.play()
|
||||
} catch {
|
||||
// couldn't load file :(
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
//view.frame = CGRect(origin: CGPoint(), size: NSScreen.main!.visibleFrame.size)
|
||||
|
||||
// createHiRes()
|
||||
|
||||
@ -17,6 +17,7 @@
|
||||
#define G (M * K)
|
||||
#define T (G * K)
|
||||
|
||||
#define PG 256ULL
|
||||
#define KB 1024ULL
|
||||
#define MB (KB * KB)
|
||||
#define GB (MB * KB)
|
||||
|
||||
@ -11,7 +11,7 @@
|
||||
|
||||
#ifdef DISASSEMBLER
|
||||
|
||||
extern unsigned long long int clktime;
|
||||
//extern unsigned long long int clktime;
|
||||
unsigned long long discnt = 0;
|
||||
|
||||
#define disHexB( to, b ) \
|
||||
@ -75,7 +75,7 @@ INLINE void printDisassembly( FILE * f ) {
|
||||
|
||||
fprintf( f, "%llu\t%llu %s: %-11s%-4s%s\t0x%02X\t0x%02X\t0x%02X\t0x%02X\t0x%02X\t;\t%s\n", // Virtual ][ style
|
||||
++discnt,
|
||||
clktime,
|
||||
m6502.clktime,
|
||||
disassembly.addr,
|
||||
disassembly.opcode,
|
||||
disassembly.inst,
|
||||
@ -97,7 +97,7 @@ INLINE void printDisassembly( FILE * f ) {
|
||||
#define disPuts( to, from )
|
||||
#define disPrintf( to, fmt, args... )
|
||||
#define disNewInstruction()
|
||||
#define printDisassembly()
|
||||
#define printDisassembly( f )
|
||||
|
||||
#endif // DISASSEMBLER
|
||||
|
||||
|
||||
@ -93,56 +93,31 @@ INLINE void STR( uint8_t * dst, uint8_t src ) {
|
||||
dbgPrintf("STR [%04X], %02X ", (int)(dst - RAM), src );
|
||||
|
||||
uint16_t addr = dst - RAM;
|
||||
// if ( ( addr >= 0x400 ) && ( addr < 0x800 ) ) {
|
||||
// char c = charConv[src];
|
||||
//// if ( c == '?' ) {
|
||||
//// printf("? SYNTAX ERROR\n");
|
||||
//// }
|
||||
//
|
||||
// if (( src > ' ' ) && ( c < 0x7F ))
|
||||
// printf("*** PRINT: %04X: t:%02X '%c'\n", addr, src, isprint(c) ? c : ' ');
|
||||
// }
|
||||
// else
|
||||
if ( ( addr >= 0xC000 ) && ( addr < 0xD000 ) ) {
|
||||
// printf("mmio write:[%04X] = %02X\n", addr, src);
|
||||
}
|
||||
// Need to protect ROM!!!
|
||||
else if ( ( addr >= 0xE000 ) && ( addr < 0xF000 ) ) {
|
||||
|
||||
// I/O or ROM or RAM EXP
|
||||
if ( addr >= 0xC000 ) {
|
||||
// ROM or RAM EXP
|
||||
if ( addr >= 0xD000 ) {
|
||||
uint8_t * pgaddr;
|
||||
// DO NOT MAKE IT NICER! faster this way!
|
||||
if ( (pgaddr = RAM_PG_WR_TBL[ addr >> 8 ]) ) {
|
||||
dst = pgaddr + (addr & 0xFF);
|
||||
}
|
||||
else {
|
||||
// NULL page table, so no need to do anything
|
||||
return;
|
||||
}
|
||||
}
|
||||
// I/O
|
||||
else {
|
||||
// printf("mmio write:[%04X] = %02X\n", addr, src);
|
||||
// dst = Apple2_Dummy_Page;
|
||||
return;
|
||||
}
|
||||
}
|
||||
else {
|
||||
*dst = src;
|
||||
}
|
||||
|
||||
*dst = src;
|
||||
|
||||
|
||||
// else switch ( addr ) {
|
||||
// case 0x36:
|
||||
// case 0x37:
|
||||
// dbgPrintf("*** OUTROUT %04X: %02X\n", addr, src);
|
||||
// break;
|
||||
//
|
||||
// case 0x9B:
|
||||
// case 0x9C:
|
||||
// dbgPrintf("*** LOWTR %04X: %02X\n", addr, src);
|
||||
// break;
|
||||
//
|
||||
// case 0x6F: // FRETOP
|
||||
// case 0x70:
|
||||
// dbgPrintf("*** FRETOP %04X: %02X\n", addr, src);
|
||||
// break;
|
||||
//
|
||||
// case 0x73: // MEMSIZ
|
||||
// case 0x74:
|
||||
// dbgPrintf("*** MEMSIZ %04X: %02X\n", addr, src);
|
||||
// break;
|
||||
//
|
||||
// case 0x5E:
|
||||
// dbgPrintf("*** ??? %04X: %02X\n", addr, src);
|
||||
// break;
|
||||
//
|
||||
// default:
|
||||
// break;
|
||||
// }
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user