mirror of https://github.com/trudnai/Steve2.git
157 lines
4.4 KiB
C
157 lines
4.4 KiB
C
//
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// main.c
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// 6502
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//
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// Created by Tamas Rudnai on 7/14/19.
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// Copyright © 2019, 2020 Tamas Rudnai. All rights reserved.
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//
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// This file is part of Steve ][ -- The Apple ][ Emulator.
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//
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// Steve ][ is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// Steve ][ is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with Steve ][. If not, see <https://www.gnu.org/licenses/>.
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//
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#ifndef __6502_INSTR_SHIFT_ROTATE_H__
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#define __6502_INSTR_SHIFT_ROTATE_H__
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/**
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ASL Shift Left One Bit (Memory or Accumulator)
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C <- [76543210] <- 0 N Z C I D V
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+ + + - - -
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addressing assembler opc bytes cyles
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--------------------------------------------
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accumulator ASL A 0A 1 2
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zeropage ASL oper 06 2 5
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zeropage,X ASL oper,X 16 2 6
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absolute ASL oper 0E 3 6
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absolute,X ASL oper,X 1E 3 7
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**/
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INLINE void _ASL( uint16_t addr ) {
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m6502.C = WRLOMEM[addr] & 0x80;
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set_flags_NZ( WRLOMEM[addr] <<= 1 );
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}
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INLINE void ASL( uint16_t addr ) {
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dbgPrintf("ASL ");
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disPrintf(disassembly.inst, "ASL");
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_ASL(addr);
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}
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INLINE void ASLA() {
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dbgPrintf("ASL ");
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disPrintf(disassembly.inst, "ASL");
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m6502.C = m6502.A & 0x80;
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set_flags_NZ( m6502.A <<= 1 );
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}
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/**
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LSR Shift One Bit Right (Memory or Accumulator)
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0 -> [76543210] -> C N Z C I D V
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0 + + - - -
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addressing assembler opc bytes cyles
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--------------------------------------------
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accumulator LSR A 4A 1 2
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zeropage LSR oper 46 2 5
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zeropage,X LSR oper,X 56 2 6
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absolute LSR oper 4E 3 6
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absolute,X LSR oper,X 5E 3 7
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**/
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INLINE void LSR( uint16_t addr ) {
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dbgPrintf("LSR ");
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disPrintf(disassembly.inst, "LSR");
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m6502.C = WRLOMEM[addr] & 1;
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set_flags_NZ( WRLOMEM[addr] >>= 1 );
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}
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INLINE void LSRA() {
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dbgPrintf("LSR ");
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disPrintf(disassembly.inst, "LSR");
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m6502.C = m6502.A & 1;
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set_flags_NZ( m6502.A >>= 1 );
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}
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/**
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ROL Rotate One Bit Left (Memory or Accumulator)
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C <- [76543210] <- C N Z C I D V
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+ + + - - -
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addressing assembler opc bytes cyles
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--------------------------------------------
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accumulator ROL A 2A 1 2
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zeropage ROL oper 26 2 5
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zeropage,X ROL oper,X 36 2 6
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absolute ROL oper 2E 3 6
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absolute,X ROL oper,X 3E 3 7
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**/
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INLINE void _ROL( uint16_t addr ) {
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uint8_t C = m6502.C != 0;
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m6502.C = WRLOMEM[addr] & 0x80;
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WRLOMEM[addr] <<= 1;
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set_flags_NZ( WRLOMEM[addr] |= C );
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}
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INLINE void ROL( uint16_t addr ) {
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dbgPrintf("ROL ");
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disPrintf(disassembly.inst, "ROL");
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_ROL(addr);
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}
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INLINE void ROLA() {
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dbgPrintf("ROL ");
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disPrintf(disassembly.inst, "ROL");
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uint8_t C = m6502.C != 0;
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m6502.C = m6502.A & 0x80;
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m6502.A <<= 1;
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set_flags_NZ( m6502.A |= C );
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}
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/**
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ROR Rotate One Bit Right (Memory or Accumulator)
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C -> [76543210] -> C N Z C I D V
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+ + + - - -
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addressing assembler opc bytes cyles
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--------------------------------------------
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accumulator ROR A 6A 1 2
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zeropage ROR oper 66 2 5
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zeropage,X ROR oper,X 76 2 6
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absolute ROR oper 6E 3 6
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absolute,X ROR oper,X 7E 3 7
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**/
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INLINE void _ROR( uint16_t addr ) {
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uint8_t C = m6502.C != 0;
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m6502.C = WRLOMEM[addr] & 1;
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WRLOMEM[addr] >>= 1;
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set_flags_NZ( WRLOMEM[addr] |= C << 7 );
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}
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INLINE void ROR( uint16_t addr ) {
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dbgPrintf("ROR ");
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disPrintf(disassembly.inst, "ROR");
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_ROR(addr);
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}
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INLINE void RORA() {
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dbgPrintf("ROR ");
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disPrintf(disassembly.inst, "ROR");
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uint8_t C = m6502.C != 0;
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m6502.C = m6502.A & 1;
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m6502.A >>= 1;
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set_flags_NZ( m6502.A |= C << 7);
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}
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#endif // __6502_INSTR_SHIFT_ROTATE_H__
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