mirror of https://github.com/trudnai/Steve2.git
597 lines
12 KiB
C
597 lines
12 KiB
C
//
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// main.c
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// 6502
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//
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// Created by Tamas Rudnai on 7/14/19.
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// Copyright © 2019, 2020 Tamas Rudnai. All rights reserved.
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//
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// This file is part of Steve ][ -- The Apple ][ Emulator.
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//
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// Steve ][ is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// Steve ][ is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with Steve ][. If not, see <https://www.gnu.org/licenses/>.
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//
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#ifndef __APPLE2_MMIO_H__
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#define __APPLE2_MMIO_H__
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#include "common.h"
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#include "6502.h"
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enum mmio {
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io_KBD = 0xC000,
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io_KBDSTRB = 0xC010,
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};
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uint8_t RAM[ 64 * KB ] = {0};
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#define PAGESIZE 256
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#define PAGES 16
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//uint8_t ram_0[PAGESIZE];
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//uint8_t ram_1[PAGESIZE];
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//uint8_t ram_2[PAGESIZE];
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//uint8_t ram_3[PAGESIZE];
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//uint8_t ram_4[PAGESIZE];
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//uint8_t ram_5[PAGESIZE];
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//uint8_t ram_6[PAGESIZE];
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//uint8_t ram_7[PAGESIZE];
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//uint8_t ram_8[PAGESIZE];
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//uint8_t ram_9[PAGESIZE];
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//uint8_t ram_A[PAGESIZE];
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//uint8_t ram_B[PAGESIZE];
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//uint8_t aui_C[PAGESIZE];
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//uint8_t rom_D[PAGESIZE];
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//uint8_t rom_E[PAGESIZE];
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//uint8_t rom_F[PAGESIZE];
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//
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//uint8_t * ram[PAGES] = {
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// ram_0,
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// ram_1,
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// ram_2,
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// ram_3,
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// ram_4,
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// ram_5,
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// ram_6,
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// ram_7,
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// ram_8,
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// ram_9,
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// ram_A,
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// ram_B,
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// aui_C,
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// rom_D,
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// rom_E,
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// rom_F,
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//};
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//uint8_t ( * mmio_read [ 64 * KB ] )( uint16_t addr );
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typedef union address16_u {
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uint16_t addr;
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struct {
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uint8_t offs;
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uint8_t page;
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};
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} address16_t;
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INLINE uint8_t ioRead( uint16_t addr ) {
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// printf("mmio:%04X\n", addr);
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// C0xx
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switch ((uint8_t)addr) {
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case 0x00:
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return RAM[io_KBD];
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case 0x10:
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// TODO: This is very slow!
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dbgPrintf("io_KBDSTRB\n");
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return RAM[io_KBD] &= 0x7F;
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case 0x01:
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case 0x02:
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case 0x03:
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case 0x04:
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case 0x05:
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case 0x06:
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case 0x07:
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case 0x08:
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case 0x09:
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case 0x0A:
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case 0x0B:
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case 0x0C:
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case 0x0D:
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case 0x0E:
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case 0x0F:
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case 0x11:
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case 0x12:
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case 0x13:
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case 0x14:
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case 0x15:
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case 0x16:
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case 0x17:
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case 0x18:
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case 0x19:
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case 0x1A:
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case 0x1B:
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case 0x1C:
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case 0x1D:
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case 0x1E:
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case 0x1F:
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case 0x20:
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case 0x21:
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case 0x22:
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case 0x23:
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case 0x24:
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case 0x25:
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case 0x26:
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case 0x27:
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case 0x28:
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case 0x29:
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case 0x2A:
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case 0x2B:
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case 0x2C:
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case 0x2D:
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case 0x2E:
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case 0x2F:
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case 0x30:
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case 0x31:
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case 0x32:
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case 0x33:
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case 0x34:
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case 0x35:
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case 0x36:
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case 0x37:
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case 0x38:
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case 0x39:
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case 0x3A:
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case 0x3B:
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case 0x3C:
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case 0x3D:
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case 0x3E:
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case 0x3F:
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case 0x40:
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case 0x41:
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case 0x42:
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case 0x43:
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case 0x44:
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case 0x45:
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case 0x46:
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case 0x47:
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case 0x48:
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case 0x49:
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case 0x4A:
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case 0x4B:
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case 0x4C:
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case 0x4D:
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case 0x4E:
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case 0x4F:
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case 0x50:
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case 0x51:
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case 0x52:
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case 0x53:
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case 0x54:
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case 0x55:
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case 0x56:
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case 0x57:
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case 0x58:
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case 0x59:
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case 0x5A:
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case 0x5B:
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case 0x5C:
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case 0x5D:
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case 0x5E:
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case 0x5F:
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case 0x60:
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case 0x61:
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case 0x62:
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case 0x63:
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case 0x64:
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case 0x65:
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case 0x66:
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case 0x67:
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case 0x68:
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case 0x69:
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case 0x6A:
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case 0x6B:
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case 0x6C:
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case 0x6D:
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case 0x6E:
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case 0x6F:
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case 0x70:
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case 0x71:
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case 0x72:
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case 0x73:
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case 0x74:
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case 0x75:
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case 0x76:
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case 0x77:
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case 0x78:
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case 0x79:
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case 0x7A:
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case 0x7B:
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case 0x7C:
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case 0x7D:
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case 0x7E:
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case 0x7F:
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case 0x80:
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case 0x81:
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case 0x82:
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case 0x83:
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case 0x84:
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case 0x85:
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case 0x86:
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case 0x87:
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case 0x88:
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case 0x89:
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case 0x8A:
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case 0x8B:
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case 0x8C:
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case 0x8D:
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case 0x8E:
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case 0x8F:
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case 0x90:
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case 0x91:
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case 0x92:
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case 0x93:
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case 0x94:
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case 0x95:
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case 0x96:
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case 0x97:
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case 0x98:
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case 0x99:
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case 0x9A:
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case 0x9B:
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case 0x9C:
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case 0x9D:
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case 0x9E:
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case 0x9F:
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case 0xA0:
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case 0xA1:
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case 0xA2:
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case 0xA3:
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case 0xA4:
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case 0xA5:
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case 0xA6:
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case 0xA7:
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case 0xA8:
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case 0xA9:
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case 0xAA:
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case 0xAB:
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case 0xAC:
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case 0xAD:
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case 0xAE:
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case 0xAF:
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case 0xB0:
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case 0xB1:
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case 0xB2:
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case 0xB3:
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case 0xB4:
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case 0xB5:
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case 0xB6:
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case 0xB7:
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case 0xB8:
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case 0xB9:
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case 0xBA:
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case 0xBB:
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case 0xBC:
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case 0xBD:
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case 0xBE:
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case 0xBF:
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case 0xC0:
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case 0xC1:
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case 0xC2:
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case 0xC3:
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case 0xC4:
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case 0xC5:
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case 0xC6:
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case 0xC7:
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case 0xC8:
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case 0xC9:
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case 0xCA:
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case 0xCB:
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case 0xCC:
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case 0xCD:
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case 0xCE:
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case 0xCF:
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case 0xD0:
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case 0xD1:
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case 0xD2:
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case 0xD3:
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case 0xD4:
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case 0xD5:
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case 0xD6:
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case 0xD7:
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case 0xD8:
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case 0xD9:
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case 0xDA:
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case 0xDB:
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case 0xDC:
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case 0xDD:
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case 0xDE:
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case 0xDF:
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case 0xE0:
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case 0xE1:
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case 0xE2:
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case 0xE3:
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case 0xE4:
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case 0xE5:
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case 0xE6:
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case 0xE7:
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case 0xE8:
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case 0xE9:
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case 0xEA:
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case 0xEB:
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case 0xEC:
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case 0xED:
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case 0xEE:
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case 0xEF:
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case 0xF0:
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case 0xF1:
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case 0xF2:
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case 0xF3:
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case 0xF4:
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case 0xF5:
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case 0xF6:
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case 0xF7:
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case 0xF8:
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case 0xF9:
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case 0xFA:
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case 0xFB:
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case 0xFC:
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case 0xFD:
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case 0xFE:
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case 0xFF:
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default:
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break;
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}
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return 0;
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}
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INLINE void ioWrite( uint16_t addr ) {
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// printf("mmio:%04X\n", addr);
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switch (addr) {
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case io_KBD:
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return;
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default:
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break;
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}
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return;
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}
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/**
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Naive implementation of RAM read from address
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**/
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INLINE uint8_t memread_zp( uint8_t addr ) {
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return RAM[ addr ];
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}
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INLINE uint8_t memread( uint16_t addr ) {
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// switch ( ((address16_t)addr).page ) {
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// case 0xC0:
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// case 0xC1:
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// case 0xC2:
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// case 0xC3:
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// case 0xC4:
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// case 0xC5:
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// case 0xC6:
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// case 0xC7:
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// case 0xC8:
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// case 0xC9:
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// case 0xCA:
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// case 0xCB:
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// case 0xCC:
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// case 0xCD:
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// case 0xCE:
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// case 0xCF:
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// return ioRead(addr);
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//
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// defaut:
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// break;
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// }
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if ( (addr >= 0xC000) && (addr < 0xD000) ) {
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ioRead(addr);
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}
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return RAM[ addr ];
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}
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/**
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Naive implementation of RAM read from address
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**/
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INLINE uint16_t memread16( uint16_t addr ) {
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// if ( ( addr >= 0xC000 ) && ( addr < 0xD000 ) ) {
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// return mmioRead(addr);
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// }
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// dbgPrintf("%04X ", * (uint16_t*) (& RAM[ addr ]));
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return * (uint16_t*) (& RAM[ addr ]);
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}
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/**
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Naive implementation of RAM read from address
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**/
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//INLINE uint16_t memioread16( uint16_t addr ) {
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// return (uint16_t)mmio_read[ addr ](addr);
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//}
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/**
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Naive implementation of RAM write to address
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**/
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static void memwrite_zp( uint8_t addr, uint8_t byte ) {
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RAM[ addr ] = byte;
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}
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/**
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Naive implementation of RAM write to address
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**/
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static void memwrite( uint16_t addr, uint8_t byte ) {
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// if ( addr >= 0xD000 ) {
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// // ROM
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// return;
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// }
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// if ( addr >= 0xC000 ) {
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// return mmioWrite(addr);
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// }
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//
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RAM[ addr ] = byte;
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}
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/**
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Fetching 1 byte from memory address pc (program counter)
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increase pc by one
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**/
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INLINE uint8_t fetch() {
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dbgPrintf("%02X ", RAM[m6502.pc]);
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return memread( m6502.pc++ );
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}
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/**
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Fetching 2 bytes as a 16 bit number from memory address pc (program counter)
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increase pc by one
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**/
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INLINE uint16_t fetch16() {
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dbgPrintf("%04X ", memread16(m6502.pc));
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uint16_t word = memread16( m6502.pc );
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m6502.pc += 2;
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return word;
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}
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/**
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get a 16 bit address from the zp:zp+1
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**/
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INLINE uint16_t addr_zp_ind( uint8_t addr ) {
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return memread16(addr);
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}
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/**
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X,ind .... X-indexed, indirect OPC ($LL,X)
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operand is zeropage address;
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effective address is word in (LL + X, LL + X + 1), inc. without carry: C.w($00LL + X)
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**/
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INLINE uint16_t addr_X_ind() {
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return addr_zp_ind( fetch() + m6502.X );
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}
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INLINE uint8_t src_X_ind() {
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return memread( addr_X_ind() );
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}
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INLINE uint8_t * dest_X_ind() {
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return & RAM[ addr_X_ind() ];
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}
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/**
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ind,Y .... indirect, Y-indexed OPC ($LL),Y
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operand is zeropage address;
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effective address is word in (LL, LL + 1) incremented by Y with carry: C.w($00LL) + Y
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**/
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INLINE uint16_t addr_ind_Y() {
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uint8_t a = fetch();
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// dbgPrintf("addr_ind_Y: %04X + %02X = %04X ", addr_zpg_ind( a ), m6502.Y, addr_zpg_ind( a ) + m6502.Y);
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return addr_zp_ind( a ) + m6502.Y;
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}
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/**
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abs,X .... absolute, X-indexed OPC $LLHH,X
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operand is address; effective address is address incremented by X with carry **
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**/
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INLINE uint16_t addr_abs_X() {
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return fetch16() + m6502.X;
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}
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INLINE uint8_t src_abs_X() {
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return memread( addr_abs_X() );
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}
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INLINE uint8_t * dest_abs_X() {
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return & RAM[ addr_abs_X() ];
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}
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INLINE uint16_t abs_addr() {
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return fetch16();
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}
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/**
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abs,Y .... absolute, Y-indexed OPC $LLHH,Y
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operand is address; effective address is address incremented by Y with carry **
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**/
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INLINE uint16_t addr_abs_Y() {
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return fetch16() + m6502.Y;
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}
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INLINE uint8_t src_abs_Y() {
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return memread(addr_abs_Y());
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}
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INLINE uint8_t * dest_abs_Y() {
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return & RAM[ addr_abs_Y() ];
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}
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/**
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zpg .... zeropage OPC $LL
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operand is zeropage address (hi-byte is zero, address = $00LL)
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**/
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INLINE uint16_t addr_zp() {
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return fetch();
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}
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INLINE uint8_t src_zp() {
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return memread_zp(addr_zp());
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}
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INLINE uint8_t * dest_zp() {
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return & RAM[ addr_zp() ];
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}
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/**
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zpg,X .... zeropage, X-indexed OPC $LL,X
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operand is zeropage address;
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effective address is address incremented by X without carry **
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**/
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INLINE uint16_t addr_zp_X() {
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return addr_zp() + m6502.X;
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}
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/**
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zpg,Y .... zeropage, Y-indexed OPC $LL,Y
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operand is zeropage address;
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effective address is address incremented by Y without carry **
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**/
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INLINE uint16_t addr_zp_Y() {
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return addr_zp() + m6502.Y;
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}
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#endif // __APPLE2_MMIO_H__
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