334 lines
8.8 KiB
Go
334 lines
8.8 KiB
Go
package mmu
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import (
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"fmt"
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"io/ioutil"
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"github.com/freewilll/apple2-go/system"
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)
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// RomPath is a hardcoded path to an Apple //e ROM file that's loaded at startup
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const RomPath = "apple2e.rom"
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// StackPage is the location of the 6504 stack
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const StackPage = 1
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// PhysicalMemory contains all the unmapped memory, ROM and RAM
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var PhysicalMemory struct {
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MainMemory [0x10000]uint8 // Main RAM
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UpperROM [0x3000]uint8 // $c000-$ffff ROM area
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RomC1 [0x1000]uint8 // First half of IO ROM
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RomC2 [0x1000]uint8 // Second half of IO ROM
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}
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// ReadPageTable is the page table for reads
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var ReadPageTable [0x100][]uint8
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// WritePageTable is the page table for writes
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var WritePageTable [0x100][]uint8
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// Memory mapping states
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var (
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D000Bank int // one maps to $c000, two maps to $d000
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UsingExternalSlotRom bool // Which IO ROM is being used
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UpperReadMappedToROM bool // Do reads go to the RAM or ROM
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UpperRAMReadOnly bool // Is the upper RAM read only
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FakeAuxMemoryRead bool // Aux memory isn't implemented
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FakeAuxMemoryWrite bool // Aux memory isn't implemented
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FakeAltZP bool // Aux memory isn't implemented
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FakePage2 bool // Aux memory isn't implemented
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Col80 bool // 80 Column card is on (not implemented)
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Store80 bool // 80 Column card is on (not implemented)
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Page2 bool // Main memory Page2 is selected
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)
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// ApplyMemoryConfiguration creates the page tables for current RAM, ROM and IO configuration
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func ApplyMemoryConfiguration() {
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// Map main RAM for read/write
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for i := 0x0; i < 0xc0; i++ {
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ReadPageTable[i] = PhysicalMemory.MainMemory[i*0x100 : i*0x100+0x100]
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WritePageTable[i] = PhysicalMemory.MainMemory[i*0x100 : i*0x100+0x100]
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}
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// Map $c000
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var ioRom *[0x1000]uint8
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if UsingExternalSlotRom {
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ioRom = &PhysicalMemory.RomC2
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} else {
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ioRom = &PhysicalMemory.RomC1
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}
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for i := 0x1; i < 0x10; i++ {
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ReadPageTable[0xc0+i] = (*ioRom)[i*0x100 : i*0x100+0x100]
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WritePageTable[0xc0+i] = nil
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}
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// Map $d000
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for i := 0xd0; i < 0xe0; i++ {
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base := i*0x100 + D000Bank*0x1000 - 0x2000
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if !UpperReadMappedToROM {
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ReadPageTable[i] = PhysicalMemory.MainMemory[base : base+0x100]
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}
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if UpperRAMReadOnly {
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WritePageTable[i] = nil
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} else {
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WritePageTable[i] = PhysicalMemory.MainMemory[base : base+0x100]
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}
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}
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// Map 0xe00 to 0xffff
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for i := 0xe0; i < 0x100; i++ {
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base := i * 0x100
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if !UpperReadMappedToROM {
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ReadPageTable[i] = PhysicalMemory.MainMemory[base : base+0x100]
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}
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if UpperRAMReadOnly {
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WritePageTable[i] = nil
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} else {
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WritePageTable[i] = PhysicalMemory.MainMemory[base : base+0x100]
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}
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}
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if UpperReadMappedToROM {
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for i := 0x00; i < 0x30; i++ {
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ReadPageTable[i+0xd0] = PhysicalMemory.UpperROM[i*0x100 : i*0x100+0x100]
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}
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}
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}
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// MapFirstHalfOfIO maps 0xc100-0xcfff for reading from RomC1
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func MapFirstHalfOfIO() {
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UsingExternalSlotRom = false
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ApplyMemoryConfiguration()
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}
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// MapSecondHalfOfIO map 0xc100-0xcfff for reading from RomC2
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func MapSecondHalfOfIO() {
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UsingExternalSlotRom = true
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ApplyMemoryConfiguration()
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}
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// emptySlot zeroes all RAM for a slot, effectively disabling the slot
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func emptySlot(slot int) {
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for i := slot * 0x100; i < (slot+1)*0x100; i++ {
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PhysicalMemory.RomC1[i] = 0
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PhysicalMemory.RomC2[i] = 0
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}
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}
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func loadApple2eROM() {
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bytes, err := ioutil.ReadFile(RomPath)
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if err != nil {
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panic(fmt.Sprintf("Unable to read ROM: %s", err))
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}
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// Copy both I/O areas over c000-cfff, including unused c000-c0ff
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for i := 0x0000; i < 0x1000; i++ {
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PhysicalMemory.RomC1[i] = bytes[i]
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PhysicalMemory.RomC2[i] = bytes[i+0x4000]
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}
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// Copy ROM over for 0xd000-0xffff area
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for i := 0x0; i < 0x3000; i++ {
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PhysicalMemory.UpperROM[i] = bytes[i+0x1000]
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}
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}
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// InitApple2eROM loads the ROM and inits the ROM page tables
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func InitApple2eROM() {
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loadApple2eROM()
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MapFirstHalfOfIO() // Map 0xc100-0xcfff for reading
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InitROM() // Map 0xd000-0xffff for reading
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}
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// InitROM sets the upper memory area for reading from ROM
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func InitROM() {
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UpperReadMappedToROM = true
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ApplyMemoryConfiguration()
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}
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// SetUpperReadMappedToROM sets the upper area so that reads are done from the ROM if true or RAM if false
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func SetUpperReadMappedToROM(value bool) {
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UpperReadMappedToROM = value
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ApplyMemoryConfiguration()
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}
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// SetUpperRAMReadOnly sets the upper RAM area to read only
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func SetUpperRAMReadOnly(value bool) {
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UpperRAMReadOnly = value
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ApplyMemoryConfiguration()
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}
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// SetD000Bank sets the $d000 bank to map to $c000 or $d000 in the physical memory
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func SetD000Bank(value int) {
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D000Bank = value
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ApplyMemoryConfiguration()
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}
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// SetFakeAuxMemoryRead sets an internal state to fake aux memory reads. Aux memory hasn't been implemented. If aux memory is selected, and a read
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// is attempted, then nonsense must be returned.
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func SetFakeAuxMemoryRead(value bool) {
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FakeAuxMemoryRead = value
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ApplyMemoryConfiguration()
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}
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// SetFakeAuxMemoryWrite sets an internal state to fake aux memory writes. Aux memory hasn't been implemented. If aux memory is selected, and a write
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// is attempted, then it must be ignored.
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func SetFakeAuxMemoryWrite(value bool) {
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FakeAuxMemoryWrite = value
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ApplyMemoryConfiguration()
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}
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// SetFakeAltZP sets an internal state to fake a missing alternate zero page. Alternate zero page isn't implemented
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func SetFakeAltZP(value bool) {
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FakeAltZP = value
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ApplyMemoryConfiguration()
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}
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// SetCol80 sets an internal state to fake a missing 80 column card
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func SetCol80(value bool) {
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Col80 = value
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// No changes are needed when this is toggled
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}
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// SetPage2 sets page1/page2 in text, lores or hires. This only works if the
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// 80 column card is disabled since the 80 columns card has not yet nbeen
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// implemented.
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func SetPage2(value bool) {
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// If the 80 column card is enabled, then this toggles aux memory
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// Otherwise, page1/page2 is toggled in the main memory
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if Col80 {
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FakePage2 = value
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ApplyMemoryConfiguration()
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} else {
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Page2 = value
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}
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}
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// SetStore80 sets an internal state to fake a missing 80 column card
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func SetStore80(value bool) {
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Store80 = value
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FakePage2 = value
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ApplyMemoryConfiguration()
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}
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// InitRAM sets all default RAM memory settings and resets the page tables
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func InitRAM() {
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UpperRAMReadOnly = false
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D000Bank = 2
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FakeAuxMemoryRead = false // Aux memory isn't implemented
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FakeAuxMemoryWrite = false // Aux memory isn't implemented
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FakeAltZP = false // Aux memory isn't implemented
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FakePage2 = false // Aux memory isn't implemented
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Col80 = false // Aux memory isn't implemented
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Page2 = false
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ApplyMemoryConfiguration()
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}
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// WipeRAM wipes all the physical RAM
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func WipeRAM() {
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for i := 0; i < 0x10000; i++ {
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PhysicalMemory.MainMemory[i] = 0
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}
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}
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// SetMemoryMode is used to set UpperRAMReadOnly, UpperReadMappedToROM and D000Bank number
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func SetMemoryMode(mode uint8) {
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// mode corresponds to a read/write to $c080 with
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// $c080 mode=$00
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// $c08f mode=$0f
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if (mode & 1) == 0 {
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UpperRAMReadOnly = true
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} else {
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UpperRAMReadOnly = false
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}
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if (((mode & 2) >> 1) ^ (mode & 1)) == 0 {
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UpperReadMappedToROM = false
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} else {
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UpperReadMappedToROM = true
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}
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if (mode & 8) == 0 {
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D000Bank = 2
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} else {
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D000Bank = 1
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}
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ApplyMemoryConfiguration()
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}
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// ReadMemory reads the ROM or RAM page table
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func ReadMemory(address uint16) uint8 {
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if (address >= 0xc000) && (address < 0xc100) {
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return ReadIO(address)
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}
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if FakePage2 && (address >= 0x400 && address < 0x800) {
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// Return nothingness
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return uint8(0x00)
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}
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if FakeAuxMemoryRead {
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if address >= 0x200 {
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// Return nothingness
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return uint8(0x00)
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}
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if FakeAltZP {
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return uint8(0x00)
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}
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}
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// Implicit else, we're reading the main non-IO RAM
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return ReadPageTable[address>>8][address&0xff]
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}
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// WriteMemory writes to the ROM or RAM page table
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func WriteMemory(address uint16, value uint8) {
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if (address >= 0xc000) && (address < 0xc100) {
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WriteIO(address, value)
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return
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}
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// Magic routine to trigger an interrupt, used in the CPU interrupt tests
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if system.RunningInterruptTests && address == 0xbffc {
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oldValue := ReadMemory(address)
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system.WriteInterruptTestOpenCollector(address, oldValue, value)
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WritePageTable[uint8(address>>8)][uint8(address&0xff)] = value
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return
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}
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if FakePage2 && (address >= 0x400 && address < 0x800) {
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// Do nothing
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return
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}
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if FakeAuxMemoryWrite {
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// If there is no aux memory, then the write is ignored.
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return
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}
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memory := WritePageTable[address>>8]
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// If memory is nil, then it's read only. The write is ignored.
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if memory != nil {
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memory[uint8(address&0xff)] = value
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}
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// If doing CPU functional tests, 0x200 has the test number in it. A write to
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// it means a test passed or the tests are complete.
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if system.RunningFunctionalTests && address == 0x200 {
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testNumber := ReadMemory(0x200)
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if testNumber == 0xf0 {
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fmt.Println("Opcode testing completed")
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} else {
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fmt.Printf("Test %d OK\n", ReadMemory(0x200))
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}
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}
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}
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