2014-05-10 18:25:35 +00:00
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/*
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2015-10-22 05:13:26 +00:00
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* Apple // emulator for *ix
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2014-05-10 18:25:35 +00:00
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*
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* This software package is subject to the GNU General Public License
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2015-10-22 05:13:26 +00:00
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* version 3 or later (your choice) as published by the Free Software
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2014-05-10 18:25:35 +00:00
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* Foundation.
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*
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2015-10-22 05:13:26 +00:00
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* Copyright 2013-2015 Aaron Culliney
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2014-05-10 18:25:35 +00:00
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*
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*/
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#include "common.h"
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2015-09-11 07:00:04 +00:00
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extern const uint8_t apple_iie_rom[32768]; // rom.c
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uint8_t apple_ii_64k[2][65536] = { { 0 } };
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uint8_t language_card[2][8192] = { { 0 } };
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uint8_t language_banks[2][8192] = { { 0 } };
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uint32_t softswitches = 0x0;
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const uint8_t *base_vmem = apple_ii_64k[0];
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uint8_t *base_ramrd = NULL;
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uint8_t *base_ramwrt = NULL;
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uint8_t *base_textrd = NULL;
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uint8_t *base_textwrt = NULL;
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uint8_t *base_hgrrd = NULL;
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uint8_t *base_hgrwrt = NULL;
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uint8_t *base_stackzp = NULL;
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uint8_t *base_d000_rd = NULL;
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uint8_t *base_e000_rd = NULL;
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uint8_t *base_d000_wrt = NULL;
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uint8_t *base_e000_wrt = NULL;
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uint8_t *base_c3rom = NULL;
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uint8_t *base_c4rom = NULL;
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uint8_t *base_c5rom = NULL;
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uint8_t *base_cxrom = NULL;
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2015-01-31 21:57:10 +00:00
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// joystick timer values
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int gc_cycles_timer_0 = 0;
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int gc_cycles_timer_1 = 0;
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2014-11-23 22:03:18 +00:00
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#if VM_TRACING
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FILE *test_vm_fp = NULL;
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2014-11-23 22:28:00 +00:00
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typedef struct vm_trace_range_t {
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uint16_t lo;
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uint16_t hi;
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} vm_trace_range_t;
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2014-11-23 22:03:18 +00:00
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#endif
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2015-09-11 07:00:04 +00:00
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// ----------------------------------------------------------------------------
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GLUE_BANK_READ(iie_read_ram_default,base_ramrd);
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GLUE_BANK_WRITE(iie_write_ram_default,base_ramwrt);
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GLUE_BANK_READ(read_ram_bank,base_d000_rd);
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GLUE_BANK_MAYBEWRITE(write_ram_bank,base_d000_wrt);
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GLUE_BANK_READ(read_ram_lc,base_e000_rd);
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GLUE_BANK_MAYBEWRITE(write_ram_lc,base_e000_wrt);
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GLUE_BANK_READ(iie_read_ram_text_page0,base_textrd);
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GLUE_BANK_WRITE(iie_write_screen_hole_text_page0,base_textwrt);
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GLUE_BANK_READ(iie_read_ram_hires_page0,base_hgrrd);
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GLUE_BANK_WRITE(iie_write_screen_hole_hires_page0,base_hgrwrt);
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GLUE_BANK_READ(iie_read_ram_zpage_and_stack,base_stackzp);
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GLUE_BANK_WRITE(iie_write_ram_zpage_and_stack,base_stackzp);
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GLUE_BANK_READ(iie_read_slot3,base_c3rom);
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GLUE_BANK_MAYBEREAD(iie_read_slot4,base_c4rom);
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GLUE_BANK_MAYBEREAD(iie_read_slot5,base_c5rom);
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GLUE_BANK_READ(iie_read_slotx,base_cxrom);
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GLUE_EXTERN_C_READ(speaker_toggle);
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2014-05-10 18:25:35 +00:00
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GLUE_C_READ(ram_nop)
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{
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2015-01-31 21:57:10 +00:00
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return (cpu65_rw&MEM_WRITE_FLAG) ? 0x0 : floating_bus();
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2014-05-10 18:25:35 +00:00
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}
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GLUE_C_READ(read_unmapped_softswitch)
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{
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2015-01-11 00:13:36 +00:00
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return c_ram_nop(ea);
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2014-05-10 18:25:35 +00:00
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}
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GLUE_C_WRITE(write_unmapped_softswitch)
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{
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// ...
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}
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2015-02-01 23:25:55 +00:00
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GLUE_C_READ(read_keyboard)
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{
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2015-08-16 05:02:51 +00:00
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uint8_t b = apple_ii_64k[0][0xC000];
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#if INTERFACE_TOUCH
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// touch interface is expected to rate limit this callback by unregistering/NULLifying
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void (*readCallback)(void) = keydriver_keyboardReadCallback;
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if (readCallback) {
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readCallback();
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}
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#endif
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return b;
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2015-02-01 23:25:55 +00:00
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}
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2014-05-10 18:25:35 +00:00
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GLUE_C_READ(read_keyboard_strobe)
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{
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apple_ii_64k[0][0xC000] &= 0x7F;
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apple_ii_64k[1][0xC000] &= 0x7F;
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return apple_ii_64k[0][0xC000];
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}
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2014-05-10 18:56:54 +00:00
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// ----------------------------------------------------------------------------
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2014-05-10 20:08:44 +00:00
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// graphics softswitches
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2014-05-10 18:56:54 +00:00
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GLUE_C_READ(iie_page2_off)
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{
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if (!(softswitches & SS_PAGE2)) {
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2015-01-31 21:57:10 +00:00
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return floating_bus();
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2014-05-10 18:56:54 +00:00
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}
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softswitches &= ~(SS_PAGE2|SS_SCREEN);
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if (softswitches & SS_80STORE) {
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softswitches &= ~(SS_TEXTRD|SS_TEXTWRT);
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base_textrd = apple_ii_64k[0];
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base_textwrt = apple_ii_64k[0];
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if (softswitches & SS_HIRES) {
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softswitches &= ~(SS_HGRRD|SS_HGRWRT);
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base_hgrrd = apple_ii_64k[0];
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base_hgrwrt = apple_ii_64k[0];
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}
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}
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2016-01-21 05:56:25 +00:00
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video_setDirty(A2_DIRTY_FLAG);
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2014-05-10 18:56:54 +00:00
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2015-01-31 21:57:10 +00:00
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return floating_bus();
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2014-05-10 18:56:54 +00:00
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}
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GLUE_C_READ(iie_page2_on)
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{
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if (softswitches & SS_PAGE2) {
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2015-01-31 21:57:10 +00:00
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return floating_bus();
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2014-05-10 18:56:54 +00:00
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}
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softswitches |= SS_PAGE2;
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if (softswitches & SS_80STORE) {
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softswitches |= (SS_TEXTRD|SS_TEXTWRT);
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base_textrd = apple_ii_64k[1];
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base_textwrt = apple_ii_64k[1];
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if (softswitches & SS_HIRES) {
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softswitches |= (SS_HGRRD|SS_HGRWRT);
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base_hgrrd = apple_ii_64k[1];
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base_hgrwrt = apple_ii_64k[1];
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}
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} else {
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softswitches |= SS_SCREEN;
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}
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2016-01-22 07:09:57 +00:00
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video_setDirty(A2_DIRTY_FLAG);
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2015-01-31 21:57:10 +00:00
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return floating_bus();
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2014-05-10 18:56:54 +00:00
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}
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2014-05-11 05:14:46 +00:00
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GLUE_C_READ(iie_check_page2)
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{
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return (softswitches & SS_PAGE2) ? 0x80 : 0x00;
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}
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2014-05-10 19:26:06 +00:00
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GLUE_C_READ(read_switch_graphics)
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{
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if (softswitches & SS_TEXT) {
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softswitches &= ~SS_TEXT;
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2016-01-22 07:09:57 +00:00
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video_setDirty(A2_DIRTY_FLAG);
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2014-05-10 19:26:06 +00:00
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}
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2015-01-31 21:57:10 +00:00
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return floating_bus();
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2014-05-10 19:26:06 +00:00
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}
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GLUE_C_READ(read_switch_text)
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{
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if (!(softswitches & SS_TEXT)) {
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softswitches |= SS_TEXT;
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2016-01-22 07:09:57 +00:00
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video_setDirty(A2_DIRTY_FLAG);
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2014-05-10 19:26:06 +00:00
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}
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2015-01-31 21:57:10 +00:00
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return floating_bus();
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2014-05-10 19:26:06 +00:00
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}
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2014-05-11 05:14:46 +00:00
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GLUE_C_READ(iie_check_text)
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{
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return (softswitches & SS_TEXT) ? 0x80 : 0x00;
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}
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2014-05-10 19:26:06 +00:00
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GLUE_C_READ(read_switch_no_mixed)
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{
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if (softswitches & SS_MIXED) {
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softswitches &= ~SS_MIXED;
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2016-01-22 07:09:57 +00:00
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video_setDirty(A2_DIRTY_FLAG);
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2014-05-10 19:26:06 +00:00
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}
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2015-01-31 21:57:10 +00:00
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return floating_bus();
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2014-05-10 19:26:06 +00:00
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}
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GLUE_C_READ(read_switch_mixed)
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{
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if (!(softswitches & SS_MIXED)) {
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softswitches |= SS_MIXED;
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2016-01-22 07:09:57 +00:00
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video_setDirty(A2_DIRTY_FLAG);
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2014-05-10 19:26:06 +00:00
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}
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2015-01-31 21:57:10 +00:00
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return floating_bus();
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2014-05-10 19:26:06 +00:00
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}
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2014-05-11 05:14:46 +00:00
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GLUE_C_READ(iie_check_mixed)
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{
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return (softswitches & SS_MIXED) ? 0x80 : 0x00;
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}
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2015-01-11 00:13:36 +00:00
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GLUE_C_READ(iie_annunciator)
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2014-11-19 06:31:38 +00:00
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{
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2015-01-11 00:13:36 +00:00
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if ((ea >= 0xC058) && (ea <= 0xC05B)) {
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// TODO: alternate joystick management?
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}
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2015-01-31 21:57:10 +00:00
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return (cpu65_rw&MEM_WRITE_FLAG) ? 0x0 : floating_bus();
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2014-11-19 06:31:38 +00:00
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}
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2014-05-10 19:36:59 +00:00
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GLUE_C_READ(iie_hires_off)
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{
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if (!(softswitches & SS_HIRES)) {
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2015-01-31 21:57:10 +00:00
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return floating_bus();
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2014-05-10 19:36:59 +00:00
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}
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softswitches &= ~(SS_HIRES|SS_HGRRD|SS_HGRWRT);
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base_hgrrd = apple_ii_64k[0];
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base_hgrwrt = apple_ii_64k[0];
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if (softswitches & SS_RAMRD) {
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base_hgrrd = apple_ii_64k[1];
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softswitches |= SS_HGRRD;
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}
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if (softswitches & SS_RAMWRT) {
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base_hgrwrt = apple_ii_64k[1];
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softswitches |= SS_HGRWRT;
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}
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2016-01-22 07:09:57 +00:00
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video_setDirty(A2_DIRTY_FLAG);
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2015-01-31 21:57:10 +00:00
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return floating_bus();
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2014-05-10 19:36:59 +00:00
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}
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GLUE_C_READ(iie_hires_on)
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{
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if (softswitches & SS_HIRES) {
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2015-01-31 21:57:10 +00:00
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return floating_bus();
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2014-05-10 19:36:59 +00:00
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}
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softswitches |= SS_HIRES;
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if (softswitches & SS_80STORE) {
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if (softswitches & SS_PAGE2) {
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softswitches |= (SS_HGRRD|SS_HGRWRT);
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base_hgrrd = apple_ii_64k[1];
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base_hgrwrt = apple_ii_64k[1];
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2014-11-26 06:01:46 +00:00
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} else {
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softswitches &= ~(SS_HGRRD|SS_HGRWRT);
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base_hgrrd = apple_ii_64k[0];
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base_hgrwrt = apple_ii_64k[0];
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2014-05-10 19:36:59 +00:00
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}
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}
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2016-01-22 07:09:57 +00:00
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video_setDirty(A2_DIRTY_FLAG);
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2015-01-31 21:57:10 +00:00
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return floating_bus();
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2014-05-10 19:36:59 +00:00
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}
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2014-05-11 05:14:46 +00:00
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GLUE_C_READ(iie_check_hires)
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{
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return (softswitches & SS_HIRES) ? 0x80 : 0x00;
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}
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2014-05-10 20:08:44 +00:00
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// ----------------------------------------------------------------------------
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// GC softswitches : Game Controller (joystick/paddles)
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#define JOY_STEP_USEC (3300.0 / 256.0)
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#define CYCLES_PER_USEC (CLK_6502 / 1000000)
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#define JOY_STEP_CYCLES (JOY_STEP_USEC / CYCLES_PER_USEC)
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GLUE_C_READ(read_button0)
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{
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return joy_button0;
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}
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GLUE_C_READ(read_button1)
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{
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return joy_button1;
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}
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GLUE_C_READ(read_button2)
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{
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2016-04-17 18:26:35 +00:00
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return joy_button0 | joy_button1;
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2014-05-10 20:08:44 +00:00
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}
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GLUE_C_READ(read_gc_strobe)
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{
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// Read Game Controller (paddle) strobe ...
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// From _Understanding the Apple IIe_ :
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// * 7-29, discussing PREAD : "The timer duration will vary between 2 and 3302 usecs"
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// * 7-30, timer reset : "But the timer pulse may still be high from the previous [strobe access] and the timers are
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// not retriggered by C07X' if they have not yet reset from the previous trigger"
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if (gc_cycles_timer_0 <= 0)
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{
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2014-05-12 00:45:00 +00:00
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gc_cycles_timer_0 = (int)((joy_x-5) * JOY_STEP_CYCLES);
|
2014-05-10 20:08:44 +00:00
|
|
|
}
|
|
|
|
if (gc_cycles_timer_1 <= 0)
|
|
|
|
{
|
|
|
|
gc_cycles_timer_1 = (int)(joy_y * JOY_STEP_CYCLES) + 2;
|
|
|
|
}
|
|
|
|
|
|
|
|
// NOTE (possible TODO FIXME): unimplemented GC2 and GC3 timers since they were not wired on the //e ...
|
2015-01-31 21:57:10 +00:00
|
|
|
return floating_bus();
|
2014-05-10 20:08:44 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
GLUE_C_READ(read_gc0)
|
|
|
|
{
|
|
|
|
if (gc_cycles_timer_0 <= 0)
|
|
|
|
{
|
|
|
|
gc_cycles_timer_0 = 0;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
return 0xFF;
|
|
|
|
}
|
|
|
|
|
|
|
|
GLUE_C_READ(read_gc1)
|
|
|
|
{
|
|
|
|
if (gc_cycles_timer_1 <= 0)
|
|
|
|
{
|
|
|
|
gc_cycles_timer_1 = 0;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
return 0xFF;
|
|
|
|
}
|
|
|
|
|
|
|
|
GLUE_C_READ(iie_read_gc2)
|
|
|
|
{
|
2015-01-31 21:57:10 +00:00
|
|
|
return floating_bus();
|
2014-05-10 20:08:44 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
GLUE_C_READ(iie_read_gc3)
|
|
|
|
{
|
2015-01-31 21:57:10 +00:00
|
|
|
return floating_bus();
|
2014-05-10 20:08:44 +00:00
|
|
|
}
|
|
|
|
|
2014-05-11 05:14:46 +00:00
|
|
|
// ----------------------------------------------------------------------------
|
|
|
|
// LC : language card routines
|
|
|
|
|
2014-05-10 20:40:29 +00:00
|
|
|
static inline void _lc_to_auxmem() {
|
|
|
|
if (softswitches & SS_LCRAM) {
|
|
|
|
base_d000_rd += 0x2000;
|
|
|
|
base_e000_rd = language_card[0]-0xC000;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (softswitches & SS_LCWRT) {
|
|
|
|
base_d000_wrt += 0x2000;
|
|
|
|
base_e000_wrt = language_card[0]-0xC000;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
GLUE_C_READ(iie_c080)
|
|
|
|
{
|
|
|
|
softswitches |= (SS_LCRAM|SS_BANK2);
|
|
|
|
softswitches &= ~(SS_LCSEC|SS_LCWRT);
|
|
|
|
|
|
|
|
base_d000_rd = language_banks[0]-0xD000;
|
|
|
|
base_e000_rd = language_card[0]-0xE000;
|
|
|
|
|
|
|
|
base_d000_wrt = 0;
|
|
|
|
base_e000_wrt = 0;
|
|
|
|
|
|
|
|
if (softswitches & SS_ALTZP) {
|
|
|
|
_lc_to_auxmem();
|
|
|
|
}
|
2015-01-31 21:57:10 +00:00
|
|
|
return floating_bus();
|
2014-05-10 20:40:29 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
GLUE_C_READ(iie_c081)
|
|
|
|
{
|
|
|
|
if (softswitches & SS_LCSEC) {
|
|
|
|
softswitches |= SS_LCWRT;
|
|
|
|
base_d000_wrt = language_banks[0]-0xD000;
|
|
|
|
base_e000_wrt = language_card[0]-0xE000;
|
|
|
|
}
|
|
|
|
|
|
|
|
softswitches |= (SS_LCSEC|SS_BANK2);
|
|
|
|
softswitches &= ~SS_LCRAM;
|
|
|
|
|
|
|
|
base_d000_rd = apple_ii_64k[0];
|
|
|
|
base_e000_rd = apple_ii_64k[0];
|
|
|
|
|
|
|
|
if (softswitches & SS_ALTZP) {
|
|
|
|
_lc_to_auxmem();
|
|
|
|
}
|
2015-01-31 21:57:10 +00:00
|
|
|
return floating_bus();
|
2014-05-10 20:40:29 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
GLUE_C_READ(lc_c082)
|
|
|
|
{
|
|
|
|
softswitches &= ~(SS_LCRAM|SS_LCWRT|SS_LCSEC);
|
|
|
|
softswitches |= SS_BANK2;
|
|
|
|
|
|
|
|
base_d000_rd = apple_ii_64k[0];
|
|
|
|
base_e000_rd = apple_ii_64k[0];
|
|
|
|
|
|
|
|
base_d000_wrt = 0;
|
|
|
|
base_e000_wrt = 0;
|
|
|
|
|
2015-01-31 21:57:10 +00:00
|
|
|
return floating_bus();
|
2014-05-10 20:40:29 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
GLUE_C_READ(iie_c083)
|
|
|
|
{
|
|
|
|
if (softswitches & SS_LCSEC) {
|
|
|
|
softswitches |= SS_LCWRT;
|
|
|
|
base_d000_wrt = language_banks[0]-0xD000;
|
|
|
|
base_e000_wrt = language_card[0]-0xE000;
|
|
|
|
}
|
|
|
|
|
|
|
|
softswitches |= (SS_LCSEC|SS_LCRAM|SS_BANK2);
|
|
|
|
base_d000_rd = language_banks[0]-0xD000;
|
|
|
|
base_e000_rd = language_card[0]-0xE000;
|
|
|
|
|
|
|
|
if (softswitches & SS_ALTZP) {
|
|
|
|
_lc_to_auxmem();
|
|
|
|
}
|
2015-01-31 21:57:10 +00:00
|
|
|
return floating_bus();
|
2014-05-10 20:40:29 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
GLUE_C_READ(iie_c088)
|
|
|
|
{
|
|
|
|
softswitches |= SS_LCRAM;
|
|
|
|
softswitches &= ~(SS_LCWRT|SS_LCSEC|SS_BANK2);
|
|
|
|
|
|
|
|
base_d000_rd = language_banks[0]-0xC000;
|
|
|
|
base_e000_rd = language_card[0]-0xE000;
|
|
|
|
|
|
|
|
base_d000_wrt = 0;
|
|
|
|
base_e000_wrt = 0;
|
|
|
|
|
|
|
|
if (softswitches & SS_ALTZP) {
|
|
|
|
_lc_to_auxmem();
|
|
|
|
}
|
2015-01-31 21:57:10 +00:00
|
|
|
return floating_bus();
|
2014-05-10 20:40:29 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
GLUE_C_READ(iie_c089)
|
|
|
|
{
|
|
|
|
if (softswitches & SS_LCSEC) {
|
|
|
|
softswitches |= SS_LCWRT;
|
|
|
|
base_d000_wrt = language_banks[0]-0xC000;
|
|
|
|
base_e000_wrt = language_card[0]-0xE000;
|
|
|
|
}
|
|
|
|
|
|
|
|
softswitches |= SS_LCSEC;
|
|
|
|
softswitches &= ~(SS_LCRAM|SS_BANK2);
|
|
|
|
|
|
|
|
base_d000_rd = apple_ii_64k[0];
|
|
|
|
base_e000_rd = apple_ii_64k[0];
|
|
|
|
|
|
|
|
if (softswitches & SS_ALTZP) {
|
|
|
|
_lc_to_auxmem();
|
|
|
|
}
|
2015-01-31 21:57:10 +00:00
|
|
|
return floating_bus();
|
2014-05-10 20:40:29 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
GLUE_C_READ(lc_c08a)
|
|
|
|
{
|
|
|
|
softswitches &= ~(SS_LCRAM|SS_LCWRT|SS_LCSEC|SS_BANK2);
|
|
|
|
|
|
|
|
base_d000_rd = apple_ii_64k[0];
|
|
|
|
base_e000_rd = apple_ii_64k[0];
|
|
|
|
|
|
|
|
base_d000_wrt = 0;
|
|
|
|
base_e000_wrt = 0;
|
|
|
|
|
2015-01-31 21:57:10 +00:00
|
|
|
return floating_bus();
|
2014-05-10 20:40:29 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
GLUE_C_READ(iie_c08b)
|
|
|
|
{
|
|
|
|
if (softswitches & SS_LCSEC) {
|
|
|
|
softswitches |= SS_LCWRT;
|
|
|
|
base_d000_wrt = language_banks[0]-0xC000;
|
|
|
|
base_e000_wrt = language_card[0]-0xE000;
|
|
|
|
}
|
|
|
|
|
|
|
|
softswitches |= (SS_LCRAM|SS_LCSEC);
|
|
|
|
softswitches &= ~SS_BANK2;
|
|
|
|
|
|
|
|
base_d000_rd = language_banks[0]-0xC000;
|
|
|
|
base_e000_rd = language_card[0]-0xE000;
|
|
|
|
|
|
|
|
if (softswitches & SS_ALTZP) {
|
|
|
|
_lc_to_auxmem();
|
|
|
|
}
|
2015-01-31 21:57:10 +00:00
|
|
|
return floating_bus();
|
2014-05-10 20:40:29 +00:00
|
|
|
}
|
|
|
|
|
2014-05-11 05:14:46 +00:00
|
|
|
GLUE_C_READ(iie_check_bank)
|
|
|
|
{
|
|
|
|
return (softswitches & SS_BANK2) ? 0x80 : 0x00;
|
|
|
|
}
|
|
|
|
|
|
|
|
GLUE_C_READ(iie_check_lcram)
|
|
|
|
{
|
|
|
|
return (softswitches & SS_LCRAM) ? 0x80 : 0x00;
|
|
|
|
}
|
|
|
|
|
2014-05-10 20:59:07 +00:00
|
|
|
// ----------------------------------------------------------------------------
|
|
|
|
// Misc //e softswitches and vm routines
|
|
|
|
|
|
|
|
GLUE_C_READ(iie_80store_off)
|
|
|
|
{
|
|
|
|
if (!(softswitches & SS_80STORE)) {
|
2015-01-31 21:57:10 +00:00
|
|
|
return floating_bus();
|
2014-05-10 20:59:07 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
softswitches &= ~(SS_80STORE|SS_TEXTRD|SS_TEXTWRT|SS_HGRRD|SS_HGRWRT);
|
|
|
|
|
|
|
|
base_textrd = apple_ii_64k[0];
|
|
|
|
base_textwrt = apple_ii_64k[0];
|
|
|
|
base_hgrrd = apple_ii_64k[0];
|
|
|
|
base_hgrwrt = apple_ii_64k[0];
|
|
|
|
|
|
|
|
if (softswitches & SS_RAMRD) {
|
|
|
|
softswitches |= (SS_TEXTRD|SS_HGRRD);
|
|
|
|
base_textrd = apple_ii_64k[1];
|
|
|
|
base_hgrrd = apple_ii_64k[1];
|
|
|
|
}
|
|
|
|
|
|
|
|
if (softswitches & SS_RAMWRT) {
|
|
|
|
softswitches |= (SS_TEXTWRT|SS_HGRWRT);
|
|
|
|
base_textwrt = apple_ii_64k[1];
|
|
|
|
base_hgrwrt = apple_ii_64k[1];
|
|
|
|
}
|
|
|
|
|
|
|
|
if (softswitches & SS_PAGE2) {
|
|
|
|
softswitches |= SS_SCREEN;
|
|
|
|
}
|
|
|
|
|
2016-01-22 07:09:57 +00:00
|
|
|
video_setDirty(A2_DIRTY_FLAG);
|
|
|
|
|
2015-01-31 21:57:10 +00:00
|
|
|
return floating_bus();
|
2014-05-10 20:59:07 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
GLUE_C_READ(iie_80store_on)
|
|
|
|
{
|
|
|
|
if (softswitches & SS_80STORE) {
|
2015-01-31 21:57:10 +00:00
|
|
|
return floating_bus();
|
2014-05-10 20:59:07 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
softswitches |= SS_80STORE;
|
|
|
|
|
|
|
|
if (softswitches & SS_PAGE2) {
|
|
|
|
softswitches |= (SS_TEXTRD|SS_TEXTWRT);
|
|
|
|
base_textrd = apple_ii_64k[1];
|
|
|
|
base_textwrt = apple_ii_64k[1];
|
|
|
|
if (softswitches & SS_HIRES) {
|
|
|
|
softswitches |= (SS_HGRRD|SS_HGRWRT);
|
|
|
|
base_hgrrd = apple_ii_64k[1];
|
|
|
|
base_hgrwrt = apple_ii_64k[1];
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
softswitches &= ~(SS_TEXTRD|SS_TEXTWRT);
|
|
|
|
base_textrd = apple_ii_64k[0];
|
|
|
|
base_textwrt = apple_ii_64k[0];
|
|
|
|
if (softswitches & SS_HIRES) {
|
|
|
|
softswitches &= ~(SS_HGRRD|SS_HGRWRT);
|
|
|
|
base_hgrrd = apple_ii_64k[0];
|
|
|
|
base_hgrwrt = apple_ii_64k[0];
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
softswitches &= ~SS_SCREEN;
|
2016-01-21 05:56:25 +00:00
|
|
|
video_setDirty(A2_DIRTY_FLAG);
|
|
|
|
|
2015-01-31 21:57:10 +00:00
|
|
|
return floating_bus();
|
2014-05-10 20:59:07 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
GLUE_C_READ(iie_check_80store)
|
|
|
|
{
|
|
|
|
return (softswitches & SS_80STORE) ? 0x80 : 0x00;
|
|
|
|
}
|
|
|
|
|
2014-05-10 21:19:06 +00:00
|
|
|
GLUE_C_READ(iie_ramrd_main)
|
|
|
|
{
|
|
|
|
if (!(softswitches & SS_RAMRD)) {
|
2015-01-31 21:57:10 +00:00
|
|
|
return floating_bus();
|
2014-05-10 21:19:06 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
softswitches &= ~SS_RAMRD;
|
|
|
|
base_ramrd = apple_ii_64k[0];
|
|
|
|
|
|
|
|
if (softswitches & SS_80STORE) {
|
|
|
|
if (!(softswitches & SS_HIRES)) {
|
|
|
|
softswitches &= ~SS_HGRRD;
|
|
|
|
base_hgrrd = apple_ii_64k[0];
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
softswitches &= ~(SS_TEXTRD|SS_HGRRD);
|
|
|
|
base_textrd = apple_ii_64k[0];
|
|
|
|
base_hgrrd = apple_ii_64k[0];
|
|
|
|
}
|
|
|
|
|
2016-01-22 07:09:57 +00:00
|
|
|
video_setDirty(A2_DIRTY_FLAG);
|
|
|
|
|
2015-01-31 21:57:10 +00:00
|
|
|
return floating_bus();
|
2014-05-10 21:19:06 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
GLUE_C_READ(iie_ramrd_aux)
|
|
|
|
{
|
|
|
|
if (softswitches & SS_RAMRD) {
|
2015-01-31 21:57:10 +00:00
|
|
|
return floating_bus();
|
2014-05-10 21:19:06 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
softswitches |= SS_RAMRD;
|
|
|
|
base_ramrd = apple_ii_64k[1];
|
|
|
|
|
|
|
|
if (softswitches & SS_80STORE) {
|
|
|
|
if (!(softswitches & SS_HIRES)) {
|
|
|
|
softswitches |= SS_HGRRD;
|
|
|
|
base_hgrrd = apple_ii_64k[1];
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
softswitches |= (SS_TEXTRD|SS_HGRRD);
|
|
|
|
base_textrd = apple_ii_64k[1];
|
|
|
|
base_hgrrd = apple_ii_64k[1];
|
|
|
|
}
|
|
|
|
|
2016-01-22 07:09:57 +00:00
|
|
|
video_setDirty(A2_DIRTY_FLAG);
|
|
|
|
|
2015-01-31 21:57:10 +00:00
|
|
|
return floating_bus();
|
2014-05-10 21:19:06 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
GLUE_C_READ(iie_check_ramrd)
|
|
|
|
{
|
|
|
|
return (softswitches & SS_RAMRD) ? 0x80 : 0x00;
|
|
|
|
}
|
|
|
|
|
|
|
|
GLUE_C_READ(iie_ramwrt_main)
|
|
|
|
{
|
|
|
|
if (!(softswitches & SS_RAMWRT)) {
|
2015-01-31 21:57:10 +00:00
|
|
|
return floating_bus();
|
2014-05-10 21:19:06 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
softswitches &= ~SS_RAMWRT;
|
|
|
|
base_ramwrt = apple_ii_64k[0];
|
|
|
|
|
|
|
|
if (softswitches & SS_80STORE) {
|
|
|
|
if (!(softswitches & SS_HIRES)) {
|
|
|
|
softswitches &= ~SS_HGRWRT;
|
|
|
|
base_hgrwrt = apple_ii_64k[0];
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
softswitches &= ~(SS_TEXTWRT|SS_HGRWRT);
|
|
|
|
base_textwrt = apple_ii_64k[0];
|
|
|
|
base_hgrwrt = apple_ii_64k[0];
|
|
|
|
}
|
|
|
|
|
2015-01-31 21:57:10 +00:00
|
|
|
return floating_bus();
|
2014-05-10 21:19:06 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
GLUE_C_READ(iie_ramwrt_aux)
|
|
|
|
{
|
|
|
|
if (softswitches & SS_RAMWRT) {
|
2015-01-31 21:57:10 +00:00
|
|
|
return floating_bus();
|
2014-05-10 21:19:06 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
softswitches |= SS_RAMWRT;
|
|
|
|
base_ramwrt = apple_ii_64k[1];
|
|
|
|
|
|
|
|
if (softswitches & SS_80STORE) {
|
|
|
|
if (!(softswitches & SS_HIRES)) {
|
|
|
|
softswitches |= SS_HGRWRT;
|
|
|
|
base_hgrwrt = apple_ii_64k[1];
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
softswitches |= (SS_TEXTWRT|SS_HGRWRT);
|
|
|
|
base_textwrt = apple_ii_64k[1];
|
|
|
|
base_hgrwrt = apple_ii_64k[1];
|
|
|
|
}
|
|
|
|
|
2015-01-31 21:57:10 +00:00
|
|
|
return floating_bus();
|
2014-05-10 21:19:06 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
GLUE_C_READ(iie_check_ramwrt)
|
|
|
|
{
|
|
|
|
return (softswitches & SS_RAMWRT) ? 0x80 : 0x00;
|
|
|
|
}
|
|
|
|
|
2014-05-11 04:25:54 +00:00
|
|
|
GLUE_C_READ_ALTZP(iie_altzp_main)
|
|
|
|
{
|
|
|
|
if (!(softswitches & SS_ALTZP)) {
|
|
|
|
/* NOTE : test if ALTZP already off - due to d000-bank issues it is *needed*, not just a shortcut */
|
2015-01-31 21:57:10 +00:00
|
|
|
return floating_bus();
|
2014-05-11 04:25:54 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
softswitches &= ~SS_ALTZP;
|
|
|
|
base_stackzp = apple_ii_64k[0];
|
|
|
|
|
|
|
|
if (softswitches & SS_LCRAM) {
|
|
|
|
base_d000_rd -= 0x2000;
|
|
|
|
base_e000_rd = language_card[0] - 0xE000;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (softswitches & SS_LCWRT) {
|
|
|
|
base_d000_wrt -= 0x2000;
|
|
|
|
base_e000_wrt = language_card[0] - 0xE000;
|
|
|
|
}
|
|
|
|
|
2015-01-31 21:57:10 +00:00
|
|
|
return floating_bus();
|
2014-05-11 04:25:54 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
GLUE_C_READ_ALTZP(iie_altzp_aux)
|
|
|
|
{
|
|
|
|
if (softswitches & SS_ALTZP) {
|
|
|
|
/* NOTE : test if ALTZP already on - due to d000-bank issues it is *needed*, not just a shortcut */
|
2015-01-31 21:57:10 +00:00
|
|
|
return floating_bus();
|
2014-05-11 04:25:54 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
softswitches |= SS_ALTZP;
|
|
|
|
base_stackzp = apple_ii_64k[1];
|
|
|
|
|
|
|
|
_lc_to_auxmem();
|
|
|
|
|
2015-01-31 21:57:10 +00:00
|
|
|
return floating_bus();
|
2014-05-11 04:25:54 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
GLUE_C_READ(iie_check_altzp)
|
|
|
|
{
|
|
|
|
return (softswitches & SS_ALTZP) ? 0x80 : 0x00;
|
|
|
|
}
|
|
|
|
|
2014-05-11 04:36:55 +00:00
|
|
|
GLUE_C_READ(iie_80col_off)
|
|
|
|
{
|
|
|
|
if (!(softswitches & SS_80COL)) {
|
2015-01-31 21:57:10 +00:00
|
|
|
return floating_bus();
|
2014-05-11 04:36:55 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
softswitches &= ~SS_80COL;
|
2016-01-22 07:09:57 +00:00
|
|
|
video_setDirty(A2_DIRTY_FLAG);
|
2014-05-11 04:36:55 +00:00
|
|
|
|
2015-01-31 21:57:10 +00:00
|
|
|
return floating_bus();
|
2014-05-11 04:36:55 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
GLUE_C_READ(iie_80col_on)
|
|
|
|
{
|
|
|
|
if (softswitches & SS_80COL) {
|
2015-01-31 21:57:10 +00:00
|
|
|
return floating_bus();
|
2014-05-11 04:36:55 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
softswitches |= SS_80COL;
|
2016-01-22 07:09:57 +00:00
|
|
|
video_setDirty(A2_DIRTY_FLAG);
|
2014-05-11 04:36:55 +00:00
|
|
|
|
2015-01-31 21:57:10 +00:00
|
|
|
return floating_bus();
|
2014-05-11 04:36:55 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
GLUE_C_READ(iie_check_80col)
|
|
|
|
{
|
|
|
|
return (softswitches & SS_80COL) ? 0x80 : 0x00;
|
|
|
|
}
|
|
|
|
|
2014-05-11 04:41:48 +00:00
|
|
|
GLUE_C_READ(iie_altchar_off)
|
|
|
|
{
|
|
|
|
if (softswitches & SS_ALTCHAR) {
|
|
|
|
softswitches &= ~SS_ALTCHAR;
|
2015-09-11 07:00:04 +00:00
|
|
|
video_loadfont(0x40,0x40,ucase_glyphs,3);
|
2016-01-22 07:09:57 +00:00
|
|
|
video_setDirty(A2_DIRTY_FLAG);
|
2014-05-11 04:41:48 +00:00
|
|
|
}
|
2015-01-31 21:57:10 +00:00
|
|
|
return floating_bus();
|
2014-05-11 04:41:48 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
GLUE_C_READ(iie_altchar_on)
|
|
|
|
{
|
|
|
|
if (!(softswitches & SS_ALTCHAR)) {
|
|
|
|
softswitches |= SS_ALTCHAR;
|
2015-09-11 07:00:04 +00:00
|
|
|
video_loadfont(0x40,0x20,mousetext_glyphs,1);
|
|
|
|
video_loadfont(0x60,0x20,lcase_glyphs,2);
|
2016-01-22 07:09:57 +00:00
|
|
|
video_setDirty(A2_DIRTY_FLAG);
|
2014-05-11 04:41:48 +00:00
|
|
|
}
|
2015-01-31 21:57:10 +00:00
|
|
|
return floating_bus();
|
2014-05-11 04:41:48 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
GLUE_C_READ(iie_check_altchar)
|
|
|
|
{
|
|
|
|
return (softswitches & SS_ALTCHAR) ? 0x80 : 0x00;
|
|
|
|
}
|
|
|
|
|
2014-05-11 05:07:25 +00:00
|
|
|
GLUE_C_READ(iie_ioudis_off)
|
|
|
|
{
|
|
|
|
softswitches &= ~SS_IOUDIS;
|
|
|
|
return c_read_gc_strobe(ea);
|
|
|
|
}
|
|
|
|
|
|
|
|
GLUE_C_READ(iie_ioudis_on)
|
|
|
|
{
|
|
|
|
softswitches |= SS_IOUDIS;
|
|
|
|
return c_read_gc_strobe(ea);
|
|
|
|
}
|
|
|
|
|
|
|
|
GLUE_C_READ(iie_check_ioudis)
|
|
|
|
{
|
|
|
|
c_read_gc_strobe(ea);
|
|
|
|
return (softswitches & SS_IOUDIS) ? 0x80 : 0x00;
|
|
|
|
}
|
|
|
|
|
|
|
|
GLUE_C_READ(iie_dhires_on)
|
|
|
|
{
|
|
|
|
if (!(softswitches & SS_DHIRES)) {
|
|
|
|
softswitches |= SS_DHIRES;
|
2016-01-22 07:09:57 +00:00
|
|
|
video_setDirty(A2_DIRTY_FLAG);
|
2014-05-11 05:07:25 +00:00
|
|
|
}
|
2015-01-31 21:57:10 +00:00
|
|
|
return floating_bus();
|
2014-05-11 05:07:25 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
GLUE_C_READ(iie_dhires_off)
|
|
|
|
{
|
|
|
|
if (softswitches & SS_DHIRES) {
|
|
|
|
softswitches &= ~SS_DHIRES;
|
2016-01-22 07:09:57 +00:00
|
|
|
video_setDirty(A2_DIRTY_FLAG);
|
2014-05-11 05:07:25 +00:00
|
|
|
}
|
2015-01-31 21:57:10 +00:00
|
|
|
return floating_bus();
|
2014-05-11 05:07:25 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
GLUE_C_READ(iie_check_dhires)
|
|
|
|
{
|
|
|
|
c_read_gc_strobe(ea); // HACK FIXME : is this correct?
|
|
|
|
return (softswitches & SS_DHIRES) ? 0x80 : 0x00;
|
|
|
|
}
|
|
|
|
|
2014-05-11 05:39:03 +00:00
|
|
|
GLUE_C_READ(iie_check_vbl)
|
|
|
|
{
|
2015-01-10 17:53:38 +00:00
|
|
|
bool vbl_bar = false;
|
2015-01-31 21:57:10 +00:00
|
|
|
video_scanner_get_address(&vbl_bar);
|
2015-01-18 19:06:02 +00:00
|
|
|
uint8_t key = apple_ii_64k[0][0xC000];
|
2015-01-10 17:53:38 +00:00
|
|
|
return (key & ~0x80) | (vbl_bar ? 0x80 : 0x00);
|
2014-05-11 05:39:03 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
GLUE_C_READ(iie_c3rom_peripheral)
|
|
|
|
{
|
|
|
|
softswitches &= ~SS_C3ROM;
|
|
|
|
if (!(softswitches & SS_CXROM)) {
|
|
|
|
base_c3rom = apple_ii_64k[0];
|
|
|
|
}
|
|
|
|
return 0x0;
|
|
|
|
}
|
|
|
|
|
|
|
|
GLUE_C_READ(iie_c3rom_internal)
|
|
|
|
{
|
|
|
|
softswitches |= SS_C3ROM;
|
|
|
|
base_c3rom = apple_ii_64k[1];
|
|
|
|
return 0x0;
|
|
|
|
}
|
|
|
|
|
|
|
|
GLUE_C_READ(iie_check_c3rom)
|
|
|
|
{
|
|
|
|
return (softswitches & SS_C3ROM) ? 0x00 : 0x80; // reversed pattern
|
|
|
|
}
|
|
|
|
|
|
|
|
typedef uint8_t *(VMFunc)(uint16_t);
|
|
|
|
|
|
|
|
GLUE_C_READ(iie_cxrom_peripheral)
|
|
|
|
{
|
|
|
|
softswitches &= ~SS_CXROM;
|
|
|
|
base_cxrom = apple_ii_64k[0];
|
|
|
|
#ifdef AUDIO_ENABLED
|
|
|
|
extern VMFunc MB_Read;
|
|
|
|
base_c4rom = (void*)MB_Read;
|
|
|
|
base_c5rom = (void*)MB_Read;
|
2015-03-09 19:28:10 +00:00
|
|
|
#else
|
|
|
|
base_c4rom = (void*)ram_nop;
|
|
|
|
base_c5rom = (void*)ram_nop;
|
2014-05-11 05:39:03 +00:00
|
|
|
#endif
|
|
|
|
if (!(softswitches & SS_C3ROM)) {
|
|
|
|
base_c3rom = apple_ii_64k[0];
|
|
|
|
}
|
|
|
|
return 0x0;
|
|
|
|
}
|
|
|
|
|
|
|
|
GLUE_C_READ(iie_cxrom_internal)
|
|
|
|
{
|
|
|
|
softswitches |= SS_CXROM;
|
|
|
|
base_cxrom = apple_ii_64k[1];
|
|
|
|
base_c3rom = apple_ii_64k[1];
|
|
|
|
base_c4rom = apple_ii_64k[1];
|
|
|
|
base_c5rom = apple_ii_64k[1];
|
|
|
|
return 0x0;
|
|
|
|
}
|
|
|
|
|
|
|
|
GLUE_C_READ(iie_check_cxrom)
|
|
|
|
{
|
|
|
|
return (softswitches & SS_CXROM) ? 0x80 : 0x00;
|
|
|
|
}
|
|
|
|
|
2014-05-11 20:42:55 +00:00
|
|
|
GLUE_C_READ(iie_read_slot_expansion)
|
|
|
|
{
|
|
|
|
// HACK TODO FIXME : how does the expansion slot get referenced? Need to handle other ROMs that might use this area
|
|
|
|
// ... Also Need moar tests ...
|
2015-01-11 00:13:36 +00:00
|
|
|
if (ea == 0xCFFF) {
|
|
|
|
// disable expansion ROM
|
|
|
|
}
|
2014-05-11 20:42:55 +00:00
|
|
|
return apple_ii_64k[1][ea];
|
|
|
|
}
|
|
|
|
|
2015-09-11 07:00:04 +00:00
|
|
|
GLUE_C_READ(debug_illegal_bcd)
|
|
|
|
{
|
|
|
|
RELEASE_LOG("Illegal/undefined BCD operation encountered, debug break on c_debug_illegal_bcd to debug...");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-11-23 20:53:59 +00:00
|
|
|
// ----------------------------------------------------------------------------
|
|
|
|
|
2015-09-11 07:00:04 +00:00
|
|
|
static void _initialize_iie_switches(void) {
|
|
|
|
|
|
|
|
base_stackzp = apple_ii_64k[0];
|
|
|
|
base_d000_rd = apple_ii_64k[0];
|
|
|
|
base_d000_wrt = language_banks[0] - 0xD000;
|
|
|
|
base_e000_rd = apple_ii_64k[0];
|
|
|
|
base_e000_wrt = language_card[0] - 0xE000;
|
|
|
|
|
|
|
|
base_ramrd = apple_ii_64k[0];
|
|
|
|
base_ramwrt = apple_ii_64k[0];
|
|
|
|
base_textrd = apple_ii_64k[0];
|
|
|
|
base_textwrt = apple_ii_64k[0];
|
|
|
|
base_hgrrd = apple_ii_64k[0];
|
|
|
|
base_hgrwrt= apple_ii_64k[0];
|
|
|
|
|
|
|
|
base_c3rom = apple_ii_64k[1]; // c3rom internal
|
|
|
|
base_c4rom = apple_ii_64k[1]; // c4rom internal
|
|
|
|
base_c5rom = apple_ii_64k[1]; // c5rom internal
|
|
|
|
base_cxrom = apple_ii_64k[0]; // cxrom peripheral
|
|
|
|
}
|
|
|
|
|
|
|
|
static void _initialize_font(void) {
|
|
|
|
video_loadfont(0x00,0x40,ucase_glyphs,2);
|
|
|
|
video_loadfont(0x40,0x40,ucase_glyphs,3);
|
|
|
|
video_loadfont(0x80,0x40,ucase_glyphs,0);
|
|
|
|
video_loadfont(0xC0,0x20,ucase_glyphs,0);
|
|
|
|
video_loadfont(0xE0,0x20,lcase_glyphs,0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void _initialize_apple_ii_memory(void) {
|
|
|
|
for (unsigned int i = 0; i < 0x10000; i++) {
|
|
|
|
apple_ii_64k[0][i] = 0;
|
|
|
|
apple_ii_64k[1][i] = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Stripe words of main memory on machine reset ...
|
|
|
|
// NOTE: cracked version of J---- will lock up without this
|
|
|
|
for (unsigned int i = 0; i < 0xC000;) {
|
|
|
|
apple_ii_64k[0][i++] = 0xFF;
|
|
|
|
apple_ii_64k[0][i++] = 0xFF;
|
|
|
|
i += 2;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (unsigned int i = 0; i < 8192; i++) {
|
|
|
|
language_card[0][i] = language_card[1][i] = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (unsigned int i = 0; i < 8192; i++) {
|
|
|
|
language_banks[0][i] = language_banks[1][i] = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
// load the rom from 0xC000, slot rom main, internal rom aux
|
|
|
|
|
|
|
|
for (unsigned int i = 0xC000; i < 0x10000; i++) {
|
|
|
|
apple_ii_64k[0][i] = apple_iie_rom[i - 0xC000];
|
|
|
|
apple_ii_64k[1][i] = apple_iie_rom[i - 0x8000];
|
|
|
|
}
|
|
|
|
|
|
|
|
for (unsigned int i = 0; i < 0x1000; i++) {
|
|
|
|
language_banks[0][i] = apple_iie_rom[i + 0x1000];
|
|
|
|
language_banks[1][i] = apple_iie_rom[i + 0x5000];
|
|
|
|
}
|
|
|
|
|
|
|
|
for (unsigned int i = 0; i < 0x2000; i++) {
|
|
|
|
language_card[0][i] = apple_iie_rom[i + 0x2000];
|
|
|
|
language_card[1][i] = apple_iie_rom[i + 0x6000];
|
|
|
|
}
|
|
|
|
|
|
|
|
apple_ii_64k[0][0xC000] = 0x00;
|
|
|
|
apple_ii_64k[1][0xC000] = 0x00;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void _initialize_tables(void) {
|
|
|
|
|
|
|
|
for (unsigned int i = 0; i < 0x10000; i++) {
|
|
|
|
cpu65_vmem_r[i] = iie_read_ram_default;
|
|
|
|
cpu65_vmem_w[i] = iie_write_ram_default;
|
|
|
|
}
|
|
|
|
|
|
|
|
// language card read/write area
|
|
|
|
|
|
|
|
for (unsigned int i = 0xD000; i < 0xE000; i++) {
|
|
|
|
cpu65_vmem_w[i] = write_ram_bank;
|
|
|
|
cpu65_vmem_r[i] = read_ram_bank;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (unsigned int i = 0xE000; i < 0x10000; i++) {
|
|
|
|
cpu65_vmem_w[i] = write_ram_lc;
|
|
|
|
cpu65_vmem_r[i] = read_ram_lc;
|
|
|
|
}
|
|
|
|
|
|
|
|
// done common initialization
|
|
|
|
|
|
|
|
// initialize zero-page, //e specific
|
|
|
|
for (unsigned int i = 0; i < 0x200; i++) {
|
|
|
|
cpu65_vmem_r[i] = iie_read_ram_zpage_and_stack;
|
|
|
|
cpu65_vmem_w[i] = iie_write_ram_zpage_and_stack;
|
|
|
|
}
|
|
|
|
|
|
|
|
// initialize first text & hires page, which are specially bank switched
|
|
|
|
//
|
|
|
|
// video_reset() below substitutes it's own hooks for all visible write locations affect the display, leaving our
|
|
|
|
// write-functions in place only at the `screen holes', hence the name.
|
|
|
|
for (unsigned int i = 0x400; i < 0x800; i++) {
|
|
|
|
cpu65_vmem_r[i] = iie_read_ram_text_page0;
|
|
|
|
cpu65_vmem_w[i] = iie_write_screen_hole_text_page0;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (unsigned int i = 0x2000; i < 0x4000; i++) {
|
|
|
|
cpu65_vmem_r[i] = iie_read_ram_hires_page0;
|
|
|
|
cpu65_vmem_w[i] = iie_write_screen_hole_hires_page0;
|
|
|
|
}
|
|
|
|
|
|
|
|
// softswich rom
|
|
|
|
for (unsigned int i = 0xC000; i < 0xC100; i++) {
|
|
|
|
cpu65_vmem_r[i] = read_unmapped_softswitch;
|
|
|
|
cpu65_vmem_w[i] = write_unmapped_softswitch;
|
|
|
|
}
|
|
|
|
|
|
|
|
// slot rom defaults
|
|
|
|
for (unsigned int i = 0xC100; i < 0xD000; i++) {
|
|
|
|
cpu65_vmem_r[i] = iie_read_ram_default;
|
|
|
|
cpu65_vmem_w[i] = ram_nop;
|
|
|
|
}
|
|
|
|
|
|
|
|
// keyboard data and strobe (READ)
|
|
|
|
for (unsigned int i = 0xC000; i < 0xC010; i++) {
|
|
|
|
cpu65_vmem_r[i] = read_keyboard;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (unsigned int i = 0xC010; i < 0xC020; i++) {
|
|
|
|
cpu65_vmem_r[i] = cpu65_vmem_w[i] = read_keyboard_strobe;
|
|
|
|
}
|
|
|
|
|
|
|
|
// RDBNK2 switch
|
|
|
|
cpu65_vmem_r[0xC011] = iie_check_bank;
|
|
|
|
|
|
|
|
// RDLCRAM switch
|
|
|
|
cpu65_vmem_r[0xC012] = iie_check_lcram;
|
|
|
|
|
|
|
|
// 80STORE switch
|
|
|
|
cpu65_vmem_w[0xC000] = iie_80store_off;
|
|
|
|
cpu65_vmem_w[0xC001] = iie_80store_on;
|
|
|
|
cpu65_vmem_r[0xC018] = iie_check_80store;
|
|
|
|
|
|
|
|
// RAMRD switch
|
|
|
|
cpu65_vmem_w[0xC002] = iie_ramrd_main;
|
|
|
|
cpu65_vmem_w[0xC003] = iie_ramrd_aux;
|
|
|
|
cpu65_vmem_r[0xC013] = iie_check_ramrd;
|
|
|
|
|
|
|
|
// RAMWRT switch
|
|
|
|
cpu65_vmem_w[0xC004] = iie_ramwrt_main;
|
|
|
|
cpu65_vmem_w[0xC005] = iie_ramwrt_aux;
|
|
|
|
cpu65_vmem_r[0xC014] = iie_check_ramwrt;
|
|
|
|
|
|
|
|
// ALTZP switch
|
|
|
|
cpu65_vmem_w[0xC008] = iie_altzp_main;
|
|
|
|
cpu65_vmem_w[0xC009] = iie_altzp_aux;
|
|
|
|
cpu65_vmem_r[0xC016] = iie_check_altzp;
|
|
|
|
|
|
|
|
// 80COL switch
|
|
|
|
cpu65_vmem_w[0xC00C] = iie_80col_off;
|
|
|
|
cpu65_vmem_w[0xC00D] = iie_80col_on;
|
|
|
|
cpu65_vmem_r[0xC01F] = iie_check_80col;
|
|
|
|
|
|
|
|
// ALTCHAR switch
|
|
|
|
cpu65_vmem_w[0xC00E] = iie_altchar_off;
|
|
|
|
cpu65_vmem_w[0xC00F] = iie_altchar_on;
|
|
|
|
cpu65_vmem_r[0xC01E] = iie_check_altchar;
|
|
|
|
|
|
|
|
// SLOTC3ROM switch
|
|
|
|
cpu65_vmem_w[0xC00A] = iie_c3rom_internal;
|
|
|
|
cpu65_vmem_w[0xC00B] = iie_c3rom_peripheral;
|
|
|
|
cpu65_vmem_r[0xC017] = iie_check_c3rom;
|
|
|
|
|
|
|
|
// SLOTCXROM switch
|
|
|
|
cpu65_vmem_w[0xC006] = iie_cxrom_peripheral;
|
|
|
|
cpu65_vmem_w[0xC007] = iie_cxrom_internal;
|
|
|
|
cpu65_vmem_r[0xC015] = iie_check_cxrom;
|
|
|
|
|
|
|
|
// RDVBLBAR switch
|
|
|
|
cpu65_vmem_r[0xC019] = iie_check_vbl;
|
|
|
|
|
|
|
|
// TEXT switch
|
|
|
|
cpu65_vmem_r[0xC050] = cpu65_vmem_w[0xC050] = read_switch_graphics;
|
|
|
|
cpu65_vmem_r[0xC051] = cpu65_vmem_w[0xC051] = read_switch_text;
|
|
|
|
cpu65_vmem_r[0xC01A] = iie_check_text;
|
|
|
|
|
|
|
|
// MIXED switch
|
|
|
|
cpu65_vmem_r[0xC052] = cpu65_vmem_w[0xC052] = read_switch_no_mixed;
|
|
|
|
cpu65_vmem_r[0xC053] = cpu65_vmem_w[0xC053] = read_switch_mixed;
|
|
|
|
cpu65_vmem_r[0xC01B] = iie_check_mixed;
|
|
|
|
|
|
|
|
// PAGE2 switch
|
|
|
|
cpu65_vmem_r[0xC054] = cpu65_vmem_w[0xC054] = iie_page2_off;
|
|
|
|
cpu65_vmem_r[0xC01C] = iie_check_page2;
|
|
|
|
cpu65_vmem_r[0xC055] = cpu65_vmem_w[0xC055] = iie_page2_on;
|
|
|
|
|
|
|
|
// HIRES switch
|
|
|
|
cpu65_vmem_r[0xC01D] = iie_check_hires;
|
|
|
|
cpu65_vmem_r[0xC056] = cpu65_vmem_w[0xC056] = iie_hires_off;
|
|
|
|
cpu65_vmem_r[0xC057] = cpu65_vmem_w[0xC057] = iie_hires_on;
|
|
|
|
|
|
|
|
// game I/O switches
|
|
|
|
cpu65_vmem_r[0xC061] = cpu65_vmem_r[0xC069] = read_button0;
|
|
|
|
cpu65_vmem_r[0xC062] = cpu65_vmem_r[0xC06A] = read_button1;
|
|
|
|
cpu65_vmem_r[0xC063] = cpu65_vmem_r[0xC06B] = read_button2;
|
|
|
|
cpu65_vmem_r[0xC064] = cpu65_vmem_r[0xC06C] = read_gc0;
|
|
|
|
cpu65_vmem_r[0xC065] = cpu65_vmem_r[0xC06D] = read_gc1;
|
|
|
|
cpu65_vmem_r[0xC066] = iie_read_gc2;
|
|
|
|
cpu65_vmem_r[0xC067] = iie_read_gc3;
|
|
|
|
|
|
|
|
for (unsigned int i = 0xC070; i < 0xC080; i++) {
|
|
|
|
cpu65_vmem_r[i] = cpu65_vmem_w[i] = read_gc_strobe;
|
|
|
|
}
|
|
|
|
|
|
|
|
// IOUDIS switch & read_gc_strobe
|
|
|
|
cpu65_vmem_w[0xC07E] = iie_ioudis_on;
|
|
|
|
cpu65_vmem_w[0xC07F] = iie_ioudis_off; // HACK FIXME TODO : double-check this stuff against AWin...
|
|
|
|
cpu65_vmem_r[0xC07E] = iie_check_ioudis;
|
|
|
|
cpu65_vmem_r[0xC07F] = iie_check_dhires;
|
|
|
|
|
|
|
|
// Annunciator
|
|
|
|
for (unsigned int i = 0xC058; i <= 0xC05D; i++) {
|
|
|
|
cpu65_vmem_w[i] = cpu65_vmem_r[i] = iie_annunciator;
|
|
|
|
}
|
|
|
|
|
|
|
|
// DHIRES
|
|
|
|
cpu65_vmem_w[0xC05E] = cpu65_vmem_r[0xC05E] = iie_dhires_on;
|
|
|
|
cpu65_vmem_w[0xC05F] = cpu65_vmem_r[0xC05F] = iie_dhires_off;
|
|
|
|
|
|
|
|
// language card softswitches
|
|
|
|
cpu65_vmem_r[0xC080] = cpu65_vmem_w[0xC080] = cpu65_vmem_r[0xC084] = cpu65_vmem_w[0xC084] = iie_c080;
|
|
|
|
cpu65_vmem_r[0xC081] = cpu65_vmem_w[0xC081] = cpu65_vmem_r[0xC085] = cpu65_vmem_w[0xC085] = iie_c081;
|
|
|
|
cpu65_vmem_r[0xC082] = cpu65_vmem_w[0xC082] = cpu65_vmem_r[0xC086] = cpu65_vmem_w[0xC086] = lc_c082;
|
|
|
|
cpu65_vmem_r[0xC083] = cpu65_vmem_w[0xC083] = cpu65_vmem_r[0xC087] = cpu65_vmem_w[0xC087] = iie_c083;
|
|
|
|
|
|
|
|
cpu65_vmem_r[0xC088] = cpu65_vmem_w[0xC088] = cpu65_vmem_r[0xC08C] = cpu65_vmem_w[0xC08C] = iie_c088;
|
|
|
|
cpu65_vmem_r[0xC089] = cpu65_vmem_w[0xC089] = cpu65_vmem_r[0xC08D] = cpu65_vmem_w[0xC08D] = iie_c089;
|
|
|
|
cpu65_vmem_r[0xC08A] = cpu65_vmem_w[0xC08A] = cpu65_vmem_r[0xC08E] = cpu65_vmem_w[0xC08E] = lc_c08a;
|
|
|
|
cpu65_vmem_r[0xC08B] = cpu65_vmem_w[0xC08B] = cpu65_vmem_r[0xC08F] = cpu65_vmem_w[0xC08F] = iie_c08b;
|
|
|
|
|
|
|
|
// slot i/o area
|
|
|
|
for (unsigned int i = 0xC100; i < 0xC300; i++) {
|
|
|
|
cpu65_vmem_r[i] = iie_read_slotx; // slots 1 & 2 (x)
|
|
|
|
}
|
|
|
|
|
|
|
|
for (unsigned int i = 0xC300; i < 0xC400; i++) {
|
|
|
|
cpu65_vmem_r[i] = iie_read_slot3; // slot 3 (80col)
|
|
|
|
}
|
|
|
|
|
|
|
|
for (unsigned int i = 0xC400; i < 0xC500; i++) {
|
|
|
|
cpu65_vmem_r[i] = iie_read_slot4; // slot 4 - MB or Phasor
|
|
|
|
}
|
|
|
|
|
|
|
|
for (unsigned int i = 0xC500; i < 0xC600; i++) {
|
|
|
|
cpu65_vmem_r[i] = iie_read_slot5; // slot 5 - MB #2
|
|
|
|
}
|
|
|
|
|
|
|
|
for (unsigned int i = 0xC600; i < 0xC800; i++) {
|
|
|
|
cpu65_vmem_r[i] = iie_read_slotx; // slots 6 - 7 (x)
|
|
|
|
}
|
|
|
|
|
|
|
|
for (unsigned int i = 0xC800; i < 0xD000; i++) {
|
|
|
|
cpu65_vmem_r[i] = iie_read_slot_expansion;
|
|
|
|
}
|
|
|
|
|
|
|
|
cpu65_vmem_w[0xCFFF] = iie_read_slot_expansion;
|
|
|
|
|
|
|
|
video_reset();
|
|
|
|
|
|
|
|
// Peripheral card slot initializations ...
|
|
|
|
|
|
|
|
// HACK TODO FIXME : this needs to be tied to the UI/configuration system (once we have more/conflicting options)
|
|
|
|
|
|
|
|
#ifdef AUDIO_ENABLED
|
|
|
|
mb_io_initialize(4, 5); /* Mockingboard(s) and/or Phasor in slots 4 & 5 */
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
// ----------------------------------------------------------------------------
|
|
|
|
|
|
|
|
void vm_initialize(void) {
|
|
|
|
_initialize_font();
|
|
|
|
_initialize_apple_ii_memory();
|
|
|
|
_initialize_tables();
|
|
|
|
vm_reinitializeAudio();
|
2015-10-16 04:23:21 +00:00
|
|
|
disk6_init();
|
2015-09-11 07:00:04 +00:00
|
|
|
_initialize_iie_switches();
|
|
|
|
c_joystick_reset();
|
|
|
|
}
|
|
|
|
|
|
|
|
void vm_reinitializeAudio(void) {
|
|
|
|
for (unsigned int i = 0xC030; i < 0xC040; i++) {
|
|
|
|
cpu65_vmem_r[i] = cpu65_vmem_w[i] =
|
|
|
|
#ifdef AUDIO_ENABLED
|
2016-03-26 05:34:33 +00:00
|
|
|
speaker_toggle;
|
|
|
|
#else
|
2015-09-11 07:00:04 +00:00
|
|
|
ram_nop;
|
2016-03-26 05:34:33 +00:00
|
|
|
#endif
|
2015-09-11 07:00:04 +00:00
|
|
|
}
|
|
|
|
#warning TODO FIXME ... should unset MB/Phasor hooks if volume is zero ...
|
|
|
|
}
|
|
|
|
|
2015-11-23 03:04:46 +00:00
|
|
|
bool vm_saveState(StateHelper_s *helper) {
|
|
|
|
bool saved = false;
|
|
|
|
int fd = helper->fd;
|
|
|
|
|
|
|
|
do {
|
|
|
|
uint8_t serialized[8] = { 0 };
|
|
|
|
|
|
|
|
serialized[0] = (uint8_t)((softswitches & 0xFF000000) >> 24);
|
|
|
|
serialized[1] = (uint8_t)((softswitches & 0xFF0000 ) >> 16);
|
|
|
|
serialized[2] = (uint8_t)((softswitches & 0xFF00 ) >> 8);
|
|
|
|
serialized[3] = (uint8_t)((softswitches & 0xFF ) >> 0);
|
|
|
|
LOG("SAVE softswitches = %08x", softswitches);
|
|
|
|
if (!helper->save(fd, serialized, sizeof(softswitches))) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
// save main/aux memory state
|
|
|
|
if (!helper->save(fd, apple_ii_64k[0], sizeof(apple_ii_64k))) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
// save language card
|
|
|
|
if (!helper->save(fd, language_card[0], sizeof(language_card))) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
// save language banks
|
|
|
|
if (!helper->save(fd, language_banks[0], sizeof(language_banks))) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
// save offsets
|
|
|
|
serialized[0] = 0x0;
|
|
|
|
serialized[1] = 0x1;
|
|
|
|
serialized[2] = 0x2;
|
|
|
|
serialized[3] = 0x3;
|
|
|
|
serialized[4] = 0x4;
|
|
|
|
serialized[5] = 0x5;
|
|
|
|
LOG("SAVE base_ramrd = %d", (base_ramrd == apple_ii_64k[0]) ? serialized[0] : serialized[1]);
|
|
|
|
if (!helper->save(fd, (base_ramrd == apple_ii_64k[0]) ? &serialized[0] : &serialized[1], 1)) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
LOG("SAVE base_ramwrt = %d", (base_ramwrt == apple_ii_64k[0]) ? serialized[0] : serialized[1]);
|
|
|
|
if (!helper->save(fd, (base_ramwrt == apple_ii_64k[0]) ? &serialized[0] : &serialized[1], 1)) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
LOG("SAVE base_textrd = %d", (base_textrd == apple_ii_64k[0]) ? serialized[0] : serialized[1]);
|
|
|
|
if (!helper->save(fd, (base_textrd == apple_ii_64k[0]) ? &serialized[0] : &serialized[1], 1)) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
LOG("SAVE base_textwrt = %d", (base_textwrt == apple_ii_64k[0]) ? serialized[0] : serialized[1]);
|
|
|
|
if (!helper->save(fd, (base_textwrt == apple_ii_64k[0]) ? &serialized[0] : &serialized[1], 1)) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
LOG("SAVE base_hgrrd = %d", (base_hgrrd == apple_ii_64k[0]) ? serialized[0] : serialized[1]);
|
|
|
|
if (!helper->save(fd, (base_hgrrd == apple_ii_64k[0]) ? &serialized[0] : &serialized[1], 1)) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
LOG("SAVE base_hgrwrt = %d", (base_hgrwrt == apple_ii_64k[0]) ? serialized[0] : serialized[1]);
|
|
|
|
if (!helper->save(fd, (base_hgrwrt == apple_ii_64k[0]) ? &serialized[0] : &serialized[1], 1)) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
LOG("SAVE base_stackzp = %d", (base_stackzp == apple_ii_64k[0]) ? serialized[0] : serialized[1]);
|
|
|
|
if (!helper->save(fd, (base_stackzp == apple_ii_64k[0]) ? &serialized[0] : &serialized[1], 1)) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
LOG("SAVE base_c3rom = %d", (base_c3rom == apple_ii_64k[0]) ? serialized[0] : serialized[1]);
|
|
|
|
if (!helper->save(fd, (base_c3rom == apple_ii_64k[0]) ? &serialized[0] : &serialized[1], 1)) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
LOG("SAVE base_cxrom = %d", (base_cxrom == apple_ii_64k[0]) ? serialized[0] : serialized[1]);
|
|
|
|
if (!helper->save(fd, (base_cxrom == apple_ii_64k[0]) ? &serialized[0] : &serialized[1], 1)) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (base_d000_rd == apple_ii_64k[0]) {
|
|
|
|
LOG("SAVE base_d000_rd = %d", serialized[0]);
|
|
|
|
if (!helper->save(fd, &serialized[0], 1)) { // base_d000_rd --> //e ROM
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
} else if (base_d000_rd == language_banks[0] - 0xD000) {
|
|
|
|
LOG("SAVE base_d000_rd = %d", serialized[2]);
|
|
|
|
if (!helper->save(fd, &serialized[2], 1)) { // base_d000_rd --> main LC mem
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
} else if (base_d000_rd == language_banks[0] - 0xC000) {
|
|
|
|
LOG("SAVE base_d000_rd = %d", serialized[3]);
|
|
|
|
if (!helper->save(fd, &serialized[3], 1)) { // base_d000_rd --> main LC mem
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
} else if (base_d000_rd == language_banks[1] - 0xD000) {
|
|
|
|
LOG("SAVE base_d000_rd = %d", serialized[4]);
|
|
|
|
if (!helper->save(fd, &serialized[4], 1)) { // base_d000_rd --> aux LC mem
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
} else if (base_d000_rd == language_banks[1] - 0xC000) {
|
|
|
|
LOG("SAVE base_d000_rd = %d", serialized[5]);
|
|
|
|
if (!helper->save(fd, &serialized[5], 1)) { // base_d000_rd --> aux LC mem
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
LOG("OOPS ... language_banks[0] == %p base_d000_rd == %p", language_banks[0], base_d000_rd);
|
|
|
|
RELEASE_BREAK();
|
|
|
|
}
|
|
|
|
|
|
|
|
if (base_d000_wrt == 0) {
|
|
|
|
LOG("SAVE base_d000_wrt = %d", serialized[0]);
|
|
|
|
if (!helper->save(fd, &serialized[0], 1)) { // base_d000_wrt --> no write
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
} else if (base_d000_wrt == language_banks[0] - 0xD000) {
|
|
|
|
LOG("SAVE base_d000_wrt = %d", serialized[2]);
|
|
|
|
if (!helper->save(fd, &serialized[2], 1)) { // base_d000_wrt --> main LC mem
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
} else if (base_d000_wrt == language_banks[0] - 0xC000) {
|
|
|
|
LOG("SAVE base_d000_wrt = %d", serialized[3]);
|
|
|
|
if (!helper->save(fd, &serialized[3], 1)) { // base_d000_wrt --> main LC mem
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
} else if (base_d000_wrt == language_banks[1] - 0xD000) {
|
|
|
|
LOG("SAVE base_d000_wrt = %d", serialized[4]);
|
|
|
|
if (!helper->save(fd, &serialized[4], 1)) { // base_d000_wrt --> aux LC mem
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
} else if (base_d000_wrt == language_banks[1] - 0xC000) {
|
|
|
|
LOG("SAVE base_d000_wrt = %d", serialized[5]);
|
|
|
|
if (!helper->save(fd, &serialized[5], 1)) { // base_d000_wrt --> aux LC mem
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
LOG("OOPS ... language_banks[0] == %p base_d000_wrt == %p", language_banks[0], base_d000_wrt);
|
|
|
|
RELEASE_BREAK();
|
|
|
|
}
|
|
|
|
|
|
|
|
if (base_e000_rd == apple_ii_64k[0]) {
|
|
|
|
LOG("SAVE base_e000_rd = %d", serialized[0]);
|
|
|
|
if (!helper->save(fd, &serialized[0], 1)) { // base_e000_rd --> //e ROM
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
} else if (base_e000_rd == language_card[0] - 0xE000) {
|
|
|
|
LOG("SAVE base_e000_rd = %d", serialized[2]);
|
|
|
|
if (!helper->save(fd, &serialized[2], 1)) { // base_e000_rd --> main LC mem
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
} else if (base_e000_rd == language_card[0] - 0xC000) {
|
|
|
|
LOG("SAVE base_e000_rd = %d", serialized[3]);
|
|
|
|
if (!helper->save(fd, &serialized[3], 1)) { // base_e000_rd --> aux LC mem
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
LOG("OOPS ... language_card[0] == %p base_e000_rd == %p", language_card[0], base_e000_rd);
|
|
|
|
RELEASE_BREAK();
|
|
|
|
}
|
|
|
|
|
|
|
|
if (base_e000_wrt == 0) {
|
|
|
|
LOG("SAVE base_e000_wrt = %d", serialized[0]);
|
|
|
|
if (!helper->save(fd, &serialized[0], 1)) { // base_e000_wrt --> no write
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
} else if (base_e000_wrt == language_card[0] - 0xE000) {
|
|
|
|
LOG("SAVE base_e000_wrt = %d", serialized[2]);
|
|
|
|
if (!helper->save(fd, &serialized[2], 1)) { // base_e000_wrt --> main LC mem
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
} else if (base_e000_wrt == language_card[0] - 0xC000) {
|
|
|
|
LOG("SAVE base_e000_wrt = %d", serialized[3]);
|
|
|
|
if (!helper->save(fd, &serialized[3], 1)) { // base_e000_wrt --> aux LC mem
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
LOG("OOPS ... language_card[0] == %p base_e000_wrt == %p", language_card[0], base_e000_wrt);
|
|
|
|
RELEASE_BREAK();
|
|
|
|
}
|
|
|
|
|
|
|
|
saved = true;
|
|
|
|
} while (0);
|
|
|
|
|
|
|
|
return saved;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool vm_loadState(StateHelper_s *helper) {
|
|
|
|
bool loaded = false;
|
|
|
|
int fd = helper->fd;
|
|
|
|
|
|
|
|
do {
|
|
|
|
|
|
|
|
uint8_t serialized[4] = { 0 };
|
|
|
|
|
|
|
|
if (!helper->load(fd, serialized, sizeof(uint32_t))) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
softswitches = (uint32_t)(serialized[0] << 24);
|
|
|
|
softswitches |= (uint32_t)(serialized[1] << 16);
|
|
|
|
softswitches |= (uint32_t)(serialized[2] << 8);
|
|
|
|
softswitches |= (uint32_t)(serialized[3] << 0);
|
|
|
|
LOG("LOAD softswitches = %08x", softswitches);
|
|
|
|
|
|
|
|
// load main/aux memory state
|
|
|
|
if (!helper->load(fd, apple_ii_64k[0], sizeof(apple_ii_64k))) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
// load language card
|
|
|
|
if (!helper->load(fd, language_card[0], sizeof(language_card))) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
// load language banks
|
|
|
|
if (!helper->load(fd, language_banks[0], sizeof(language_banks))) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
// load offsets
|
|
|
|
uint8_t state = 0x0;
|
|
|
|
if (!helper->load(fd, &state, 1)) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
LOG("LOAD base_ramrd = %d", state);
|
|
|
|
base_ramrd = state == 0x0 ? apple_ii_64k[0] : apple_ii_64k[1];
|
|
|
|
|
|
|
|
if (!helper->load(fd, &state, 1)) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
LOG("LOAD base_ramwrt = %d", state);
|
|
|
|
base_ramwrt = state == 0x0 ? apple_ii_64k[0] : apple_ii_64k[1];
|
|
|
|
|
|
|
|
if (!helper->load(fd, &state, 1)) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
LOG("LOAD base_textrd = %d", state);
|
|
|
|
base_textrd = state == 0x0 ? apple_ii_64k[0] : apple_ii_64k[1];
|
|
|
|
|
|
|
|
if (!helper->load(fd, &state, 1)) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
LOG("LOAD base_textwrt = %d", state);
|
|
|
|
base_textwrt = state == 0x0 ? apple_ii_64k[0] : apple_ii_64k[1];
|
|
|
|
|
|
|
|
if (!helper->load(fd, &state, 1)) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
LOG("LOAD base_hgrrd = %d", state);
|
|
|
|
base_hgrrd = state == 0x0 ? apple_ii_64k[0] : apple_ii_64k[1];
|
|
|
|
|
|
|
|
if (!helper->load(fd, &state, 1)) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
LOG("LOAD base_hgrwrt = %d", state);
|
|
|
|
base_hgrwrt = state == 0x0 ? apple_ii_64k[0] : apple_ii_64k[1];
|
|
|
|
|
|
|
|
if (!helper->load(fd, &state, 1)) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
LOG("LOAD base_stackzp = %d", state);
|
|
|
|
base_stackzp = state == 0x0 ? apple_ii_64k[0] : apple_ii_64k[1];
|
|
|
|
|
|
|
|
if (!helper->load(fd, &state, 1)) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
LOG("LOAD base_c3rom = %d", state);
|
|
|
|
base_c3rom = state == 0x0 ? apple_ii_64k[0] : apple_ii_64k[1];
|
|
|
|
|
|
|
|
if (!helper->load(fd, &state, 1)) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
LOG("LOAD base_cxrom = %d", state);
|
|
|
|
if (state == 0) {
|
|
|
|
base_cxrom = apple_ii_64k[0];
|
|
|
|
#ifdef AUDIO_ENABLED
|
|
|
|
extern VMFunc MB_Read;
|
|
|
|
base_c4rom = (void *)MB_Read;
|
|
|
|
base_c5rom = (void *)MB_Read;
|
|
|
|
#else
|
|
|
|
base_c4rom = (void *)ram_nop;
|
|
|
|
base_c5rom = (void *)ram_nop;
|
|
|
|
#endif
|
|
|
|
} else {
|
|
|
|
base_cxrom = apple_ii_64k[1];
|
|
|
|
base_c4rom = apple_ii_64k[1];
|
|
|
|
base_c5rom = apple_ii_64k[1];
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!helper->load(fd, &state, 1)) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
switch (state) {
|
|
|
|
case 0:
|
|
|
|
base_d000_rd = apple_ii_64k[0];
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
base_d000_rd = language_banks[0] - 0xD000;
|
|
|
|
break;
|
|
|
|
case 3:
|
|
|
|
base_d000_rd = language_banks[0] - 0xC000;
|
|
|
|
break;
|
|
|
|
case 4:
|
|
|
|
base_d000_rd = language_banks[1] - 0xD000;
|
|
|
|
break;
|
|
|
|
case 5:
|
|
|
|
base_d000_rd = language_banks[1] - 0xC000;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
LOG("Unknown state base_d000_rd %02x", state);
|
|
|
|
RELEASE_BREAK();
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
LOG("LOAD base_d000_rd = %d", state);
|
|
|
|
|
|
|
|
if (!helper->load(fd, &state, 1)) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
switch (state) {
|
|
|
|
case 0:
|
|
|
|
base_d000_wrt = 0;
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
base_d000_wrt = language_banks[0] - 0xD000;
|
|
|
|
break;
|
|
|
|
case 3:
|
|
|
|
base_d000_wrt = language_banks[0] - 0xC000;
|
|
|
|
break;
|
|
|
|
case 4:
|
|
|
|
base_d000_wrt = language_banks[1] - 0xD000;
|
|
|
|
break;
|
|
|
|
case 5:
|
|
|
|
base_d000_wrt = language_banks[1] - 0xC000;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
LOG("Unknown state base_d000_wrt %02x", state);
|
|
|
|
RELEASE_BREAK();
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
LOG("LOAD base_d000_wrt = %d", state);
|
|
|
|
|
|
|
|
if (!helper->load(fd, &state, 1)) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
switch (state) {
|
|
|
|
case 0:
|
|
|
|
base_e000_rd = apple_ii_64k[0];
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
base_e000_rd = language_card[0] - 0xE000;
|
|
|
|
break;
|
|
|
|
case 3:
|
|
|
|
base_e000_rd = language_card[0] - 0xC000;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
LOG("Unknown state base_e000_rd %02x", state);
|
|
|
|
RELEASE_BREAK();
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
LOG("LOAD base_e000_rd = %d", state);
|
|
|
|
|
|
|
|
if (!helper->load(fd, &state, 1)) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
switch (state) {
|
|
|
|
case 0:
|
|
|
|
base_e000_wrt = 0;
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
base_e000_wrt = language_card[0] - 0xE000;
|
|
|
|
break;
|
|
|
|
case 3:
|
|
|
|
base_e000_wrt = language_card[0] - 0xC000;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
LOG("Unknown state base_e000_wrt %02x", state);
|
|
|
|
RELEASE_BREAK();
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
LOG("LOAD base_e000_wrt = %d", state);
|
|
|
|
|
|
|
|
loaded = true;
|
|
|
|
} while (0);
|
|
|
|
|
|
|
|
return loaded;
|
|
|
|
}
|
|
|
|
|
2014-11-23 20:53:59 +00:00
|
|
|
void debug_print_softwitches(void) {
|
|
|
|
// useful from GDB ...
|
|
|
|
|
|
|
|
fprintf(stderr, "STANDARD: ");
|
|
|
|
if (softswitches & SS_TEXT) {
|
|
|
|
fprintf(stderr, "SS_TEXT ");
|
|
|
|
}
|
|
|
|
if (softswitches & SS_MIXED) {
|
|
|
|
fprintf(stderr, "SS_MIXED ");
|
|
|
|
}
|
|
|
|
if (softswitches & SS_HIRES) {
|
|
|
|
fprintf(stderr, "SS_HIRES ");
|
|
|
|
}
|
|
|
|
if (softswitches & SS_PAGE2) {
|
|
|
|
fprintf(stderr, "SS_PAGE2 ");
|
|
|
|
}
|
|
|
|
if (softswitches & SS_BANK2) {
|
|
|
|
fprintf(stderr, "SS_BANK2 ");
|
|
|
|
}
|
|
|
|
if (softswitches & SS_LCRAM) {
|
|
|
|
fprintf(stderr, "SS_LCRAM ");
|
|
|
|
}
|
|
|
|
if (softswitches & SS_80STORE) {
|
|
|
|
fprintf(stderr, "SS_80STORE ");
|
|
|
|
}
|
|
|
|
if (softswitches & SS_80COL) {
|
|
|
|
fprintf(stderr, "SS_80COL ");
|
|
|
|
}
|
|
|
|
if (softswitches & SS_RAMRD) {
|
|
|
|
fprintf(stderr, "SS_RAMRD ");
|
|
|
|
}
|
|
|
|
if (softswitches & SS_RAMWRT) {
|
|
|
|
fprintf(stderr, "SS_RAMWRT ");
|
|
|
|
}
|
|
|
|
if (softswitches & SS_ALTZP) {
|
|
|
|
fprintf(stderr, "SS_ALTZP ");
|
|
|
|
}
|
|
|
|
if (softswitches & SS_DHIRES) {
|
|
|
|
fprintf(stderr, "SS_DHIRES ");
|
|
|
|
}
|
|
|
|
if (softswitches & SS_IOUDIS) {
|
|
|
|
fprintf(stderr, "SS_IOUDIS ");
|
|
|
|
}
|
|
|
|
if (softswitches & SS_CXROM) {
|
|
|
|
fprintf(stderr, "SS_CXROM ");
|
|
|
|
}
|
|
|
|
if (softswitches & SS_C3ROM) {
|
|
|
|
fprintf(stderr, "SS_C3ROM ");
|
|
|
|
}
|
|
|
|
if (softswitches & SS_ALTCHAR) {
|
|
|
|
fprintf(stderr, "SS_ALTCHAR ");
|
|
|
|
}
|
|
|
|
fprintf(stderr, "\n");
|
|
|
|
|
|
|
|
// pseudo #1
|
|
|
|
fprintf(stderr, "PSEUDO 1: ");
|
|
|
|
if (softswitches & SS_LCSEC) {
|
|
|
|
fprintf(stderr, "SS_LCSEC ");
|
|
|
|
}
|
|
|
|
if (softswitches & SS_LCWRT) {
|
|
|
|
fprintf(stderr, "SS_LCWRT ");
|
|
|
|
}
|
|
|
|
fprintf(stderr, "\n");
|
|
|
|
|
|
|
|
// pseudo #2
|
|
|
|
fprintf(stderr, "PSEUDO 2: ");
|
|
|
|
if (softswitches & SS_SCREEN) {
|
|
|
|
fprintf(stderr, "SS_SCREEN ");
|
|
|
|
}
|
|
|
|
if (softswitches & SS_TEXTRD) {
|
|
|
|
fprintf(stderr, "SS_TEXTRD ");
|
|
|
|
}
|
|
|
|
if (softswitches & SS_TEXTWRT) {
|
|
|
|
fprintf(stderr, "SS_TEXTWRT ");
|
|
|
|
}
|
|
|
|
if (softswitches & SS_HGRRD) {
|
|
|
|
fprintf(stderr, "SS_HGRRD ");
|
|
|
|
}
|
|
|
|
if (softswitches & SS_HGRWRT) {
|
|
|
|
fprintf(stderr, "SS_HGRWRT ");
|
|
|
|
}
|
|
|
|
|
|
|
|
fprintf(stderr, "\n");
|
|
|
|
}
|
2014-11-23 22:03:18 +00:00
|
|
|
|
|
|
|
#if VM_TRACING
|
2014-11-23 22:28:00 +00:00
|
|
|
void vm_trace_begin(const char *vm_file) {
|
2014-11-23 22:03:18 +00:00
|
|
|
if (vm_file) {
|
|
|
|
if (test_vm_fp) {
|
2014-11-23 22:28:00 +00:00
|
|
|
vm_trace_end();
|
2014-11-23 22:03:18 +00:00
|
|
|
}
|
|
|
|
test_vm_fp = fopen(vm_file, "w");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-11-23 22:28:00 +00:00
|
|
|
void vm_trace_end(void) {
|
2014-11-23 22:03:18 +00:00
|
|
|
if (test_vm_fp) {
|
|
|
|
fflush(test_vm_fp);
|
|
|
|
fclose(test_vm_fp);
|
|
|
|
test_vm_fp = NULL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-11-23 22:28:00 +00:00
|
|
|
void vm_trace_toggle(const char *vm_file) {
|
2014-11-23 22:03:18 +00:00
|
|
|
if (test_vm_fp) {
|
2014-11-23 22:28:00 +00:00
|
|
|
vm_trace_end();
|
2014-11-23 22:03:18 +00:00
|
|
|
} else {
|
2014-11-23 22:28:00 +00:00
|
|
|
vm_trace_begin(vm_file);
|
2014-11-23 22:03:18 +00:00
|
|
|
}
|
|
|
|
}
|
2014-11-23 22:28:00 +00:00
|
|
|
|
|
|
|
void vm_trace_ignore(vm_trace_range_t range) {
|
|
|
|
// TODO ...
|
|
|
|
}
|
|
|
|
|
|
|
|
bool vm_trace_is_ignored(uint16_t ea) {
|
|
|
|
if ((ea < 0xC000) || (ea > 0xCFFF)) {
|
|
|
|
return true;
|
|
|
|
}
|
2014-11-27 18:52:12 +00:00
|
|
|
return false;
|
2014-11-23 22:28:00 +00:00
|
|
|
}
|
|
|
|
|
2014-11-23 22:03:18 +00:00
|
|
|
#endif
|
|
|
|
|