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@ -100,7 +100,7 @@ extern int16_t cpu65_cycles_to_execute;
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#define N_Flag_Bit 15 /* 6502 Neg */
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/*
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* These are the 6502 Flags bit positions
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* 6502 flags bit mask
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*/
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#define C_Flag_6502 0x1 // [C]arry
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#define Z_Flag_6502 0x2 // [Z]ero
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@ -79,8 +79,8 @@ extern uint32_t softswitches;
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#define SS_PAGE2 0x00000008
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#define SS_BANK2 0x00000010
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#define SS_LCRAM 0x00000020
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#define SS_LCSEC 0x00000040 /* check for double read */
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#define SS_LCWRT 0x00000080 /* LC write enable */
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#define SS_LCSEC 0x00000040 /* Pseudo-softswitch : enabled if 2+ reads have occurred */
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#define SS_LCWRT 0x00000080 /* Pseudo-softswitch : LC write enable */
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#define SS_80STORE 0x00000100
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#define SS_80COL 0x00000200
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#define SS_RAMRD 0x00000400
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