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https://github.com/mauiaaron/apple2.git
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WARNING : changes test to accommodate CPU implementation
- TODO : check the Apple //e Bible for this ... - Calculates 2-byte branch instructions (Bxx +OFF)--that sit right at page boundary (at 0x..fe 0x..ff)--as 3 cycles rather than 4, since PC has already advanced to the new page (matches logic currently in x86/cpu.S
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15dd90902c
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@ -1137,15 +1137,14 @@ TEST test_BCC(int8_t off, bool flag, uint16_t addrs) {
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flags |= flag ? fC : 0;
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flags |= flag ? fC : 0;
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uint8_t cycle_count = 2;
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uint8_t cycle_count = 2;
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uint16_t newpc = 0xffff;
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uint16_t newpc = addrs+2;
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if (flag) {
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if (!flag) {
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newpc = addrs+2;
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uint16_t prebranch = newpc;
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} else {
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newpc += off;
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newpc = addrs+2+off;
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++cycle_count;
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++cycle_count;
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if ((newpc&0xFF00) != (addrs&0xFF00)) {
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if ((newpc&0xFF00) != (prebranch&0xFF00)) {
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++cycle_count;
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++cycle_count;
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}
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}
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}
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}
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apple_ii_64k[0][addrs+0] = 0x90;
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apple_ii_64k[0][addrs+0] = 0x90;
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@ -1183,13 +1182,12 @@ TEST test_BCS(int8_t off, bool flag, uint16_t addrs) {
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flags |= flag ? fC : 0;
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flags |= flag ? fC : 0;
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uint8_t cycle_count = 2;
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uint8_t cycle_count = 2;
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uint16_t newpc = 0xffff;
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uint16_t newpc = addrs+2;
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if (!flag) {
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if (flag) {
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newpc = addrs+2;
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uint16_t prebranch = newpc;
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} else {
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newpc += off;
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newpc = addrs+2+off;
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++cycle_count;
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++cycle_count;
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if ((newpc&0xFF00) != (addrs&0xFF00)) {
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if ((newpc&0xFF00) != (prebranch&0xFF00)) {
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++cycle_count;
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++cycle_count;
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}
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}
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}
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}
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@ -1229,13 +1227,12 @@ TEST test_BEQ(int8_t off, bool flag, uint16_t addrs) {
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flags |= flag ? fZ : 0;
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flags |= flag ? fZ : 0;
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uint8_t cycle_count = 2;
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uint8_t cycle_count = 2;
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uint16_t newpc = 0xffff;
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uint16_t newpc = addrs+2;
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if (!flag) {
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if (flag) {
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newpc = addrs+2;
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uint16_t prebranch = newpc;
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} else {
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newpc += off;
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newpc = addrs+2+off;
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++cycle_count;
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++cycle_count;
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if ((newpc&0xFF00) != (addrs&0xFF00)) {
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if ((newpc&0xFF00) != (prebranch&0xFF00)) {
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++cycle_count;
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++cycle_count;
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}
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}
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}
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}
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@ -1275,13 +1272,12 @@ TEST test_BNE(int8_t off, bool flag, uint16_t addrs) {
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flags |= flag ? fZ : 0;
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flags |= flag ? fZ : 0;
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uint8_t cycle_count = 2;
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uint8_t cycle_count = 2;
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uint16_t newpc = 0xffff;
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uint16_t newpc = addrs+2;
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if (flag) {
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if (!flag) {
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newpc = addrs+2;
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uint16_t prebranch = newpc;
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} else {
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newpc += off;
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newpc = addrs+2+off;
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++cycle_count;
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++cycle_count;
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if ((newpc&0xFF00) != (addrs&0xFF00)) {
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if ((newpc&0xFF00) != (prebranch&0xFF00)) {
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++cycle_count;
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++cycle_count;
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}
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}
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}
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}
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@ -1321,13 +1317,12 @@ TEST test_BMI(int8_t off, bool flag, uint16_t addrs) {
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flags |= flag ? fN : 0;
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flags |= flag ? fN : 0;
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uint8_t cycle_count = 2;
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uint8_t cycle_count = 2;
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uint16_t newpc = 0xffff;
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uint16_t newpc = addrs+2;
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if (!flag) {
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if (flag) {
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newpc = addrs+2;
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uint16_t prebranch = newpc;
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} else {
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newpc += off;
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newpc = addrs+2+off;
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++cycle_count;
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++cycle_count;
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if ((newpc&0xFF00) != (addrs&0xFF00)) {
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if ((newpc&0xFF00) != (prebranch&0xFF00)) {
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++cycle_count;
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++cycle_count;
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}
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}
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}
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}
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@ -1367,13 +1362,12 @@ TEST test_BPL(int8_t off, bool flag, uint16_t addrs) {
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flags |= flag ? fN : 0;
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flags |= flag ? fN : 0;
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uint8_t cycle_count = 2;
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uint8_t cycle_count = 2;
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uint16_t newpc = 0xffff;
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uint16_t newpc = addrs+2;
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if (flag) {
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if (!flag) {
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newpc = addrs+2;
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uint16_t prebranch = newpc;
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} else {
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newpc += off;
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newpc = addrs+2+off;
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++cycle_count;
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++cycle_count;
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if ((newpc&0xFF00) != (addrs&0xFF00)) {
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if ((newpc&0xFF00) != (prebranch&0xFF00)) {
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++cycle_count;
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++cycle_count;
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}
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}
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}
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}
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@ -1413,8 +1407,10 @@ TEST test_BRA(volatile int8_t off, volatile bool flag, volatile uint16_t addrs)
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flags |= flag ? fN : 0;
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flags |= flag ? fN : 0;
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uint8_t cycle_count = 3;
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uint8_t cycle_count = 3;
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uint16_t newpc = addrs+2+off;
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uint16_t newpc = addrs+2;
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if ((newpc&0xFF00) != (addrs&0xFF00)) {
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uint16_t prebranch = newpc;
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newpc += off;
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if ((newpc&0xFF00) != (prebranch&0xFF00)) {
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++cycle_count;
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++cycle_count;
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}
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}
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@ -1453,13 +1449,12 @@ TEST test_BVC(int8_t off, bool flag, uint16_t addrs) {
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flags |= flag ? fV : 0;
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flags |= flag ? fV : 0;
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uint8_t cycle_count = 2;
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uint8_t cycle_count = 2;
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uint16_t newpc = 0xffff;
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uint16_t newpc = addrs+2;
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if (flag) {
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if (!flag) {
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newpc = addrs+2;
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uint16_t prebranch = newpc;
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} else {
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newpc += off;
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newpc = addrs+2+off;
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++cycle_count;
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++cycle_count;
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if ((newpc&0xFF00) != (addrs&0xFF00)) {
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if ((newpc&0xFF00) != (prebranch&0xFF00)) {
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++cycle_count;
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++cycle_count;
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}
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}
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}
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}
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@ -1499,13 +1494,12 @@ TEST test_BVS(int8_t off, bool flag, uint16_t addrs) {
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flags |= flag ? fV : 0;
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flags |= flag ? fV : 0;
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uint8_t cycle_count = 2;
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uint8_t cycle_count = 2;
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uint16_t newpc = 0xffff;
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uint16_t newpc = addrs+2;
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if (!flag) {
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if (flag) {
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newpc = addrs+2;
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uint16_t prebranch = newpc;
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} else {
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newpc += off;
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newpc = addrs+2+off;
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++cycle_count;
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++cycle_count;
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if ((newpc&0xFF00) != (addrs&0xFF00)) {
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if ((newpc&0xFF00) != (prebranch&0xFF00)) {
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++cycle_count;
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++cycle_count;
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}
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}
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}
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}
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