953 lines
28 KiB
TypeScript
953 lines
28 KiB
TypeScript
import { CPU6502 } from '@whscullin/cpu6502';
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import RAM, { RAMState } from './ram';
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import ROM, { ROMState } from './roms/rom';
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import { debug } from './util';
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import { byte, Memory, Restorable } from './types';
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import Apple2IO from './apple2io';
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import { HiresPage, LoresPage, VideoModes } from './videomodes';
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/*
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* I/O Switch locations
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*/
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const LOC = {
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// 80 Column memory
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_80STOREOFF: 0x00,
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_80STOREON: 0x01,
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// Aux RAM
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RAMRDOFF: 0x02,
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RAMRDON: 0x03,
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RAMWROFF: 0x04,
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RAMWRON: 0x05,
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// Bank switched ROM
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INTCXROMOFF: 0x06,
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INTCXROMON: 0x07,
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ALTZPOFF: 0x08,
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ALTZPON: 0x09,
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SLOTC3ROMOFF: 0x0a,
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SLOTC3ROMON: 0x0b,
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// 80 Column video
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CLR80VID: 0x0c, // clear 80 column mode
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SET80VID: 0x0d, // set 80 column mode
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CLRALTCH: 0x0e, // clear mousetext
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SETALTCH: 0x0f, // set mousetext
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// Status
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BSRBANK2: 0x11,
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BSRREADRAM: 0x12,
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RAMRD: 0x13,
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RAMWRT: 0x14,
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INTCXROM: 0x15,
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ALTZP: 0x16,
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SLOTC3ROM: 0x17,
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_80STORE: 0x18,
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VERTBLANK: 0x19,
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RDTEXT: 0x1a, // using text mode
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RDMIXED: 0x1b, // using mixed mode
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RDPAGE2: 0x1c, // using text/graphics page2
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RDHIRES: 0x1d, // using Hi-res graphics mode
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RDALTCH: 0x1e, // using alternate character set
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RD80VID: 0x1f, // using 80-column display mode
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// Graphics
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PAGE1: 0x54, // select text/graphics page1 main/aux
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PAGE2: 0x55, // select text/graphics page2 main/aux
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RESET_HIRES: 0x56,
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SET_HIRES: 0x57,
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DHIRESON: 0x5e, // Enable double hires (CLRAN3)
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DHIRESOFF: 0x5f, // Disable double hires (SETAN3)
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// Misc
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BANK: 0x73, // Back switched RAM card bank
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IOUDISON: 0x7e, // W IOU Disable on / R7 IOU Disable
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IOUDISOFF: 0x7f, // W IOU Disable off / R7 Double Hires
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// Language Card
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// Bank 2
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READBSR2: 0x80,
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WRITEBSR2: 0x81,
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OFFBSR2: 0x82,
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READWRBSR2: 0x83,
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// Bank 1
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READBSR1: 0x88,
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WRITEBSR1: 0x89,
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OFFBSR1: 0x8a,
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READWRBSR1: 0x8b,
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};
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class Switches implements Memory {
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constructor(private mmu: MMU) {}
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read(_page: byte, off: byte) {
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return this.mmu._access(off) || 0;
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}
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write(_page: byte, off: byte, val: byte) {
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this.mmu._access(off, val);
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}
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}
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class AuxRom implements Memory {
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constructor(
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private readonly mmu: MMU,
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private readonly rom: ROM
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) {}
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_access(page: byte, off: byte) {
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if (page === 0xc3) {
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this.mmu._setIntc8rom(true);
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this.mmu._updateBanks();
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}
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if (page === 0xcf && off === 0xff) {
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this.mmu._setIntc8rom(false);
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this.mmu._updateBanks();
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}
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}
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read(page: byte, off: byte) {
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this._access(page, off);
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return this.rom.read(page, off);
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}
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write(page: byte, off: byte, _val: byte) {
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this._access(page, off);
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}
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}
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export interface MMUState {
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bank1: boolean;
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readbsr: boolean;
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writebsr: boolean;
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prewrite: boolean;
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intcxrom: boolean;
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slot3rom: boolean;
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intc8rom: boolean;
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auxRamRead: boolean;
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auxRamWrite: boolean;
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altzp: boolean;
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_80store: boolean;
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page2: boolean;
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hires: boolean;
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mem00_01: [RAMState, RAMState];
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mem02_03: [RAMState, RAMState];
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mem0C_1F: [RAMState, RAMState];
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mem60_BF: [RAMState, RAMState];
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memD0_DF: [ROMState, RAMState, RAMState, RAMState, RAMState];
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memE0_FF: [ROMState, RAMState, RAMState];
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}
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export default class MMU implements Memory, Restorable<MMUState> {
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private _readPages = new Array<Memory>(0x100);
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private _writePages = new Array<Memory>(0x100);
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private _pages = new Array<Memory[]>(0x100);
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// Language Card RAM Softswitches
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private _bank1: boolean;
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private _readbsr: boolean;
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private _writebsr: boolean;
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private _prewrite: boolean;
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// Auxillary ROM
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private _intcxrom: boolean;
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private _slot3rom: boolean;
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private _intc8rom: boolean;
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// Auxillary RAM
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private _auxRamRead: boolean;
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private _auxRamWrite: boolean;
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private _altzp: boolean;
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// Video
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private __80store: boolean;
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private _page2: boolean;
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private _hires: boolean;
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private _iouDisable: boolean;
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private _vbEnd = 0;
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private switches = new Switches(this);
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private auxRom = new AuxRom(this, this.rom);
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// These fields represent the bank-switched memory ranges.
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private mem00_01 = [new RAM(0x0, 0x1), new RAM(0x0, 0x1)];
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private mem02_03 = [new RAM(0x2, 0x3), new RAM(0x2, 0x3)];
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private mem04_07 = [this.lores1.bank0(), this.lores1.bank1()];
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private mem08_0B = [this.lores2.bank0(), this.lores2.bank1()];
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private mem0C_1F = [new RAM(0xc, 0x1f), new RAM(0xc, 0x1f)];
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private mem20_3F = [this.hires1.bank0(), this.hires1.bank1()];
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private mem40_5F = [this.hires2.bank0(), this.hires2.bank1()];
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private mem60_BF = [new RAM(0x60, 0xbf), new RAM(0x60, 0xbf)];
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private memC0_C0 = [this.switches];
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private memC1_CF = [this.io, this.auxRom];
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private memD0_DF: [ROM, RAM, RAM, RAM, RAM] = [
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this.rom,
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new RAM(0xd0, 0xdf),
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new RAM(0xd0, 0xdf),
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new RAM(0xd0, 0xdf),
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new RAM(0xd0, 0xdf),
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];
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private memE0_FF: [ROM, RAM, RAM] = [
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this.rom,
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new RAM(0xe0, 0xff),
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new RAM(0xe0, 0xff),
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];
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constructor(
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private readonly cpu: CPU6502,
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private readonly vm: VideoModes,
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private readonly lores1: LoresPage,
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private readonly lores2: LoresPage,
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private readonly hires1: HiresPage,
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private readonly hires2: HiresPage,
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private readonly io: Apple2IO,
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private readonly rom: ROM
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) {
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/*
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* Initialize read/write banks
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*/
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// Zero Page/Stack
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for (let idx = 0x0; idx < 0x2; idx++) {
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this._pages[idx] = this.mem00_01;
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this._readPages[idx] = this._pages[idx][0];
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this._writePages[idx] = this._pages[idx][0];
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}
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// 0x300-0x400
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for (let idx = 0x2; idx < 0x4; idx++) {
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this._pages[idx] = this.mem02_03;
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this._readPages[idx] = this._pages[idx][0];
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this._writePages[idx] = this._pages[idx][0];
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}
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// Text Page 1
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for (let idx = 0x4; idx < 0x8; idx++) {
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this._pages[idx] = this.mem04_07;
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this._readPages[idx] = this._pages[idx][0];
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this._writePages[idx] = this._pages[idx][0];
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}
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// Text Page 2
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for (let idx = 0x8; idx < 0xc; idx++) {
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this._pages[idx] = this.mem08_0B;
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this._readPages[idx] = this._pages[idx][0];
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this._writePages[idx] = this._pages[idx][0];
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}
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// 0xC00-0x2000
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for (let idx = 0xc; idx < 0x20; idx++) {
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this._pages[idx] = this.mem0C_1F;
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this._readPages[idx] = this._pages[idx][0];
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this._writePages[idx] = this._pages[idx][0];
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}
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// Hires Page 1
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for (let idx = 0x20; idx < 0x40; idx++) {
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this._pages[idx] = this.mem20_3F;
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this._readPages[idx] = this._pages[idx][0];
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this._writePages[idx] = this._pages[idx][0];
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}
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// Hires Page 2
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for (let idx = 0x40; idx < 0x60; idx++) {
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this._pages[idx] = this.mem40_5F;
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this._readPages[idx] = this._pages[idx][0];
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this._writePages[idx] = this._pages[idx][0];
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}
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// 0x6000-0xc000
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for (let idx = 0x60; idx < 0xc0; idx++) {
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this._pages[idx] = this.mem60_BF;
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this._readPages[idx] = this._pages[idx][0];
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this._writePages[idx] = this._pages[idx][0];
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}
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// I/O Switches
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{
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const idx = 0xc0;
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this._pages[idx] = this.memC0_C0;
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this._readPages[idx] = this._pages[idx][0];
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this._writePages[idx] = this._pages[idx][0];
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}
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// Slots
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for (let idx = 0xc1; idx < 0xd0; idx++) {
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this._pages[idx] = this.memC1_CF;
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this._readPages[idx] = this._pages[idx][0];
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this._writePages[idx] = this._pages[idx][0];
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}
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// Basic ROM
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for (let idx = 0xd0; idx < 0xe0; idx++) {
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this._pages[idx] = this.memD0_DF;
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this._readPages[idx] = this._pages[idx][0];
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this._writePages[idx] = this._pages[idx][0];
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}
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// Monitor ROM
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for (let idx = 0xe0; idx < 0x100; idx++) {
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this._pages[idx] = this.memE0_FF;
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this._readPages[idx] = this._pages[idx][0];
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this._writePages[idx] = this._pages[idx][0];
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}
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}
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private _initSwitches() {
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this._bank1 = false;
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this._readbsr = false;
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this._writebsr = false;
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this._prewrite = false;
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this._auxRamRead = false;
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this._auxRamWrite = false;
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this._altzp = false;
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this._intcxrom = false;
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this._slot3rom = false;
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this._intc8rom = false;
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this.__80store = false;
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this._page2 = false;
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this._hires = false;
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this._iouDisable = true;
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}
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private _debug(..._args: unknown[]) {
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// debug.apply(this, _args);
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}
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_setIntc8rom(on: boolean) {
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this._intc8rom = on;
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}
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_updateBanks() {
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if (this._auxRamRead) {
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for (let idx = 0x02; idx < 0xc0; idx++) {
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this._readPages[idx] = this._pages[idx][1];
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}
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} else {
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for (let idx = 0x02; idx < 0xc0; idx++) {
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this._readPages[idx] = this._pages[idx][0];
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}
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}
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if (this._auxRamWrite) {
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for (let idx = 0x02; idx < 0xc0; idx++) {
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this._writePages[idx] = this._pages[idx][1];
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}
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} else {
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for (let idx = 0x02; idx < 0xc0; idx++) {
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this._writePages[idx] = this._pages[idx][0];
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}
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}
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if (this.__80store) {
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if (this._page2) {
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for (let idx = 0x4; idx < 0x8; idx++) {
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this._readPages[idx] = this._pages[idx][1];
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this._writePages[idx] = this._pages[idx][1];
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}
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if (this._hires) {
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for (let idx = 0x20; idx < 0x40; idx++) {
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this._readPages[idx] = this._pages[idx][1];
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this._writePages[idx] = this._pages[idx][1];
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}
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}
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} else {
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for (let idx = 0x4; idx < 0x8; idx++) {
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this._readPages[idx] = this._pages[idx][0];
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this._writePages[idx] = this._pages[idx][0];
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}
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if (this._hires) {
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for (let idx = 0x20; idx < 0x40; idx++) {
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this._readPages[idx] = this._pages[idx][0];
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this._writePages[idx] = this._pages[idx][0];
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}
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}
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}
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}
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if (this._intcxrom) {
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for (let idx = 0xc1; idx < 0xd0; idx++) {
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this._readPages[idx] = this._pages[idx][1];
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this._writePages[idx] = this._pages[idx][1];
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}
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} else {
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for (let idx = 0xc1; idx < 0xd0; idx++) {
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this._readPages[idx] = this._pages[idx][0];
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this._writePages[idx] = this._pages[idx][0];
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}
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if (!this._slot3rom) {
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this._readPages[0xc3] = this._pages[0xc3][1];
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this._writePages[0xc3] = this._pages[0xc3][1];
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}
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if (this._intc8rom) {
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for (let idx = 0xc8; idx < 0xd0; idx++) {
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this._readPages[idx] = this._pages[idx][1];
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this._writePages[idx] = this._pages[idx][1];
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}
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}
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}
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if (this._altzp) {
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for (let idx = 0x0; idx < 0x2; idx++) {
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this._readPages[idx] = this._pages[idx][1];
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this._writePages[idx] = this._pages[idx][1];
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}
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} else {
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for (let idx = 0x0; idx < 0x2; idx++) {
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this._readPages[idx] = this._pages[idx][0];
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this._writePages[idx] = this._pages[idx][0];
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}
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}
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if (this._readbsr) {
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if (this._bank1) {
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for (let idx = 0xd0; idx < 0xe0; idx++) {
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this._readPages[idx] =
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this._pages[idx][this._altzp ? 2 : 1];
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}
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} else {
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for (let idx = 0xd0; idx < 0xe0; idx++) {
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this._readPages[idx] =
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this._pages[idx][this._altzp ? 4 : 3];
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}
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}
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for (let idx = 0xe0; idx < 0x100; idx++) {
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this._readPages[idx] = this._pages[idx][this._altzp ? 2 : 1];
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}
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} else {
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for (let idx = 0xd0; idx < 0x100; idx++) {
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this._readPages[idx] = this._pages[idx][0];
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}
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}
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if (this._writebsr) {
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if (this._bank1) {
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for (let idx = 0xd0; idx < 0xe0; idx++) {
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this._writePages[idx] =
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this._pages[idx][this._altzp ? 2 : 1];
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}
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} else {
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for (let idx = 0xd0; idx < 0xe0; idx++) {
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this._writePages[idx] =
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this._pages[idx][this._altzp ? 4 : 3];
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}
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}
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for (let idx = 0xe0; idx < 0x100; idx++) {
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this._writePages[idx] = this._pages[idx][this._altzp ? 2 : 1];
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}
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} else {
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for (let idx = 0xd0; idx < 0x100; idx++) {
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this._writePages[idx] = this._pages[idx][0];
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}
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}
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}
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// Apple //e memory management
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private _accessMMUSet(off: byte, _val?: byte) {
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switch (off) {
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case LOC._80STOREOFF:
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this.__80store = false;
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this._debug('80 Store Off', _val);
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this.vm.page(this._page2 ? 2 : 1);
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break;
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case LOC._80STOREON:
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this.__80store = true;
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this._debug('80 Store On', _val);
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break;
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case LOC.RAMRDOFF:
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this._auxRamRead = false;
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this._debug('Aux RAM Read Off');
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break;
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case LOC.RAMRDON:
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this._auxRamRead = true;
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this._debug('Aux RAM Read On');
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break;
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case LOC.RAMWROFF:
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this._auxRamWrite = false;
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this._debug('Aux RAM Write Off');
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break;
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case LOC.RAMWRON:
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this._auxRamWrite = true;
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this._debug('Aux RAM Write On');
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break;
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case LOC.INTCXROMOFF:
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this._intcxrom = false;
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if (this._slot3rom) {
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this._intc8rom = false;
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}
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this._debug('Int CX ROM Off');
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break;
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case LOC.INTCXROMON:
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this._intcxrom = true;
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this._debug('Int CX ROM On');
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break;
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case LOC.ALTZPOFF: // 0x08
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this._altzp = false;
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this._debug('Alt ZP Off');
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break;
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case LOC.ALTZPON: // 0x09
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this._altzp = true;
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this._debug('Alt ZP On');
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break;
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case LOC.SLOTC3ROMOFF: // 0x0A
|
|
this._slot3rom = false;
|
|
this._debug('Slot 3 ROM Off');
|
|
break;
|
|
case LOC.SLOTC3ROMON: // 0x0B
|
|
this._slot3rom = true;
|
|
this._debug('Slot 3 ROM On');
|
|
break;
|
|
|
|
// Graphics Switches
|
|
|
|
case LOC.CLR80VID:
|
|
this._debug('80 Column Mode off');
|
|
this.vm._80col(false);
|
|
break;
|
|
case LOC.SET80VID:
|
|
this._debug('80 Column Mode on');
|
|
this.vm._80col(true);
|
|
break;
|
|
case LOC.CLRALTCH:
|
|
this._debug('Alt Char off');
|
|
this.vm.altChar(false);
|
|
break;
|
|
case LOC.SETALTCH:
|
|
this._debug('Alt Char on');
|
|
this.vm.altChar(true);
|
|
break;
|
|
}
|
|
this._updateBanks();
|
|
}
|
|
|
|
// Status registers
|
|
|
|
private _accessStatus(off: byte, val?: byte) {
|
|
let result = undefined;
|
|
|
|
switch (off) {
|
|
case LOC.BSRBANK2:
|
|
this._debug(`Bank 2 Read ${!this._bank1 ? 'true' : 'false'}`);
|
|
result = !this._bank1 ? 0x80 : 0x00;
|
|
break;
|
|
case LOC.BSRREADRAM:
|
|
this._debug(
|
|
`Bank SW RAM Read ${this._readbsr ? 'true' : 'false'}`
|
|
);
|
|
result = this._readbsr ? 0x80 : 0x00;
|
|
break;
|
|
case LOC.RAMRD: // 0xC013
|
|
this._debug(
|
|
`Aux RAM Read ${this._auxRamRead ? 'true' : 'false'}`
|
|
);
|
|
result = this._auxRamRead ? 0x80 : 0x0;
|
|
break;
|
|
case LOC.RAMWRT: // 0xC014
|
|
this._debug(
|
|
`Aux RAM Write ${this._auxRamWrite ? 'true' : 'false'}`
|
|
);
|
|
result = this._auxRamWrite ? 0x80 : 0x0;
|
|
break;
|
|
case LOC.INTCXROM: // 0xC015
|
|
// _debug('Int CX ROM ' + _intcxrom);
|
|
result = this._intcxrom ? 0x80 : 0x00;
|
|
break;
|
|
case LOC.ALTZP: // 0xC016
|
|
this._debug(`Alt ZP ${this._altzp ? 'true' : 'false'}`);
|
|
result = this._altzp ? 0x80 : 0x0;
|
|
break;
|
|
case LOC.SLOTC3ROM: // 0xC017
|
|
this._debug(`Slot C3 ROM ${this._slot3rom ? 'true' : 'false'}`);
|
|
result = this._slot3rom ? 0x80 : 0x00;
|
|
break;
|
|
case LOC._80STORE: // 0xC018
|
|
this._debug(`80 Store ${this.__80store ? 'true' : 'false'}`);
|
|
result = this.__80store ? 0x80 : 0x00;
|
|
break;
|
|
case LOC.VERTBLANK: // 0xC019
|
|
// result = cpu.getCycles() % 20 < 5 ? 0x80 : 0x00;
|
|
result = this.cpu.getCycles() < this._vbEnd ? 0x80 : 0x00;
|
|
break;
|
|
case LOC.RDTEXT:
|
|
result = this.vm.isText() ? 0x80 : 0x0;
|
|
break;
|
|
case LOC.RDMIXED:
|
|
result = this.vm.isMixed() ? 0x80 : 0x0;
|
|
break;
|
|
case LOC.RDPAGE2:
|
|
result = this._page2 ? 0x80 : 0x0;
|
|
break;
|
|
case LOC.RDHIRES:
|
|
result = this.vm.isHires() ? 0x80 : 0x0;
|
|
break;
|
|
case LOC.RD80VID:
|
|
result = this.vm.is80Col() ? 0x80 : 0x0;
|
|
break;
|
|
case LOC.RDALTCH:
|
|
result = this.vm.isAltChar() ? 0x80 : 0x0;
|
|
break;
|
|
default:
|
|
result = this.io.ioSwitch(off, val);
|
|
}
|
|
|
|
return result;
|
|
}
|
|
|
|
private _accessIOUDisable(off: byte, val?: byte) {
|
|
const writeMode = val !== undefined;
|
|
let result;
|
|
|
|
switch (off) {
|
|
case LOC.IOUDISON:
|
|
if (writeMode) {
|
|
this._iouDisable = true;
|
|
} else {
|
|
result = this._iouDisable ? 0x00 : 0x80;
|
|
}
|
|
break;
|
|
|
|
case LOC.IOUDISOFF:
|
|
if (writeMode) {
|
|
this._iouDisable = false;
|
|
} else {
|
|
result = this.vm.isDoubleHires() ? 0x80 : 0x00;
|
|
}
|
|
break;
|
|
|
|
default:
|
|
result = this.io.ioSwitch(off, val);
|
|
}
|
|
|
|
return result;
|
|
}
|
|
|
|
private _accessGraphics(off: byte, val?: byte) {
|
|
let result: byte | undefined = 0;
|
|
|
|
switch (off) {
|
|
case LOC.PAGE1:
|
|
this._page2 = false;
|
|
if (!this.__80store) {
|
|
result = this.io.ioSwitch(off, val);
|
|
}
|
|
this._debug('Page 2 off');
|
|
break;
|
|
|
|
case LOC.PAGE2:
|
|
this._page2 = true;
|
|
if (!this.__80store) {
|
|
result = this.io.ioSwitch(off, val);
|
|
}
|
|
this._debug('Page 2 on');
|
|
break;
|
|
|
|
case LOC.RESET_HIRES:
|
|
this._hires = false;
|
|
result = this.io.ioSwitch(off, val);
|
|
this._debug('Hires off');
|
|
break;
|
|
|
|
case LOC.DHIRESON:
|
|
if (this._iouDisable) {
|
|
this.vm.doubleHires(true);
|
|
} else {
|
|
result = this.io.ioSwitch(off, val); // an3
|
|
}
|
|
break;
|
|
|
|
case LOC.DHIRESOFF:
|
|
if (this._iouDisable) {
|
|
this.vm.doubleHires(false);
|
|
} else {
|
|
result = this.io.ioSwitch(off, val); // an3
|
|
}
|
|
break;
|
|
|
|
case LOC.SET_HIRES:
|
|
this._hires = true;
|
|
result = this.io.ioSwitch(off, val);
|
|
this._debug('Hires on');
|
|
break;
|
|
|
|
default:
|
|
result = this.io.ioSwitch(off, val);
|
|
break;
|
|
}
|
|
this._updateBanks();
|
|
|
|
return result;
|
|
}
|
|
|
|
private _accessLangCard(off: byte, val?: byte) {
|
|
const readMode = val === undefined;
|
|
const result = readMode ? 0 : undefined;
|
|
|
|
const writeSwitch = off & 0x01;
|
|
const offSwitch = off & 0x02;
|
|
const bank1Switch = off & 0x08;
|
|
|
|
let bankStr;
|
|
let rwStr;
|
|
|
|
if (writeSwitch) {
|
|
// 0xC081, 0xC083
|
|
if (readMode) {
|
|
if (this._prewrite) {
|
|
this._writebsr = true;
|
|
}
|
|
}
|
|
this._prewrite = readMode;
|
|
|
|
if (offSwitch) {
|
|
// 0xC08B
|
|
this._readbsr = true;
|
|
rwStr = 'Read/Write';
|
|
} else {
|
|
this._readbsr = false;
|
|
rwStr = 'Write';
|
|
}
|
|
} else {
|
|
// 0xC080, 0xC082
|
|
this._writebsr = false;
|
|
this._prewrite = false;
|
|
|
|
if (offSwitch) {
|
|
// 0xC082
|
|
this._readbsr = false;
|
|
rwStr = 'Off';
|
|
} else {
|
|
// 0xC080
|
|
this._readbsr = true;
|
|
rwStr = 'Read';
|
|
}
|
|
}
|
|
|
|
if (bank1Switch) {
|
|
this._bank1 = true;
|
|
bankStr = 'Bank 1';
|
|
} else {
|
|
this._bank1 = false;
|
|
bankStr = 'Bank 2';
|
|
}
|
|
|
|
this._debug(bankStr, rwStr);
|
|
this._updateBanks();
|
|
|
|
return result;
|
|
}
|
|
|
|
/*
|
|
* The Big Switch
|
|
*/
|
|
|
|
_access(off: byte, val?: byte) {
|
|
let result;
|
|
const writeMode = val !== undefined;
|
|
const highNibble = off >> 4;
|
|
|
|
switch (highNibble) {
|
|
case 0x0:
|
|
if (writeMode) {
|
|
this._accessMMUSet(off, val);
|
|
} else {
|
|
result = this.io.ioSwitch(off);
|
|
}
|
|
break;
|
|
|
|
case 0x1:
|
|
if (writeMode) {
|
|
this.io.ioSwitch(off, val);
|
|
} else {
|
|
result = this._accessStatus(off, val);
|
|
}
|
|
break;
|
|
|
|
case 0x5:
|
|
result = this._accessGraphics(off, val);
|
|
break;
|
|
|
|
case 0x7:
|
|
result = this._accessIOUDisable(off, val);
|
|
break;
|
|
|
|
case 0x8:
|
|
result = this._accessLangCard(off, val);
|
|
break;
|
|
|
|
default:
|
|
result = this.io.ioSwitch(off, val);
|
|
}
|
|
|
|
return result;
|
|
}
|
|
|
|
public start() {
|
|
this.lores1.start();
|
|
this.lores2.start();
|
|
return 0x00;
|
|
}
|
|
|
|
public end() {
|
|
return 0xff;
|
|
}
|
|
|
|
public reset() {
|
|
debug('reset');
|
|
this._initSwitches();
|
|
this._updateBanks();
|
|
this.vm.reset();
|
|
this.io.reset();
|
|
}
|
|
|
|
public read(page: byte, off: byte) {
|
|
return this._readPages[page].read(page, off);
|
|
}
|
|
|
|
public write(page: byte, off: byte, val: byte) {
|
|
this._writePages[page].write(page, off, val);
|
|
}
|
|
|
|
public writeBank(bank: number, page: byte, off: byte, val: byte) {
|
|
this._pages[page][bank].write(page, off, val);
|
|
}
|
|
|
|
public resetVB() {
|
|
this._vbEnd = this.cpu.getCycles() + 1000;
|
|
}
|
|
|
|
public get bank1() {
|
|
return this._bank1;
|
|
}
|
|
|
|
public get readbsr() {
|
|
return this._readbsr;
|
|
}
|
|
|
|
public get writebsr() {
|
|
return this._writebsr;
|
|
}
|
|
|
|
public get auxread() {
|
|
return this._auxRamRead;
|
|
}
|
|
|
|
public get auxwrite() {
|
|
return this._auxRamWrite;
|
|
}
|
|
|
|
public get altzp() {
|
|
return this._altzp;
|
|
}
|
|
|
|
public get _80store() {
|
|
return this.__80store;
|
|
}
|
|
|
|
public get page2() {
|
|
return this._page2;
|
|
}
|
|
|
|
public get hires() {
|
|
return this._hires;
|
|
}
|
|
|
|
public get intcxrom() {
|
|
return this._intcxrom;
|
|
}
|
|
|
|
public getState(): MMUState {
|
|
return {
|
|
bank1: this._bank1,
|
|
readbsr: this._readbsr,
|
|
writebsr: this._writebsr,
|
|
prewrite: this._prewrite,
|
|
|
|
intcxrom: this._intcxrom,
|
|
slot3rom: this._slot3rom,
|
|
intc8rom: this._intc8rom,
|
|
|
|
auxRamRead: this._auxRamRead,
|
|
auxRamWrite: this._auxRamWrite,
|
|
altzp: this._altzp,
|
|
|
|
_80store: this.__80store,
|
|
page2: this._page2,
|
|
hires: this._hires,
|
|
|
|
mem00_01: [
|
|
this.mem00_01[0].getState(),
|
|
this.mem00_01[1].getState(),
|
|
],
|
|
mem02_03: [
|
|
this.mem02_03[0].getState(),
|
|
this.mem02_03[1].getState(),
|
|
],
|
|
mem0C_1F: [
|
|
this.mem0C_1F[0].getState(),
|
|
this.mem0C_1F[1].getState(),
|
|
],
|
|
mem60_BF: [
|
|
this.mem60_BF[0].getState(),
|
|
this.mem60_BF[1].getState(),
|
|
],
|
|
memD0_DF: [
|
|
this.memD0_DF[0].getState(),
|
|
this.memD0_DF[1].getState(),
|
|
this.memD0_DF[2].getState(),
|
|
this.memD0_DF[3].getState(),
|
|
this.memD0_DF[4].getState(),
|
|
],
|
|
memE0_FF: [
|
|
this.memE0_FF[0].getState(),
|
|
this.memE0_FF[1].getState(),
|
|
this.memE0_FF[2].getState(),
|
|
],
|
|
};
|
|
}
|
|
|
|
public setState(state: MMUState) {
|
|
this._readbsr = state.readbsr;
|
|
this._writebsr = state.writebsr;
|
|
this._bank1 = state.bank1;
|
|
this._prewrite = state.prewrite;
|
|
|
|
this._intcxrom = state.intcxrom;
|
|
this._slot3rom = state.slot3rom;
|
|
this._intc8rom = state.intc8rom;
|
|
|
|
this._auxRamRead = state.auxRamRead;
|
|
this._auxRamWrite = state.auxRamWrite;
|
|
this._altzp = state.altzp;
|
|
|
|
this.__80store = state._80store;
|
|
this._page2 = state.page2;
|
|
this._hires = state.hires;
|
|
|
|
this.mem00_01[0].setState(state.mem00_01[0]);
|
|
this.mem00_01[1].setState(state.mem00_01[1]);
|
|
this.mem02_03[0].setState(state.mem02_03[0]);
|
|
this.mem02_03[1].setState(state.mem02_03[1]);
|
|
this.mem0C_1F[0].setState(state.mem0C_1F[0]);
|
|
this.mem0C_1F[1].setState(state.mem0C_1F[1]);
|
|
this.mem60_BF[0].setState(state.mem60_BF[0]);
|
|
this.mem60_BF[1].setState(state.mem60_BF[1]);
|
|
this.memD0_DF[0].setState(state.memD0_DF[0]);
|
|
this.memD0_DF[1].setState(state.memD0_DF[1]);
|
|
this.memD0_DF[2].setState(state.memD0_DF[2]);
|
|
this.memD0_DF[3].setState(state.memD0_DF[3]);
|
|
this.memD0_DF[4].setState(state.memD0_DF[4]);
|
|
this.memE0_FF[0].setState(state.memE0_FF[0]);
|
|
this.memE0_FF[1].setState(state.memE0_FF[1]);
|
|
this.memE0_FF[2].setState(state.memE0_FF[2]);
|
|
|
|
this._updateBanks();
|
|
}
|
|
}
|