mirror of
https://github.com/whscullin/apple2js.git
synced 2024-01-12 14:14:38 +00:00
* Convert js/ram to a class * Convert js/mmu to Typescript * Convert js/apple2io to Typescript * Convert js/canvas to Typescript * Use new types in js/mmu * Rename js/symbols.js to js/symbols.ts * Remove the difference between readPages and writePages As @whscullin said in PR #38, there's no need to have both readable and writable pages since all implementations are currently both. This change combines them into `Page`. Likewise, `PageHandler` now extends `Page`. `Apple2IO` now implements `PageHandler`. This caught a bug where `end` had been renamed `endend` by mistake. There are a few other formatting changes as well. * Convert js/apple2 to Typescript * Convert js/prefs to Typescript * Convert all of the ROMs in js/roms to Typescript Now all of the ROMs are classes that extend the ROM class. There is some rudamentary checking to make sure that the length of the ROM matches the declared start and end pages. (This caught what looks to be an error in roms/apple2e, but it's hard for me to tell.) The typing also caught an error where the character ROM was being used for the main ROM for the apple2j version. * Convert js/roms/cards/* to Typescript * Convert js/formats/format_utils to Typescript This change also seems to fix a bug with `.po` image files that weren't being read correctly.
895 lines
28 KiB
TypeScript
895 lines
28 KiB
TypeScript
/* Copyright 2010-2019 Will Scullin <scullin@scullinsteel.com>
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*
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* Permission to use, copy, modify, distribute, and sell this software and its
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* documentation for any purpose is hereby granted without fee, provided that
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* the above copyright notice appear in all copies and that both that
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* copyright notice and this permission notice appear in supporting
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* documentation. No representations are made about the suitability of this
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* software for any purpose. It is provided "as is" without express or
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* implied warranty.
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*/
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import CPU6502 from './cpu6502';
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import RAM from './ram';
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import { debug, toHex } from './util';
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import { byte, Memory } from './types';
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import Apple2IO from './apple2io';
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import { HiresPage, LoresPage, VideoModes } from './canvas';
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/*
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* I/O Switch locations
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*/
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const LOC = {
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// 80 Column
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_80STOREOFF: 0x00,
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_80STOREON: 0x01,
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// Aux RAM
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RAMRDOFF: 0x02,
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RAMRDON: 0x03,
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RAMWROFF: 0x04,
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RAMWRON: 0x05,
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// Bank switched ROM
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INTCXROMOFF: 0x06,
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INTCXROMON: 0x07,
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ALTZPOFF: 0x08,
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ALTZPON: 0x09,
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SLOTC3ROMOFF: 0x0A,
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SLOTC3ROMON: 0x0B,
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CLR80VID: 0x0C, // clear 80 column mode
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SET80VID: 0x0D, // set 80 column mode
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CLRALTCH: 0x0E, // clear mousetext
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SETALTCH: 0x0F, // set mousetext
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// Status
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BSRBANK2: 0x11,
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BSRREADRAM: 0x12,
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RAMRD: 0x13,
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RAMWRT: 0x14,
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INTCXROM: 0x15,
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ALTZP: 0x16,
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SLOTC3ROM: 0x17,
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_80STORE: 0x18,
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VERTBLANK: 0x19,
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RDTEXT: 0x1A, // using text mode
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RDMIXED: 0x1B, // using mixed mode
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RDPAGE2: 0x1C, // using text/graphics page2
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RDHIRES: 0x1D, // using Hi-res graphics mode
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RDALTCH: 0x1E, // using alternate character set
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RD80VID: 0x1F, // using 80-column display mode
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PAGE1: 0x54, // select text/graphics page1 main/aux
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PAGE2: 0x55, // select text/graphics page2 main/aux
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RESET_HIRES: 0x56,
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SET_HIRES: 0x57,
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DHIRESON: 0x5E, // Enable double hires
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DHIRESOFF: 0x5F, // Disable double hires
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BANK: 0x73, // Back switched RAM card bank
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IOUDISON: 0x7E, // W IOU Disable on / R7 IOU Disable
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IOUDISOFF: 0x7F, // W IOU Disable off / R7 Double Hires
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// Bank 2
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READBSR2: 0x80,
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WRITEBSR2: 0x81,
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OFFBSR2: 0x82,
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READWRBSR2: 0x83,
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// Shadow Bank 2
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_READBSR2: 0x84,
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_WRITEBSR2: 0x85,
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_OFFBSR2: 0x86,
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_READWRBSR2: 0x87,
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// Bank 1
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READBSR1: 0x88,
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WRITEBSR1: 0x89,
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OFFBSR1: 0x8a,
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READWRBSR1: 0x8b,
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// Shadow Bank 1
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_READBSR1: 0x8c,
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_WRITEBSR1: 0x8d,
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_OFFBSR1: 0x8e,
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_READWRBSR1: 0x8f
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};
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class Switches implements Memory {
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// Remapping of LOCS from string -> number to number -> string
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private locs: { [loc: number]: string } = {};
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constructor(private readonly mmu: MMU, private readonly io: any) {
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Object.keys(LOC).forEach((loc: keyof typeof LOC) => {
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let v = LOC[loc];
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this.locs[v] = loc;
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});
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}
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start() {
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return 0xC0;
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}
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end() {
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return 0xC0;
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}
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read(_page: byte, off: byte) {
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var result;
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if (off in this.locs) {
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result = this.mmu._access(off);
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} else {
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result = this.io.ioSwitch(off, undefined);
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}
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return result;
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}
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write(_page: byte, off: byte, val: byte) {
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if (off in this.locs) {
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this.mmu._access(off, val);
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} else {
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this.io.ioSwitch(off, val);
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}
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}
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}
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class AuxRom {
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constructor(
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private readonly mmu: MMU,
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private readonly rom: Memory) { }
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read(page: byte, off: byte) {
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if (page == 0xc3) {
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this.mmu._setIntc8rom(true);
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this.mmu._updateBanks();
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}
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if (page == 0xcf && off == 0xff) {
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this.mmu._setIntc8rom(false);
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this.mmu._updateBanks();
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}
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return this.rom.read(page, off);
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}
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write(_page: byte, _off: byte, _val: byte) {
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// It's ROM.
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}
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}
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/*
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interface State {
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bank1: this._bank1,
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readbsr: this._readbsr,
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writebsr: this._writebsr,
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prewrite: this._prewrite,
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intcxrom: this._intcxrom,
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slot3rom: this._slot3rom,
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intc8rom: this._intc8rom,
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auxRamRead: this._auxRamRead,
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auxRamWrite: this._auxRamWrite,
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altzp: this._altzp,
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_80store: this._80store,
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page2: this._page2,
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hires: this._hires,
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mem00_01: [this.mem00_01[0].getState(), this.mem00_01[1].getState()],
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mem02_03: [this.mem02_03[0].getState(), this.mem02_03[1].getState()],
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mem0C_1F: [this.mem0C_1F[0].getState(), this.mem0C_1F[1].getState()],
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mem60_BF: [this.mem60_BF[0].getState(), this.mem60_BF[1].getState()],
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memD0_DF: [
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this.memD0_DF[0].getState(), this.memD0_DF[1].getState(),
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this.memD0_DF[2].getState(), this.memD0_DF[3].getState()
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],
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memE0_FF: [this.memE0_FF[0].getState(), this.memE0_FF[1].getState()]
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};
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*/
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export default class MMU implements Memory {
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private _readPages = new Array(0x100);
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private _writePages = new Array(0x100);
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private _pages = new Array(0x100);
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// Language Card RAM Softswitches
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private _bank1: boolean;
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private _readbsr: boolean;
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private _writebsr: boolean;
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private _prewrite: boolean;
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// Auxillary ROM
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private _intcxrom: boolean;
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private _slot3rom: boolean;
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private _intc8rom: boolean;
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// Auxillary RAM
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private _auxRamRead: boolean;
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private _auxRamWrite: boolean;
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private _altzp: boolean;
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// Video
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private _80store: boolean;
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private _page2: boolean;
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private _hires: boolean;
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private _iouDisable: boolean;
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private _vbEnd = 0;
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private switches = new Switches(this, this.io);
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private auxRom = new AuxRom(this, this.rom);
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// These fields represent the bank-switched memory ranges.
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private mem00_01 = [new RAM(0x0, 0x1), new RAM(0x0, 0x1)];
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private mem02_03 = [new RAM(0x2, 0x3), new RAM(0x2, 0x3)];
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private mem04_07 = [this.lores1.bank0(), this.lores1.bank1()];
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private mem08_0B = [this.lores2.bank0(), this.lores2.bank1()];
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private mem0C_1F = [new RAM(0xC, 0x1F), new RAM(0xC, 0x1F)];
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private mem20_3F = [this.hires1.bank0(), this.hires1.bank1()];
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private mem40_5F = [this.hires2.bank0(), this.hires2.bank1()];
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private mem60_BF = [new RAM(0x60, 0xBF), new RAM(0x60, 0xBF)];
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private memC0_C0 = [this.switches];
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private memC1_CF = [this.io, this.auxRom];
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private memD0_DF = [
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this.rom,
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new RAM(0xD0, 0xDF), new RAM(0xD0, 0xDF),
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new RAM(0xD0, 0xDF), new RAM(0xD0, 0xDF)
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];
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private memE0_FF = [this.rom, new RAM(0xE0, 0xFF), new RAM(0xE0, 0xFF)];
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constructor(
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private readonly cpu: CPU6502,
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private readonly vm: VideoModes,
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private readonly lores1: LoresPage,
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private readonly lores2: LoresPage,
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private readonly hires1: HiresPage,
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private readonly hires2: HiresPage,
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private readonly io: Apple2IO,
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// TODO(flan): Better typing.
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private readonly rom: any) {
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/*
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* Initialize read/write banks
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*/
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// Zero Page/Stack
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for (let idx = 0x0; idx < 0x2; idx++) {
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this._pages[idx] = this.mem00_01;
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this._readPages[idx] = this._pages[idx][0];
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this._writePages[idx] = this._pages[idx][0];
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}
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// 0x300-0x400
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for (let idx = 0x2; idx < 0x4; idx++) {
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this._pages[idx] = this.mem02_03;
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this._readPages[idx] = this._pages[idx][0];
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this._writePages[idx] = this._pages[idx][0];
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}
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// Text Page 1
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for (let idx = 0x4; idx < 0x8; idx++) {
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this._pages[idx] = this.mem04_07;
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this._readPages[idx] = this._pages[idx][0];
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this._writePages[idx] = this._pages[idx][0];
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}
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// Text Page 2
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for (let idx = 0x8; idx < 0xC; idx++) {
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this._pages[idx] = this.mem08_0B;
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this._readPages[idx] = this._pages[idx][0];
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this._writePages[idx] = this._pages[idx][0];
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}
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// 0xC00-0x2000
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for (let idx = 0xC; idx < 0x20; idx++) {
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this._pages[idx] = this.mem0C_1F;
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this._readPages[idx] = this._pages[idx][0];
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this._writePages[idx] = this._pages[idx][0];
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}
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// Hires Page 1
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for (let idx = 0x20; idx < 0x40; idx++) {
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this._pages[idx] = this.mem20_3F;
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this._readPages[idx] = this._pages[idx][0];
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this._writePages[idx] = this._pages[idx][0];
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}
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// Hires Page 2
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for (let idx = 0x40; idx < 0x60; idx++) {
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this._pages[idx] = this.mem40_5F;
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this._readPages[idx] = this._pages[idx][0];
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this._writePages[idx] = this._pages[idx][0];
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}
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// 0x6000-0xc000
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for (let idx = 0x60; idx < 0xc0; idx++) {
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this._pages[idx] = this.mem60_BF;
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this._readPages[idx] = this._pages[idx][0];
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this._writePages[idx] = this._pages[idx][0];
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}
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// I/O Switches
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{
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let idx = 0xc0;
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this._pages[idx] = this.memC0_C0;
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this._readPages[idx] = this._pages[idx][0];
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this._writePages[idx] = this._pages[idx][0];
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}
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// Slots
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for (let idx = 0xc1; idx < 0xd0; idx++) {
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this._pages[idx] = this.memC1_CF;
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this._readPages[idx] = this._pages[idx][0];
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this._writePages[idx] = this._pages[idx][0];
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}
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// Basic ROM
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for (let idx = 0xd0; idx < 0xe0; idx++) {
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this._pages[idx] = this.memD0_DF;
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this._readPages[idx] = this._pages[idx][0];
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this._writePages[idx] = this._pages[idx][0];
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}
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// Monitor ROM
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for (let idx = 0xe0; idx < 0x100; idx++) {
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this._pages[idx] = this.memE0_FF;
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this._readPages[idx] = this._pages[idx][0];
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this._writePages[idx] = this._pages[idx][0];
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}
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};
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_initSwitches() {
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this._bank1 = true;
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this._readbsr = false;
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this._writebsr = false;
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this._prewrite = false;
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this._auxRamRead = false;
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this._auxRamWrite = false;
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this._altzp = false;
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this._intcxrom = false;
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this._slot3rom = false;
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this._intc8rom = false;
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this._80store = false;
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this._page2 = false;
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this._hires = false;
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this._iouDisable = true;
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}
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_debug(..._args: any) {
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// debug.apply(this, arguments);
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}
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_setIntc8rom(on: boolean) {
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this._intc8rom = on;
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}
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_updateBanks() {
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if (this._auxRamRead) {
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for (let idx = 0x02; idx < 0xC0; idx++) {
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this._readPages[idx] = this._pages[idx][1];
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}
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} else {
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for (let idx = 0x02; idx < 0xC0; idx++) {
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this._readPages[idx] = this._pages[idx][0];
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}
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}
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if (this._auxRamWrite) {
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for (let idx = 0x02; idx < 0xC0; idx++) {
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this._writePages[idx] = this._pages[idx][1];
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}
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} else {
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for (let idx = 0x02; idx < 0xC0; idx++) {
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this._writePages[idx] = this._pages[idx][0];
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}
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}
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if (this._80store) {
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if (this._page2) {
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for (let idx = 0x4; idx < 0x8; idx++) {
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this._readPages[idx] = this._pages[idx][1];
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this._writePages[idx] = this._pages[idx][1];
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}
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if (this._hires) {
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for (let idx = 0x20; idx < 0x40; idx++) {
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this._readPages[idx] = this._pages[idx][1];
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this._writePages[idx] = this._pages[idx][1];
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}
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}
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} else {
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for (let idx = 0x4; idx < 0x8; idx++) {
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this._readPages[idx] = this._pages[idx][0];
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this._writePages[idx] = this._pages[idx][0];
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}
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if (this._hires) {
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for (let idx = 0x20; idx < 0x40; idx++) {
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this._readPages[idx] = this._pages[idx][0];
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this._writePages[idx] = this._pages[idx][0];
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}
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}
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}
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}
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if (this._intcxrom) {
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for (let idx = 0xc1; idx < 0xd0; idx++) {
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this._readPages[idx] = this._pages[idx][1];
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}
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} else {
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for (let idx = 0xc1; idx < 0xd0; idx++) {
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this._readPages[idx] = this._pages[idx][0];
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}
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if (!this._slot3rom) {
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this._readPages[0xc3] = this._pages[0xc3][1];
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}
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if (this._intc8rom) {
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for (let idx = 0xc8; idx < 0xd0; idx++) {
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this._readPages[idx] = this._pages[idx][1];
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}
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}
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}
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if (this._altzp) {
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for (let idx = 0x0; idx < 0x2; idx++) {
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this._readPages[idx] = this._pages[idx][1];
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this._writePages[idx] = this._pages[idx][1];
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}
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} else {
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for (let idx = 0x0; idx < 0x2; idx++) {
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this._readPages[idx] = this._pages[idx][0];
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this._writePages[idx] = this._pages[idx][0];
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}
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}
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if (this._readbsr) {
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if (this._bank1) {
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for (let idx = 0xd0; idx < 0xe0; idx++) {
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this._readPages[idx] = this._pages[idx][this._altzp ? 2 : 1];
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}
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} else {
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for (let idx = 0xd0; idx < 0xe0; idx++) {
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this._readPages[idx] = this._pages[idx][this._altzp ? 4 : 3];
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}
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}
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for (let idx = 0xe0; idx < 0x100; idx++) {
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this._readPages[idx] = this._pages[idx][this._altzp ? 2 : 1];
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}
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} else {
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for (let idx = 0xd0; idx < 0x100; idx++) {
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this._readPages[idx] = this._pages[idx][0];
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}
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}
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if (this._writebsr) {
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if (this._bank1) {
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for (let idx = 0xd0; idx < 0xe0; idx++) {
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this._writePages[idx] = this._pages[idx][this._altzp ? 2 : 1];
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}
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} else {
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for (let idx = 0xd0; idx < 0xe0; idx++) {
|
|
this._writePages[idx] = this._pages[idx][this._altzp ? 4 : 3];
|
|
}
|
|
}
|
|
for (let idx = 0xe0; idx < 0x100; idx++) {
|
|
this._writePages[idx] = this._pages[idx][this._altzp ? 2 : 1];
|
|
}
|
|
} else {
|
|
for (let idx = 0xd0; idx < 0x100; idx++) {
|
|
this._writePages[idx] = this._pages[idx][0];
|
|
}
|
|
}
|
|
}
|
|
|
|
/*
|
|
* The Big Switch
|
|
*/
|
|
|
|
_access(off: byte, val?: byte) {
|
|
let result;
|
|
let readMode = val === undefined;
|
|
let writeMode = val !== undefined;
|
|
switch (off) {
|
|
|
|
// Apple //e memory management
|
|
|
|
case LOC._80STOREOFF:
|
|
if (writeMode) {
|
|
this._80store = false;
|
|
this._debug('80 Store Off');
|
|
this.vm.page(this._page2 ? 2 : 1);
|
|
} else {
|
|
// Chain to io for keyboard
|
|
result = this.io.ioSwitch(off, val);
|
|
}
|
|
break;
|
|
case LOC._80STOREON:
|
|
if (writeMode) {
|
|
this._80store = true;
|
|
this._debug('80 Store On');
|
|
} else
|
|
result = 0;
|
|
break;
|
|
case LOC.RAMRDOFF:
|
|
if (writeMode) {
|
|
this._auxRamRead = false;
|
|
this._debug('Aux RAM Read Off');
|
|
} else
|
|
result = 0;
|
|
break;
|
|
case LOC.RAMRDON:
|
|
if (writeMode) {
|
|
this._auxRamRead = true;
|
|
this._debug('Aux RAM Read On');
|
|
} else
|
|
result = 0;
|
|
break;
|
|
case LOC.RAMWROFF:
|
|
if (writeMode) {
|
|
this._auxRamWrite = false;
|
|
this._debug('Aux RAM Write Off');
|
|
} else
|
|
result = 0;
|
|
break;
|
|
case LOC.RAMWRON:
|
|
if (writeMode) {
|
|
this._auxRamWrite = true;
|
|
this._debug('Aux RAM Write On');
|
|
} else
|
|
result = 0;
|
|
break;
|
|
|
|
case LOC.INTCXROMOFF:
|
|
if (writeMode) {
|
|
this._intcxrom = false;
|
|
this._intc8rom = false;
|
|
this._debug('Int CX ROM Off');
|
|
}
|
|
break;
|
|
case LOC.INTCXROMON:
|
|
if (writeMode) {
|
|
this._intcxrom = true;
|
|
this._debug('Int CX ROM On');
|
|
}
|
|
break;
|
|
case LOC.ALTZPOFF: // 0x08
|
|
if (writeMode) {
|
|
this._altzp = false;
|
|
this._debug('Alt ZP Off');
|
|
}
|
|
break;
|
|
case LOC.ALTZPON: // 0x09
|
|
if (writeMode) {
|
|
this._altzp = true;
|
|
this._debug('Alt ZP On');
|
|
}
|
|
break;
|
|
case LOC.SLOTC3ROMOFF: // 0x0A
|
|
if (writeMode) {
|
|
this._slot3rom = false;
|
|
this._debug('Slot 3 ROM Off');
|
|
}
|
|
break;
|
|
case LOC.SLOTC3ROMON: // 0x0B
|
|
if (writeMode) {
|
|
this._slot3rom = true;
|
|
this._debug('Slot 3 ROM On');
|
|
}
|
|
break;
|
|
|
|
// Graphics Switches
|
|
|
|
case LOC.CLR80VID:
|
|
if (writeMode) {
|
|
this._debug('80 Column Mode off');
|
|
this.vm._80col(false);
|
|
}
|
|
break;
|
|
case LOC.SET80VID:
|
|
if (writeMode) {
|
|
this._debug('80 Column Mode on');
|
|
this.vm._80col(true);
|
|
}
|
|
break;
|
|
case LOC.CLRALTCH:
|
|
if (writeMode) {
|
|
this._debug('Alt Char off');
|
|
this.vm.altchar(false);
|
|
}
|
|
break;
|
|
case LOC.SETALTCH:
|
|
if (writeMode) {
|
|
this._debug('Alt Char on');
|
|
this.vm.altchar(true);
|
|
}
|
|
break;
|
|
case LOC.PAGE1:
|
|
this._page2 = false;
|
|
if (!this._80store) {
|
|
result = this.io.ioSwitch(off, val);
|
|
}
|
|
this._debug('Page 2 off');
|
|
break;
|
|
case LOC.PAGE2:
|
|
this._page2 = true;
|
|
if (!this._80store) {
|
|
result = this.io.ioSwitch(off, val);
|
|
}
|
|
this._debug('Page 2 on');
|
|
break;
|
|
|
|
case LOC.RESET_HIRES:
|
|
this._hires = false;
|
|
result = this.io.ioSwitch(off, val);
|
|
this._debug('Hires off');
|
|
break;
|
|
|
|
case LOC.DHIRESON:
|
|
if (this._iouDisable) {
|
|
this.vm.doubleHires(true);
|
|
} else {
|
|
result = this.io.ioSwitch(off, val); // an3
|
|
}
|
|
break;
|
|
|
|
case LOC.DHIRESOFF:
|
|
if (this._iouDisable) {
|
|
this.vm.doubleHires(false);
|
|
} else {
|
|
result = this.io.ioSwitch(off, val); // an3
|
|
}
|
|
break;
|
|
|
|
case LOC.SET_HIRES:
|
|
this._hires = true;
|
|
result = this.io.ioSwitch(off, val);
|
|
this._debug('Hires on');
|
|
break;
|
|
|
|
case LOC.IOUDISON:
|
|
if (writeMode) {
|
|
this._iouDisable = true;
|
|
}
|
|
result = this._iouDisable ? 0x00 : 0x80;
|
|
break;
|
|
|
|
case LOC.IOUDISOFF:
|
|
if (writeMode) {
|
|
this._iouDisable = false;
|
|
}
|
|
result = this.vm.isDoubleHires() ? 0x80 : 0x00;
|
|
break;
|
|
|
|
// Language Card Switches
|
|
|
|
case LOC.READBSR2: // 0xC080
|
|
case LOC._READBSR2: // 0xC084
|
|
this._bank1 = false;
|
|
this._readbsr = true;
|
|
this._writebsr = false;
|
|
this._prewrite = false;
|
|
// _debug('Bank 2 Read');
|
|
break;
|
|
case LOC.WRITEBSR2: // 0xC081
|
|
case LOC._WRITEBSR2: // 0xC085
|
|
this._bank1 = false;
|
|
this._readbsr = false;
|
|
if (readMode) { this._writebsr = this._prewrite; }
|
|
this._prewrite = readMode;
|
|
// _debug('Bank 2 Write');
|
|
break;
|
|
case LOC.OFFBSR2: // 0xC082
|
|
case LOC._OFFBSR2: // 0xC086
|
|
this._bank1 = false;
|
|
this._readbsr = false;
|
|
this._writebsr = false;
|
|
this._prewrite = false;
|
|
// _debug('Bank 2 Off');
|
|
break;
|
|
case LOC.READWRBSR2: // 0xC083
|
|
case LOC._READWRBSR2: // 0xC087
|
|
this._bank1 = false;
|
|
this._readbsr = true;
|
|
if (readMode) { this._writebsr = this._prewrite; }
|
|
this._prewrite = readMode;
|
|
// _debug('Bank 2 Read/Write');
|
|
break;
|
|
case LOC.READBSR1: // 0xC088
|
|
case LOC._READBSR1: // 0xC08c
|
|
this._bank1 = true;
|
|
this._readbsr = true;
|
|
this._writebsr = false;
|
|
this._prewrite = false;
|
|
// _debug('Bank 1 Read');
|
|
break;
|
|
case LOC.WRITEBSR1: // 0xC089
|
|
case LOC._WRITEBSR1: // 0xC08D
|
|
this._bank1 = true;
|
|
this._readbsr = false;
|
|
if (readMode) { this._writebsr = this._prewrite; }
|
|
this._prewrite = readMode;
|
|
// _debug('Bank 1 Write');
|
|
break;
|
|
case LOC.OFFBSR1: // 0xC08A
|
|
case LOC._OFFBSR1: // 0xC08E
|
|
this._bank1 = true;
|
|
this._readbsr = false;
|
|
this._writebsr = false;
|
|
this._prewrite = false;
|
|
// _debug('Bank 1 Off');
|
|
break;
|
|
case LOC.READWRBSR1: // 0xC08B
|
|
case LOC._READWRBSR1: // 0xC08F
|
|
this._bank1 = true;
|
|
this._readbsr = true;
|
|
if (readMode) { this._writebsr = this._prewrite; }
|
|
this._prewrite = readMode;
|
|
//_debug('Bank 1 Read/Write');
|
|
break;
|
|
|
|
// Status registers
|
|
|
|
case LOC.BSRBANK2:
|
|
this._debug('Bank 2 Read ' + !this._bank1);
|
|
result = !this._bank1 ? 0x80 : 0x00;
|
|
break;
|
|
case LOC.BSRREADRAM:
|
|
this._debug('Bank SW RAM Read ' + this._readbsr);
|
|
result = this._readbsr ? 0x80 : 0x00;
|
|
break;
|
|
case LOC.RAMRD: // 0xC013
|
|
this._debug('Aux RAM Read ' + this._auxRamRead);
|
|
result = this._auxRamRead ? 0x80 : 0x0;
|
|
break;
|
|
case LOC.RAMWRT: // 0xC014
|
|
this._debug('Aux RAM Write ' + this._auxRamWrite);
|
|
result = this._auxRamWrite ? 0x80 : 0x0;
|
|
break;
|
|
case LOC.INTCXROM: // 0xC015
|
|
// _debug('Int CX ROM ' + _intcxrom);
|
|
result = this._intcxrom ? 0x80 : 0x00;
|
|
break;
|
|
case LOC.ALTZP: // 0xC016
|
|
this._debug('Alt ZP ' + this._altzp);
|
|
result = this._altzp ? 0x80 : 0x0;
|
|
break;
|
|
case LOC.SLOTC3ROM: // 0xC017
|
|
this._debug('Slot C3 ROM ' + this._slot3rom);
|
|
result = this._slot3rom ? 0x80 : 0x00;
|
|
break;
|
|
case LOC._80STORE: // 0xC018
|
|
this._debug('80 Store ' + this._80store);
|
|
result = this._80store ? 0x80 : 0x00;
|
|
break;
|
|
case LOC.VERTBLANK: // 0xC019
|
|
// result = cpu.getCycles() % 20 < 5 ? 0x80 : 0x00;
|
|
result = (this.cpu.getCycles() < this._vbEnd) ? 0x80 : 0x00;
|
|
break;
|
|
case LOC.RDTEXT:
|
|
result = this.vm.isText() ? 0x80 : 0x0;
|
|
break;
|
|
case LOC.RDMIXED:
|
|
result = this.vm.isMixed() ? 0x80 : 0x0;
|
|
break;
|
|
case LOC.RDPAGE2:
|
|
result = this.vm.isPage2() ? 0x80 : 0x0;
|
|
break;
|
|
case LOC.RDHIRES:
|
|
result = this.vm.isHires() ? 0x80 : 0x0;
|
|
break;
|
|
case LOC.RD80VID:
|
|
result = this.vm.is80Col() ? 0x80 : 0x0;
|
|
break;
|
|
case LOC.RDALTCH:
|
|
result = this.vm.isAltChar() ? 0x80 : 0x0;
|
|
break;
|
|
|
|
default:
|
|
debug('MMU missing register ' + toHex(off));
|
|
break;
|
|
}
|
|
|
|
if (result !== undefined)
|
|
return result;
|
|
|
|
result = 0;
|
|
|
|
this._updateBanks();
|
|
|
|
return result;
|
|
}
|
|
|
|
public start() {
|
|
this.lores1.start();
|
|
this.lores2.start();
|
|
return 0x00;
|
|
}
|
|
|
|
public end() {
|
|
return 0xff;
|
|
}
|
|
|
|
public reset() {
|
|
debug('reset');
|
|
this._initSwitches();
|
|
this._updateBanks();
|
|
this.vm.reset();
|
|
this.io.reset();
|
|
}
|
|
|
|
public read(page: byte, off: byte) {
|
|
return this._readPages[page].read(page, off);
|
|
}
|
|
|
|
public write(page: byte, off: byte, val: byte) {
|
|
this._writePages[page].write(page, off, val);
|
|
}
|
|
|
|
public resetVB() {
|
|
this._vbEnd = this.cpu.getCycles() + 1000;
|
|
}
|
|
/*
|
|
public getState(): State {
|
|
return {
|
|
bank1: this._bank1,
|
|
readbsr: this._readbsr,
|
|
writebsr: this._writebsr,
|
|
prewrite: this._prewrite,
|
|
|
|
intcxrom: this._intcxrom,
|
|
slot3rom: this._slot3rom,
|
|
intc8rom: this._intc8rom,
|
|
|
|
auxRamRead: this._auxRamRead,
|
|
auxRamWrite: this._auxRamWrite,
|
|
altzp: this._altzp,
|
|
|
|
_80store: this._80store,
|
|
page2: this._page2,
|
|
hires: this._hires,
|
|
|
|
mem00_01: [this.mem00_01[0].getState(), this.mem00_01[1].getState()],
|
|
mem02_03: [this.mem02_03[0].getState(), this.mem02_03[1].getState()],
|
|
mem0C_1F: [this.mem0C_1F[0].getState(), this.mem0C_1F[1].getState()],
|
|
mem60_BF: [this.mem60_BF[0].getState(), this.mem60_BF[1].getState()],
|
|
memD0_DF: [
|
|
this.memD0_DF[0].getState(), this.memD0_DF[1].getState(),
|
|
this.memD0_DF[2].getState(), this.memD0_DF[3].getState()
|
|
],
|
|
memE0_FF: [this.memE0_FF[0].getState(), this.memE0_FF[1].getState()]
|
|
};
|
|
}
|
|
|
|
public setState(state: State) {
|
|
this._readbsr = state.readbsr;
|
|
this._writebsr = state.writebsr;
|
|
this._bank1 = state.bank1;
|
|
this._prewrite = state.prewrite;
|
|
|
|
this._intcxrom = state.intcxrom;
|
|
this._slot3rom = state.slot3rom;
|
|
this._intc8rom = state.intc8rom;
|
|
|
|
this._auxRamRead = state.auxRamRead;
|
|
this._auxRamWrite = state.auxRamWrite;
|
|
this._altzp = state.altzp;
|
|
|
|
this._80store = state._80store;
|
|
this._page2 = state.page2;
|
|
this._hires = state.hires;
|
|
|
|
this.mem00_01[0].setState(state.mem00_01[0]);
|
|
this.mem00_01[1].setState(state.mem00_01[1]);
|
|
this.mem02_03[0].setState(state.mem02_03[0]);
|
|
this.mem02_03[1].setState(state.mem02_03[1]);
|
|
this.mem0C_1F[0].setState(state.mem0C_1F[0]);
|
|
this.mem0C_1F[1].setState(state.mem0C_1F[1]);
|
|
this.mem60_BF[0].setState(state.mem60_BF[0]);
|
|
this.mem60_BF[1].setState(state.mem60_BF[1]);
|
|
this.memD0_DF[0].setState(state.memD0_DF[0]);
|
|
this.memD0_DF[1].setState(state.memD0_DF[1]);
|
|
this.memD0_DF[2].setState(state.memD0_DF[2]);
|
|
this.memD0_DF[3].setState(state.memD0_DF[3]);
|
|
this.memE0_FF[0].setState(state.memE0_FF[0]);
|
|
this.memE0_FF[1].setState(state.memE0_FF[1]);
|
|
|
|
this._updateBanks();
|
|
}
|
|
*/
|
|
}
|