mirror of
https://github.com/whscullin/apple2js.git
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733 lines
21 KiB
JavaScript
733 lines
21 KiB
JavaScript
/* Copyright 2010-2016 Will Scullin <scullin@scullinsteel.com>
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*
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* Permission to use, copy, modify, distribute, and sell this software and its
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* documentation for any purpose is hereby granted without fee, provided that
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* the above copyright notice appear in all copies and that both that
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* copyright notice and this permission notice appear in supporting
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* documentation. No representations are made about the suitability of this
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* software for any purpose. It is provided "as is" without express or
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* implied warranty.
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*/
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/*exported MMU */
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/*globals debug: false, toHex: false
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RAM: false
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*/
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function MMU(cpu, vm, lores1, lores2, hires1, hires2, io, rom)
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{
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'use strict';
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var idx;
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var _readPages = new Array(0x100);
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var _writePages = new Array(0x100);
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var _pages = new Array(0x100);
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// Language Card RAM Softswitches
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var _bank1;
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var _readbsr;
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var _writebsr;
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var _prewrite;
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// Auxilliary ROM
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var _intcxrom;
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var _slot3rom;
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var _intc8rom;
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// Auxilliary RAM
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var _auxRamRead;
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var _auxRamWrite;
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var _altzp;
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// Video
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var _80store;
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var _page2;
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var _hires;
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var _vbEnd = 0;
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/*
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* I/O Switch locations
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*/
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var LOC = {
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// 80 Column
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_80STOREOFF: 0x00,
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_80STOREON: 0x01,
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// Aux RAM
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RAMRDOFF: 0x02,
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RAMRDON: 0x03,
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RAMWROFF: 0x04,
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RAMWRON: 0x05,
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// Bank switched ROM
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INTCXROMOFF: 0x06,
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INTCXROMON: 0x07,
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ALTZPOFF: 0x08,
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ALTZPON: 0x09,
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SLOTC3ROMOFF: 0x0A,
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SLOTC3ROMON: 0x0B,
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// Status
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BSRBANK2: 0x11,
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BSRREADRAM: 0x12,
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RAMRD: 0x13,
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RAMWRT: 0x14,
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INTCXROM: 0x15,
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ALTZP: 0x16,
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SLOTC3ROM: 0x17,
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_80STORE: 0x18,
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VERTBLANK: 0x19,
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PAGE1: 0x54, // select text/graphics page1 main/aux
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PAGE2: 0x55, // select text/graphics page2 main/aux
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RESET_HIRES: 0x56,
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SET_HIRES: 0x57,
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// Bank 2
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READBSR2: 0x80,
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WRITEBSR2: 0x81,
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OFFBSR2: 0x82,
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READWRBSR2: 0x83,
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// Shadow Bank 2
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_READBSR2: 0x84,
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_WRITEBSR2: 0x85,
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_OFFBSR2: 0x86,
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_READWRBSR2: 0x87,
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// Bank 1
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READBSR1: 0x88,
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WRITEBSR1: 0x89,
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OFFBSR1: 0x8a,
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READWRBSR1: 0x8b,
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// Shadow Bank 1
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_READBSR1: 0x8c,
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_WRITEBSR1: 0x8d,
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_OFFBSR1: 0x8e,
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_READWRBSR1: 0x8f
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};
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function _initSwitches() {
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_bank1 = true;
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_readbsr = false;
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_writebsr = false;
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_prewrite = false;
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_auxRamRead = false;
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_auxRamWrite = false;
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_altzp = false;
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_intcxrom = false;
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_slot3rom = false;
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_intc8rom = false;
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_80store = false;
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_page2 = false;
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_hires = false;
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}
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function _debug() {
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/*eslint no-console: 0*/
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// console.debug.apply(this, arguments);
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}
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function Switches() {
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var locs = {};
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for (var loc in LOC) {
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if (LOC.hasOwnProperty(loc)) {
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locs[LOC[loc]] = loc;
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}
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}
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return {
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start: function() {
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return 0xC0;
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},
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end: function() {
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return 0xC0;
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},
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read: function(page, off) {
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var result;
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if (off in locs) {
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result = _access(off);
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} else {
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result = io.ioSwitch(off);
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}
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return result;
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},
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write: function(page, off, val) {
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if (off in locs) {
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_access(off, val);
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} else {
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io.ioSwitch(off, val);
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}
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}
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};
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}
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function AuxRom() {
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return {
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read: function(page, off) {
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if (page == 0xc3) {
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_intc8rom = true;
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_updateBanks();
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}
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if (page == 0xcf && off == 0xff) {
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_intc8rom = false;
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_updateBanks();
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}
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return rom.read(page, off);
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},
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write: function() {}
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};
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}
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var switches = new Switches();
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var auxRom = new AuxRom();
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var mem00_01 = [new RAM(0x0, 0x1), new RAM(0x0, 0x1)];
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var mem02_03 = [new RAM(0x2, 0x3), new RAM(0x2, 0x3)];
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var mem04_07 = [lores1.bank0(), lores1.bank1()];
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var mem08_0B = [lores2.bank0(), lores2.bank1()];
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var mem0C_1F = [new RAM(0xC, 0x1F), new RAM(0xC, 0x1F)];
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var mem20_3F = [hires1.bank0(), hires1.bank1()];
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var mem40_5F = [hires2.bank0(), hires2.bank1()];
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var mem60_BF = [new RAM(0x60,0xBF), new RAM(0x60,0xBF)];
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var memC0_C0 = [switches];
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var memC1_CF = [io, auxRom];
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var memD0_DF = [
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rom,
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new RAM(0xD0,0xDF), new RAM(0xD0,0xDF),
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new RAM(0xD0,0xDF), new RAM(0xD0,0xDF)
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];
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var memE0_FF = [rom, new RAM(0xE0,0xFF), new RAM(0xE0,0xFF)];
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/*
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* Initialize read/write banks
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*/
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// Zero Page/Stack
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for (idx = 0x0; idx < 0x2; idx++) {
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_pages[idx] = mem00_01;
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_readPages[idx] = _pages[idx][0];
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_writePages[idx] = _pages[idx][0];
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}
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// 0x300-0x400
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for (idx = 0x2; idx < 0x4; idx++) {
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_pages[idx] = mem02_03;
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_readPages[idx] = _pages[idx][0];
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_writePages[idx] = _pages[idx][0];
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}
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// Text Page 1
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for (idx = 0x4; idx < 0x8; idx++) {
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_pages[idx] = mem04_07;
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_readPages[idx] = _pages[idx][0];
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_writePages[idx] = _pages[idx][0];
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}
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// Text Page 2
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for (idx = 0x8; idx < 0xC; idx++) {
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_pages[idx] = mem08_0B;
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_readPages[idx] = _pages[idx][0];
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_writePages[idx] = _pages[idx][0];
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}
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// 0xC00-0x2000
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for (idx = 0xC; idx < 0x20; idx++) {
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_pages[idx] = mem0C_1F;
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_readPages[idx] = _pages[idx][0];
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_writePages[idx] = _pages[idx][0];
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}
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// Hires Page 1
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for (idx = 0x20; idx < 0x40; idx++) {
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_pages[idx] = mem20_3F;
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_readPages[idx] = _pages[idx][0];
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_writePages[idx] = _pages[idx][0];
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}
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// Hires Page 2
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for (idx = 0x40; idx < 0x60; idx++) {
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_pages[idx] = mem40_5F;
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_readPages[idx] = _pages[idx][0];
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_writePages[idx] = _pages[idx][0];
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}
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// 0x6000-0xc000
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for (idx = 0x60; idx < 0xc0; idx++) {
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_pages[idx] = mem60_BF;
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_readPages[idx] = _pages[idx][0];
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_writePages[idx] = _pages[idx][0];
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}
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// I/O Switches
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idx = 0xc0;
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_pages[idx] = memC0_C0;
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_readPages[idx] = _pages[idx][0];
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_writePages[idx] = _pages[idx][0];
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// Slots
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for (idx = 0xc1; idx < 0xd0; idx++) {
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_pages[idx] = memC1_CF;
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_readPages[idx] = _pages[idx][0];
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_writePages[idx] = _pages[idx][0];
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}
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// Basic ROM
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for (idx = 0xd0; idx < 0xe0; idx++) {
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_pages[idx] = memD0_DF;
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_readPages[idx] = _pages[idx][0];
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_writePages[idx] = _pages[idx][0];
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}
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// Monitor ROM
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for (idx = 0xe0; idx < 0x100; idx++) {
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_pages[idx] = memE0_FF;
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_readPages[idx] = _pages[idx][0];
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_writePages[idx] = _pages[idx][0];
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}
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function _updateBanks() {
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if (_auxRamRead) {
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for (idx = 0x02; idx < 0xC0; idx++) {
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_readPages[idx] = _pages[idx][1];
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}
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} else {
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for (idx = 0x02; idx < 0xC0; idx++) {
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_readPages[idx] = _pages[idx][0];
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}
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}
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if (_auxRamWrite) {
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for (idx = 0x02; idx < 0xC0; idx++) {
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_writePages[idx] = _pages[idx][1];
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}
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} else {
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for (idx = 0x02; idx < 0xC0; idx++) {
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_writePages[idx] = _pages[idx][0];
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}
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}
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if (_80store) {
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if (_page2) {
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for (idx = 0x4; idx < 0x8; idx++) {
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_readPages[idx] = _pages[idx][1];
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_writePages[idx] = _pages[idx][1];
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}
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if (_hires) {
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for (idx = 0x20; idx < 0x40; idx++) {
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_readPages[idx] = _pages[idx][1];
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_writePages[idx] = _pages[idx][1];
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}
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}
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} else {
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for (idx = 0x4; idx < 0x8; idx++) {
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_readPages[idx] = _pages[idx][0];
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_writePages[idx] = _pages[idx][0];
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}
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if (_hires) {
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for (idx = 0x20; idx < 0x40; idx++) {
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_readPages[idx] = _pages[idx][0];
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_writePages[idx] = _pages[idx][0];
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}
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}
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}
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}
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if (_intcxrom) {
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for (idx = 0xc1; idx < 0xd0; idx++) {
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_readPages[idx] = _pages[idx][1];
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}
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} else {
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for (idx = 0xc1; idx < 0xd0; idx++) {
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_readPages[idx] = _pages[idx][0];
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}
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if (!_slot3rom) {
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_readPages[0xc3] = _pages[0xc3][1];
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}
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if (_intc8rom) {
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for (idx = 0xc8; idx < 0xd0; idx++) {
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_readPages[idx] = _pages[idx][1];
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}
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}
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}
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if (_altzp) {
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for (idx = 0x0; idx < 0x2; idx++) {
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_readPages[idx] = _pages[idx][1];
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_writePages[idx] = _pages[idx][1];
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}
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} else {
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for (idx = 0x0; idx < 0x2; idx++) {
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_readPages[idx] = _pages[idx][0];
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_writePages[idx] = _pages[idx][0];
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}
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}
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if (_readbsr) {
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if (_bank1) {
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for (idx = 0xd0; idx < 0xe0; idx++) {
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_readPages[idx] = _pages[idx][_altzp ? 2 : 1];
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}
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} else {
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for (idx = 0xd0; idx < 0xe0; idx++) {
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_readPages[idx] = _pages[idx][_altzp ? 4 : 3];
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}
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}
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for (idx = 0xe0; idx < 0x100; idx++) {
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_readPages[idx] = _pages[idx][_altzp ? 2 : 1];
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}
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} else {
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for (idx = 0xd0; idx < 0x100; idx++) {
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_readPages[idx] = _pages[idx][0];
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}
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}
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if (_writebsr) {
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if (_bank1) {
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for (idx = 0xd0; idx < 0xe0; idx++) {
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_writePages[idx] = _pages[idx][_altzp ? 2 : 1];
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}
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} else {
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for (idx = 0xd0; idx < 0xe0; idx++) {
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_writePages[idx] = _pages[idx][_altzp ? 4 : 3];
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}
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}
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for (idx = 0xe0; idx < 0x100; idx++) {
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_writePages[idx] = _pages[idx][_altzp ? 2 : 1];
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}
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} else {
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for (idx = 0xd0; idx < 0x100; idx++) {
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_writePages[idx] = _pages[idx][0];
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}
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}
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}
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/*
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* The Big Switch
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*/
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function _access(off, val) {
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var result;
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var readMode = val === undefined;
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switch (off) {
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// Apple //e memory management
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case LOC._80STOREOFF:
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if (val !== undefined) {
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_80store = false;
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_debug('80 Store Off');
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} else {
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// Chain to io for keyboard
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result = io.ioSwitch(off, val);
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}
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break;
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case LOC._80STOREON:
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if (val !== undefined) {
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_80store = true;
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_debug('80 Store On');
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} else
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result = 0;
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break;
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case LOC.RAMRDOFF:
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if (val !== undefined) {
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_auxRamRead = false;
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_debug('Aux RAM Read Off');
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} else
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result = 0;
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break;
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case LOC.RAMRDON:
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if (val !== undefined) {
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_auxRamRead = true;
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_debug('Aux RAM Read On');
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} else
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result = 0;
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break;
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case LOC.RAMWROFF:
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if (val !== undefined) {
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_auxRamWrite = false;
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_debug('Aux RAM Write Off');
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} else
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result = 0;
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break;
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case LOC.RAMWRON:
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if (val !== undefined) {
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_auxRamWrite = true;
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_debug('Aux RAM Write On');
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} else
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result = 0;
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break;
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case LOC.INTCXROMOFF:
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if (val !== undefined) {
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_intcxrom = false;
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_intc8rom = false;
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_debug('Int CX ROM Off');
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}
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break;
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case LOC.INTCXROMON:
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if (val !== undefined) {
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_intcxrom = true;
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_debug('Int CX ROM On');
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}
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break;
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case LOC.ALTZPOFF: // 0x08
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if (val !== undefined) {
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_altzp = false;
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_debug('Alt ZP Off');
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}
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break;
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case LOC.ALTZPON: // 0x09
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if (val !== undefined) {
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_altzp = true;
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_debug('Alt ZP On');
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}
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break;
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case LOC.SLOTC3ROMOFF: // 0x0A
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if (val !== undefined) {
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_slot3rom = false;
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_debug('Slot 3 ROM Off');
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}
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break;
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case LOC.SLOTC3ROMON: // 0x0B
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if (val !== undefined) {
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_slot3rom = true;
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_debug('Slot 3 ROM On');
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}
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break;
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// Graphics Switches
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case LOC.PAGE1:
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_page2 = false;
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if (!_80store) {
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result = io.ioSwitch(off, val);
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}
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_debug('Page 2 off');
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break;
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case LOC.PAGE2:
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_page2 = true;
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if (!_80store) {
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result = io.ioSwitch(off, val);
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}
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_debug('Page 2 on');
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break;
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case LOC.RESET_HIRES:
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_hires = false;
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result = io.ioSwitch(off, val);
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_debug('Hires off');
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break;
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case LOC.SET_HIRES:
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_hires = true;
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result = io.ioSwitch(off, val);
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_debug('Hires on');
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break;
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// Language Card Switches
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case LOC.READBSR2: // 0xC080
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case LOC._READBSR2: // 0xC084
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_bank1 = false;
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_readbsr = true;
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_writebsr = false;
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_prewrite = false;
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// _debug('Bank 2 Read');
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break;
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case LOC.WRITEBSR2: // 0xC081
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case LOC._WRITEBSR2: // 0xC085
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_bank1 = false;
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|
_readbsr = false;
|
|
if (readMode) { _writebsr = _prewrite; }
|
|
_prewrite = readMode;
|
|
// _debug('Bank 2 Write');
|
|
break;
|
|
case LOC.OFFBSR2: // 0xC082
|
|
case LOC._OFFBSR2: // 0xC086
|
|
_bank1 = false;
|
|
_readbsr = false;
|
|
_writebsr = false;
|
|
_prewrite = false;
|
|
// _debug('Bank 2 Off');
|
|
break;
|
|
case LOC.READWRBSR2: // 0xC083
|
|
case LOC._READWRBSR2: // 0xC087
|
|
_bank1 = false;
|
|
_readbsr = true;
|
|
if (readMode) { _writebsr = _prewrite; }
|
|
_prewrite = readMode;
|
|
// _debug('Bank 2 Read/Write');
|
|
break;
|
|
case LOC.READBSR1: // 0xC088
|
|
case LOC._READBSR1: // 0xC08c
|
|
_bank1 = true;
|
|
_readbsr = true;
|
|
_writebsr = false;
|
|
_prewrite = false;
|
|
// _debug('Bank 1 Read');
|
|
break;
|
|
case LOC.WRITEBSR1: // 0xC089
|
|
case LOC._WRITEBSR1: // 0xC08D
|
|
_bank1 = true;
|
|
_readbsr = false;
|
|
if (readMode) { _writebsr = _prewrite; }
|
|
_prewrite = readMode;
|
|
// _debug('Bank 1 Write');
|
|
break;
|
|
case LOC.OFFBSR1: // 0xC08A
|
|
case LOC._OFFBSR1: // 0xC08E
|
|
_bank1 = true;
|
|
_readbsr = false;
|
|
_writebsr = false;
|
|
_prewrite = false;
|
|
// _debug('Bank 1 Off');
|
|
break;
|
|
case LOC.READWRBSR1: // 0xC08B
|
|
case LOC._READWRBSR1: // 0xC08F
|
|
_bank1 = true;
|
|
_readbsr = true;
|
|
if (readMode) { _writebsr = _prewrite; }
|
|
_prewrite = readMode;
|
|
//_debug('Bank 1 Read/Write');
|
|
break;
|
|
|
|
// Status registers
|
|
|
|
case LOC.BSRBANK2:
|
|
_debug('Bank 2 Read ' + !_bank1);
|
|
result = !_bank1 ? 0x80 : 0x00;
|
|
break;
|
|
case LOC.BSRREADRAM:
|
|
_debug('Bank SW RAM Read ' + _readbsr);
|
|
result = _readbsr ? 0x80 : 0x00;
|
|
break;
|
|
case LOC.RAMRD: // 0xC013
|
|
_debug('Aux RAM Read ' + _auxRamRead);
|
|
result = _auxRamRead ? 0x80 : 0x0;
|
|
break;
|
|
case LOC.RAMWRT: // 0xC014
|
|
_debug('Aux RAM Write ' + _auxRamWrite);
|
|
result = _auxRamWrite ? 0x80 : 0x0;
|
|
break;
|
|
case LOC.INTCXROM: // 0xC015
|
|
// _debug('Int CX ROM ' + _intcxrom);
|
|
result = _intcxrom ? 0x80 : 0x00;
|
|
break;
|
|
case LOC.ALTZP: // 0xC016
|
|
_debug('Alt ZP ' + _altzp);
|
|
result = _altzp ? 0x80 : 0x0;
|
|
break;
|
|
case LOC.SLOTC3ROM: // 0xC017
|
|
_debug('Slot C3 ROM ' + _slot3rom);
|
|
result = _slot3rom ? 0x80 : 0x00;
|
|
break;
|
|
case LOC._80STORE: // 0xC018
|
|
_debug('80 Store ' + _80store);
|
|
result = _80store ? 0x80 : 0x00;
|
|
break;
|
|
case LOC.VERTBLANK: // 0xC019
|
|
// result = cpu.cycles() % 20 < 5 ? 0x80 : 0x00;
|
|
result = (cpu.cycles() < _vbEnd) ? 0x80 : 0x00;
|
|
break;
|
|
|
|
default:
|
|
debug('MMU missing register ' + toHex(off));
|
|
break;
|
|
}
|
|
|
|
if (result !== undefined)
|
|
return result;
|
|
|
|
result = 0;
|
|
|
|
_updateBanks();
|
|
|
|
return result;
|
|
}
|
|
|
|
return {
|
|
start: function mmu_start() {
|
|
return 0x00;
|
|
},
|
|
end: function mmu_end() {
|
|
return 0xff;
|
|
},
|
|
reset: function() {
|
|
debug('reset');
|
|
_initSwitches();
|
|
_updateBanks();
|
|
vm.reset();
|
|
io.reset();
|
|
},
|
|
read: function mmu_read(page, off, debug) {
|
|
return _readPages[page].read(page, off, debug);
|
|
},
|
|
write: function mmu_write(page, off, val) {
|
|
_writePages[page].write(page, off, val);
|
|
},
|
|
resetVB: function mmu_resetVB() {
|
|
_vbEnd = cpu.cycles() + 1000;
|
|
},
|
|
getState: function() {
|
|
return {
|
|
readbsr: _readbsr,
|
|
writebsr: _writebsr,
|
|
bank1: _bank1,
|
|
prewrite: _prewrite,
|
|
|
|
intcxrom: _intcxrom,
|
|
slot3rom: _slot3rom,
|
|
intc8rom: _intc8rom,
|
|
auxRamRead: _auxRamRead,
|
|
auxRamWrite: _auxRamWrite,
|
|
altzp: _altzp,
|
|
|
|
_80store: _80store,
|
|
page2: _page2,
|
|
|
|
mem00_01: [mem00_01[0].getState(), mem00_01[1].getState()],
|
|
mem02_03: [mem02_03[0].getState(), mem02_03[1].getState()],
|
|
mem0C_1F: [mem0C_1F[0].getState(), mem0C_1F[1].getState()],
|
|
mem60_BF: [mem60_BF[0].getState(), mem60_BF[1].getState()],
|
|
memD0_DF: [
|
|
memD0_DF[0].getState(), memD0_DF[1].getState(),
|
|
memD0_DF[2].getState(), memD0_DF[3].getState()
|
|
],
|
|
memE0_FF: [memE0_FF[0].getState(), memE0_FF[1].getState()]
|
|
};
|
|
},
|
|
setState: function(state) {
|
|
_readbsr = state.readbsr;
|
|
_writebsr = state.writebsr;
|
|
_bank1 = state.bank1;
|
|
|
|
_intcxrom = state.intcxrom;
|
|
_slot3rom = state.slot3rom;
|
|
_intc8rom = state.intc8rom;
|
|
_auxRamRead = state.auxRamRead;
|
|
_auxRamWrite = state.auxRamWrite;
|
|
_altzp = state.altzp;
|
|
|
|
_80store = state._80store;
|
|
_page2 = state.page2;
|
|
|
|
mem00_01[0].setState(state.mem00_01[0]);
|
|
mem00_01[1].setState(state.mem00_01[1]);
|
|
mem02_03[0].setState(state.mem02_03[0]);
|
|
mem02_03[1].setState(state.mem02_03[1]);
|
|
mem0C_1F[0].setState(state.mem0C_1F[0]);
|
|
mem0C_1F[1].setState(state.mem0C_1F[1]);
|
|
mem60_BF[0].setState(state.mem60_BF[0]);
|
|
mem60_BF[1].setState(state.mem60_BF[1]);
|
|
memD0_DF[0].setState(state.memD0_DF[0]);
|
|
memD0_DF[1].setState(state.memD0_DF[1]);
|
|
memD0_DF[2].setState(state.memD0_DF[2]);
|
|
memD0_DF[3].setState(state.memD0_DF[3]);
|
|
memE0_FF[0].setState(state.memE0_FF[0]);
|
|
memE0_FF[1].setState(state.memE0_FF[1]);
|
|
|
|
_access(-1);
|
|
_prewrite = state.prewrite;
|
|
}
|
|
};
|
|
}
|