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https://github.com/dschmenk/apple2pi.git
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97 lines
2.9 KiB
C
Executable File
97 lines
2.9 KiB
C
Executable File
//
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// Modified from:
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// How to access GPIO registers from C-code on the Raspberry-Pi
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// Example program
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// 15-January-2012
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// Dom and Gert
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// Revised: 15-Feb-2013
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#include <stdio.h>
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#include <stdlib.h>
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#include <fcntl.h>
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#include <sys/mman.h>
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#include <unistd.h>
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// Access from ARM Running Linux
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#define BCM2708_PERI_BASE 0x7E000000
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#define ARM_PERI_BASE 0x20000000
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#define GPIO_OFFSET 0x00200000
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#define CMGP_OFFSET 0x00101000
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#define GPIO_BASE (ARM_PERI_BASE+GPIO_OFFSET) /* GPIO controller */
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#define CMGP_BASE (ARM_PERI_BASE+CMGP_OFFSET) /* CM controller */
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// GPIO setup macros. Always use INP_GPIO(x) before using OUT_GPIO(x) or SET_GPIO_ALT(x,y)
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#define INP_GPIO(g) *(gpio+((g)/10)) &= ~(7<<(((g)%10)*3))
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#define OUT_GPIO(g) *(gpio+((g)/10)) |= (1<<(((g)%10)*3))
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#define SET_GPIO_ALT(g,a) *(gpio+(((g)/10))) |= (((a)<=3?(a)+4:(a)==4?3:2)<<(((g)%10)*3))
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#define GPIO_REG(reg) (gpio[(reg-(BCM2708_PERI_BASE+GPIO_OFFSET))/4])
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#define CMGP_REG(reg) (cmgp[(reg-(BCM2708_PERI_BASE+CMGP_OFFSET))/4])
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#define GPFSEL0 (0x7E200000)
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#define CM_GP0CTL (0x7E101070)
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#define CM_GP0DIV (0x7E101074)
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//
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// Set up a memory regions to access GPIO
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//
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volatile unsigned int *setup_io(reg_base)
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{
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int mem_fd;
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void *io_map;
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// open /dev/mem
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if ((mem_fd = open("/dev/mem", O_RDWR|O_SYNC) ) < 0)
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{
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printf("can't open /dev/mem \n");
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exit(-1);
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}
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// mmap IO
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io_map = mmap(NULL, //Any adddress in our space will do
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4096, //Map length
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PROT_READ|PROT_WRITE,// Enable reading & writting to mapped memory
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MAP_SHARED, //Shared with other processes
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mem_fd, //File to map
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reg_base); //Offset to peripheral
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close(mem_fd); //No need to keep mem_fd open after mmap
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if (io_map == MAP_FAILED)
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{
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printf("mmap error %d\n", (int)io_map);//errno also set!
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exit(-1);
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}
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return (volatile unsigned *)io_map;
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}
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// I/O access
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volatile unsigned *gpio, *cmgp;
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int main(int argc, char **argv)
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{
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int g,rep;
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// Set up gpi pointer for direct register access
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cmgp = setup_io(ARM_PERI_BASE + CMGP_OFFSET);
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gpio = setup_io(ARM_PERI_BASE + GPIO_OFFSET);
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// Set Clock Manager to provivede ~1.8432 MHz from 500 MHz source (PLLD)
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CMGP_REG(CM_GP0CTL) = (0x5A << 24) // Password
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// Disable
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| (1); // Src = oscillator
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usleep(1000);
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CMGP_REG(CM_GP0CTL) = (0x5A << 24) // Password
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// Disable
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| (6); // Src = PLLD
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CMGP_REG(CM_GP0DIV) = (0x5A << 24) // Password
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| (271 << 12); // IDIV
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usleep(1000);
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CMGP_REG(CM_GP0CTL) = (0x5A << 24) // Password
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| (1 << 4) // Enable
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| (6); // Src = PLLD
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usleep(1000);
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// Set GCLK function (ALT0) for GPIO 4 (header pin #7)
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INP_GPIO(4);
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SET_GPIO_ALT(4, 0x00);
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return 0;
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}
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