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updated notes, fixing what seems to a mistake on the webpage I referenced
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@ -14,11 +14,15 @@ document some of the "why".
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What follows is an attempt to "find the patterns" in the cycle times (as
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given on http://www.6502.org/tutorials/6502opcodes.html )
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There are 12 classes of instructions when it comes to cycle times:
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NOTE: there appears to be an error in AND and ORA zero page timings on that
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webpage given above. I've now corrected this below.
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There are 11 classes of instructions when it comes to cycle times:
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Class Ia
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(followed by ADC, BIT, CMP, CPX, CPY, EOR, LDA, LDX, LDY, SBC, STX, STY)
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(followed by ADC, AND, BIT, CMP, CPX, CPY, EOR, LDA, LDX, LDY, ORA, SBC, STX,
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STY)
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immediate 2
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zero page 3
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@ -52,23 +56,6 @@ page cross even if there isn't.
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Question 1: why is this?
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Class Ic
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(followed by AND, ORA)
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immediate 2
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zero page 2
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zero page, x 3
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absolute 4
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absolute, x 4 (+1 if page crossed)
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absolute, y 4 (+1 if page crossed)
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indirect, x 6
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indirect, y 5 (+1 if page crossed)
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Note 3: just like class Ia except the zero page are a cycle faster
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Question 2: why is this? is it a bug on the webpage?
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Class II
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(followed by ASL, DEC, INC, LSR, ROL, ROR)
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@ -80,7 +67,7 @@ absolute, x 7
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Note 4: looks like class Ib + 2 in the non-implied cases
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Question 3: why does absolute, x not have a page crossing addition? same
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Question 2: why does absolute, x not have a page crossing addition? same
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reason as for Ib?
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