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implemented non-accumulator version of ROR
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parent
8f10724a7f
commit
777266f8e1
@ -456,11 +456,18 @@ class CPU:
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m = m | 0x01
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m = m | 0x01
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self.memory.write_byte(operand_address,self.update_nzc(m))
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self.memory.write_byte(operand_address,self.update_nzc(m))
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def ROR(self):
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def ROR(self, operand_address=None):
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if operand_address is None:
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if self.carry_flag:
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if self.carry_flag:
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self.accumulator = self.accumulator | 0x100
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self.accumulator = self.accumulator | 0x100
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self.carry_flag = self.accumulator % 2
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self.carry_flag = self.accumulator % 2
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self.accumulator = self.update_nz(self.accumulator >> 1)
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self.accumulator = self.update_nz(self.accumulator >> 1)
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else:
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m = self.memory.read_byte(operand_address)
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if self.carry_flag:
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m = m | 0x100
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self.carry_flag = m % 2
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self.memory.write_byte(operand_address, self.update_nz(m >> 1))
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def LSR(self, operand_address=None):
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def LSR(self, operand_address=None):
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if operand_address is None:
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if operand_address is None:
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