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https://github.com/jtauber/applepy.git
synced 2024-11-26 16:49:32 +00:00
refactored memory access so cycle can be passed in
This commit is contained in:
James Tauber
parent
a92dcfecd3
commit
be91422317
83
applepy.py
83
applepy.py
@ -271,7 +271,7 @@ class SoftSwitches:
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self.kbd = 0x00
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self.display = display
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def read_byte(self, address):
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def read_byte(self, cycle, address):
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assert 0xC000 <= address <= 0xCFFF
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if address == 0xC000:
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return self.kbd
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@ -316,22 +316,22 @@ class Memory:
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if address < 0xC000:
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self.ram.load(address, data)
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def read_byte(self, address):
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def read_byte(self, cycle, address):
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if address < 0xC000:
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return self.ram.read_byte(address)
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elif address < 0xD000:
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return self.softswitches.read_byte(address)
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return self.softswitches.read_byte(cycle, address)
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else:
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return self.rom.read_byte(address)
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def read_word(self, address):
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return self.read_byte(address) + (self.read_byte(address + 1) << 8)
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def read_word(self, cycle, address):
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return self.read_byte(cycle, address) + (self.read_byte(cycle + 1, address + 1) << 8)
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def read_word_bug(self, address):
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def read_word_bug(self, cycle, address):
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if address % 0x100 == 0xFF:
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return self.read_byte(address) + (self.read_byte(address & 0xFF00) << 8)
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return self.read_byte(cycle, address) + (self.read_byte(cycle + 1, address & 0xFF00) << 8)
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else:
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return self.read_word(address)
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return self.read_word(cycle, address)
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def write_byte(self, address, value):
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if address < 0xC000:
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@ -743,7 +743,7 @@ class CPU:
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self.ops[0xFE] = lambda: self.INC(self.absolute_x_mode(rmw=True))
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def reset(self):
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self.program_counter = self.memory.read_word(self.RESET_VECTOR)
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self.program_counter = self.read_word(self.RESET_VECTOR)
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def run(self):
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update_cycle = 0
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@ -799,11 +799,20 @@ class CPU:
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self.program_counter += inc
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return pc
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def read_byte(self, address):
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return self.memory.read_byte(self.cycles, address)
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def read_word(self, address):
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return self.memory.read_word(self.cycles, address)
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def read_word_bug(self, address):
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return self.memory.read_word_bug(self.cycles, address)
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def read_pc_byte(self):
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return self.memory.read_byte(self.get_pc())
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return self.read_byte(self.get_pc())
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def read_pc_word(self):
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return self.memory.read_word(self.get_pc(2))
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return self.read_word(self.get_pc(2))
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####
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@ -827,7 +836,7 @@ class CPU:
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def pull_byte(self):
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self.stack_pointer = (self.stack_pointer + 1) % 0x100
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return self.memory.read_byte(self.STACK_PAGE + self.stack_pointer)
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return self.read_byte(self.STACK_PAGE + self.stack_pointer)
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def push_word(self, word):
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hi, lo = divmod(word, 0x100)
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@ -837,7 +846,7 @@ class CPU:
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def pull_word(self):
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s = self.STACK_PAGE + self.stack_pointer + 1
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self.stack_pointer += 2
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return self.memory.read_word(s)
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return self.read_word(s)
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####
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@ -872,22 +881,22 @@ class CPU:
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def indirect_mode(self):
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self.cycles += 2
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return self.memory.read_word_bug(self.absolute_mode())
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return self.read_word_bug(self.absolute_mode())
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def indirect_x_mode(self):
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self.cycles += 4
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return self.memory.read_word_bug((self.read_pc_byte() + self.x_index) % 0x100)
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return self.read_word_bug((self.read_pc_byte() + self.x_index) % 0x100)
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def indirect_y_mode(self, rmw=False):
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if rmw:
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self.cycles += 4
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else:
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self.cycles += 3
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return self.memory.read_word_bug(self.read_pc_byte()) + self.y_index
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return self.read_word_bug(self.read_pc_byte()) + self.y_index
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def relative_mode(self):
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pc = self.get_pc()
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return pc + 1 + signed(self.memory.read_byte(pc))
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return pc + 1 + signed(self.read_byte(pc))
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####
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@ -906,13 +915,13 @@ class CPU:
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# LOAD / STORE
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def LDA(self, operand_address):
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self.accumulator = self.update_nz(self.memory.read_byte(operand_address))
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self.accumulator = self.update_nz(self.read_byte(operand_address))
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def LDX(self, operand_address):
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self.x_index = self.update_nz(self.memory.read_byte(operand_address))
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self.x_index = self.update_nz(self.read_byte(operand_address))
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def LDY(self, operand_address):
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self.y_index = self.update_nz(self.memory.read_byte(operand_address))
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self.y_index = self.update_nz(self.read_byte(operand_address))
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def STA(self, operand_address):
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self.memory.write_byte(operand_address, self.accumulator)
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@ -950,7 +959,7 @@ class CPU:
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self.accumulator = self.update_nzc(self.accumulator << 1)
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else:
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self.cycles += 2
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self.memory.write_byte(operand_address, self.update_nzc(self.memory.read_byte(operand_address) << 1))
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self.memory.write_byte(operand_address, self.update_nzc(self.read_byte(operand_address) << 1))
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def ROL(self, operand_address=None):
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if operand_address is None:
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@ -960,7 +969,7 @@ class CPU:
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self.accumulator = self.update_nzc(a)
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else:
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self.cycles += 2
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m = self.memory.read_byte(operand_address) << 1
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m = self.read_byte(operand_address) << 1
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if self.carry_flag:
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m = m | 0x01
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self.memory.write_byte(operand_address, self.update_nzc(m))
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@ -973,7 +982,7 @@ class CPU:
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self.accumulator = self.update_nz(self.accumulator >> 1)
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else:
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self.cycles += 2
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m = self.memory.read_byte(operand_address)
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m = self.read_byte(operand_address)
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if self.carry_flag:
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m = m | 0x100
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self.carry_flag = m % 2
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@ -985,8 +994,8 @@ class CPU:
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self.accumulator = self.update_nz(self.accumulator >> 1)
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else:
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self.cycles += 2
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self.carry_flag = self.memory.read_byte(operand_address) % 2
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self.memory.write_byte(operand_address, self.update_nz(self.memory.read_byte(operand_address) >> 1))
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self.carry_flag = self.read_byte(operand_address) % 2
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self.memory.write_byte(operand_address, self.update_nz(self.read_byte(operand_address) >> 1))
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# JUMPS / RETURNS
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@ -1072,7 +1081,7 @@ class CPU:
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def DEC(self, operand_address):
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self.cycles += 2
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self.memory.write_byte(operand_address, self.update_nz(self.memory.read_byte(operand_address) - 1))
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self.memory.write_byte(operand_address, self.update_nz(self.read_byte(operand_address) - 1))
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def DEX(self):
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self.x_index = self.update_nz(self.x_index - 1)
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@ -1082,7 +1091,7 @@ class CPU:
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def INC(self, operand_address):
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self.cycles += 2
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self.memory.write_byte(operand_address, self.update_nz(self.memory.read_byte(operand_address) + 1))
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self.memory.write_byte(operand_address, self.update_nz(self.read_byte(operand_address) + 1))
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def INX(self):
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self.x_index = self.update_nz(self.x_index + 1)
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@ -1111,13 +1120,13 @@ class CPU:
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# LOGIC
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def AND(self, operand_address):
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self.accumulator = self.update_nz(self.accumulator & self.memory.read_byte(operand_address))
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self.accumulator = self.update_nz(self.accumulator & self.read_byte(operand_address))
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def ORA(self, operand_address):
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self.accumulator = self.update_nz(self.accumulator | self.memory.read_byte(operand_address))
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self.accumulator = self.update_nz(self.accumulator | self.read_byte(operand_address))
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def EOR(self, operand_address):
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self.accumulator = self.update_nz(self.accumulator ^ self.memory.read_byte(operand_address))
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self.accumulator = self.update_nz(self.accumulator ^ self.read_byte(operand_address))
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# ARITHMETIC
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@ -1127,7 +1136,7 @@ class CPU:
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a2 = self.accumulator
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a1 = signed(a2)
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m2 = self.memory.read_byte(operand_address)
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m2 = self.read_byte(operand_address)
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m1 = signed(m2)
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# twos complement addition
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@ -1147,7 +1156,7 @@ class CPU:
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a2 = self.accumulator
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a1 = signed(a2)
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m2 = self.memory.read_byte(operand_address)
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m2 = self.read_byte(operand_address)
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m1 = signed(m2)
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# twos complement subtraction
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@ -1165,7 +1174,7 @@ class CPU:
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# BIT
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def BIT(self, operand_address):
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value = self.memory.read_byte(operand_address)
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value = self.read_byte(operand_address)
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self.sign_flag = ((value >> 7) % 2) # bit 7
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self.overflow_flag = ((value >> 6) % 2) # bit 6
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self.zero_flag = [0, 1][((self.accumulator & value) == 0)]
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@ -1173,17 +1182,17 @@ class CPU:
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# COMPARISON
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def CMP(self, operand_address):
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result = self.accumulator - self.memory.read_byte(operand_address)
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result = self.accumulator - self.read_byte(operand_address)
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self.carry_flag = [0, 1][(result >= 0)]
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self.update_nz(result)
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def CPX(self, operand_address):
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result = self.x_index - self.memory.read_byte(operand_address)
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result = self.x_index - self.read_byte(operand_address)
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self.carry_flag = [0, 1][(result >= 0)]
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self.update_nz(result)
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def CPY(self, operand_address):
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result = self.y_index - self.memory.read_byte(operand_address)
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result = self.y_index - self.read_byte(operand_address)
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self.carry_flag = [0, 1][(result >= 0)]
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self.update_nz(result)
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@ -1196,7 +1205,7 @@ class CPU:
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self.cycles += 5
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self.push_word(self.program_counter + 1)
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self.push_byte(self.status_as_byte())
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self.program_counter = self.memory.read_word(0xFFFE)
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self.program_counter = self.read_word(0xFFFE)
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self.break_flag = 1
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def RTI(self):
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