Port from py6502 to py65 since it is more mature and has fewer CPU
bugs.
Implement basic support for parts of the apple II memory map
- 64K address space is assembled from multiple memory regions
- a memory region can optionally intercept reads and/or writes
- memory regions may be marked non-writable (this has a bug and isn't
yet working)
- execution handler can intercept execution to defined entry points
when PC enters a memory region
- can trap when PC enters a memory region to an unhandled entry point
- basic support for some IO page soft switches and status registers
- mostly just printing an event
- support loading boot1 image from sqlite DB
- load and install bits of the apple IIe ROM
- but I don't think I have got all of the important bits from the
image yet -- e.g. the CXROM image at alternate $C100 is not yet
installed
This commit is contained in:
kris
parent
9f8538b5dc
commit
aadc97efcb
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@ -0,0 +1,97 @@
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from py65 import memory
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from collections import defaultdict
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class WriteProtectedException(Exception):
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def __init__(self, name, addr, value):
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self.name = name
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self.addr = addr
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self.value = value
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def __str__(self):
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return 'Write denied to %s ($%04X): $%02X' % (self.name, self.addr, self.value)
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class UndefinedEntryPointException(Exception):
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def __init__(self, region, prev_addr, addr):
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self.region = region
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self.prev_addr = prev_addr
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self.addr = addr
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def __str__(self):
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return 'Entered region %s via undefined entry point: $%04X --> $%04X' % (
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self.region.name, self.prev_addr, self.addr)
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class MemoryManager(object):
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def __init__(self, memory_map):
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self.entrypoints = defaultdict(list)
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default_region = MemoryRegion('default', 0x0, 0xffff)
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def _default_region():
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return default_region
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self.regions = defaultdict(_default_region)
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self.memory = memory.ObservableMemory()
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for region in memory_map:
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self.RegisterRegion(region)
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def MaybeInterceptExecution(self, cpu, old_pc):
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pc = cpu.pc
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if pc in self.entrypoints:
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handlers = self.entrypoints[pc]
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else:
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handlers = []
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if self.regions[old_pc] != self.regions[pc]:
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print "Entering region %s" % self.regions[pc].name
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if not handlers:
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raise UndefinedEntryPointException(self.regions[pc], old_pc, pc)
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for handler in handlers:
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handler(cpu)
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return
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def RegisterRegion(self, region):
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addr_range = xrange(region.start, region.end + 1)
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if region.read_interceptor:
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self.memory.subscribe_to_read(addr_range, region.read_interceptor)
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if region.write_interceptor:
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self.memory.subscribe_to_write(addr_range, region.write_interceptor)
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if not region.writable:
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self.memory.subscribe_to_write(addr_range, self.DenyWritesToRegion(region))
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for addr in addr_range:
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self.regions[addr] = region
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for addr, handler in region.entrypoints.iteritems():
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self.entrypoints[addr].append(handler)
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# TODO: should trap by default
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@staticmethod
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def DenyWritesToRegion(region):
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def _DenyWritesInterceptor(addr, value):
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raise WriteProtectedException(region.name, addr, value)
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return _DenyWritesInterceptor
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class MemoryRegion(object):
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def __init__(
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self, name, start, end, read_interceptor=None, write_interceptor=None, entrypoints=None,
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writable=True):
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self.name = name
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self.start = start
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self.end = end
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self.read_interceptor = read_interceptor
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self.write_interceptor = write_interceptor
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self.writable = writable
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# Maps PC to handler
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self.entrypoints = entrypoints or {}
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218
sim_apple2.py
218
sim_apple2.py
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@ -1,55 +1,217 @@
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"""Partial simulation of Apple II"""
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import sqlite3
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import memory
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from py65.devices import mpu65c02
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from py65 import memory
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DB_PATH = '/tank/apple2/data/apple2.db'
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MODE_READ = 0x1
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MODE_WRITE = 0x2
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MODE_RW = MODE_READ | MODE_WRITE
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class Event(object):
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def __init__(self, event_type, details):
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self.event_type = event_type
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self.details = details
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def __str__(self):
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return "Event(%s): %s" % (self.event_type, self.details)
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def _Event(region, message):
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def _Event(cpu):
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print "%s event: %s" % (region, message)
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return _Event
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class TrapException(Exception):
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def __init__(self, address, msg):
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self.address = address
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self.msg = msg
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def __str__(self):
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return "$%04X: %s" % (self.address, self.msg)
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class AppleII(object):
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def __init__(self):
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# TODO: should trap by default
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self.memory = memory.ObservableMemory()
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memory_map = [
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memory.MemoryRegion("Zero page", 0x0000, 0x00ff),
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memory.MemoryRegion("Stack", 0x0100, 0x01ff),
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memory.MemoryRegion(
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"Text page 1", 0x0400, 0x7ff,
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write_interceptor=self.TextPageWriteInterceptor),
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memory.MemoryRegion(
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"IO page", 0xc000, 0xc0ff, read_interceptor=self.IOInterceptor,
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write_interceptor=self.IOInterceptor),
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memory.MemoryRegion("Slot 1 ROM", 0xc100, 0xc1ff, writable=False),
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memory.MemoryRegion("Slot 2 ROM", 0xc200, 0xc2ff, writable=False),
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memory.MemoryRegion("Slot 3 ROM", 0xc300, 0xc3ff, writable=False),
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memory.MemoryRegion("Slot 4 ROM", 0xc400, 0xc4ff, writable=False),
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memory.MemoryRegion("Slot 5 ROM", 0xc500, 0xc5ff, writable=False),
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memory.MemoryRegion("Slot 6 ROM", 0xc600, 0xc6ff,
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entrypoints={
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0xc65c: self._ReadDiskSector
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},
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writable=False
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),
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memory.MemoryRegion("Slot 7 ROM", 0xc700, 0xc7ff, writable=False),
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memory.MemoryRegion(
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"ROM", 0xd000, 0xffff,
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entrypoints={
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0xfca8: self._Wait,
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0xfe89: _Event("ROM", "Select the keyboard (IN#0)")
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},
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writable=False
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)
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]
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self.memory_manager = memory.MemoryManager(memory_map)
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self.memory = self.memory_manager.memory
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self.cpu = mpu65c02.MPU(memory=self.memory)
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# Set up interceptors for accessing various interesting parts of the memory map
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# Text page 1
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self.memory.subscribe_to_write(xrange(0x400, 0x7ff), self.TextPageWriteInterceptor)
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self.io_map = {
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0xc007: (MODE_WRITE, "Turn CXROM switch on"),
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0xc015: (MODE_READ, "Status of Peripheral/CXROM Access"),
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self.memory.subscribe_to_write(xrange(0xc000, 0xffff), self.TraceWriteInterceptor)
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self.memory.subscribe_to_read(xrange(0xc000, 0xffff), self.TraceReadInterceptor)
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0xc051: (MODE_READ, "Display text"),
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0xc054: (MODE_READ, "Text page 1"),
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0xc056: (MODE_READ, "Enter lores mode"),
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# Slot 6 Disk II
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0xc0e0: (MODE_READ, "phase 0 off"),
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0xc0e1: (MODE_READ, "phase 0 on"),
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0xc0e2: (MODE_READ, "phase 1 off"),
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0xc0e3: (MODE_READ, "phase 1 on"),
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0xc0e4: (MODE_READ, "phase 2 off"),
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0xc0e5: (MODE_READ, "phase 2 on"),
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0xc0e6: (MODE_READ, "phase 3 off"),
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0xc0e7: (MODE_READ, "phase 3 on"),
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0xc0e8: (MODE_READ, "Drives off"),
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0xc0e9: (MODE_READ, "Selected drive on"),
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0xc0ea: (MODE_READ, "Select drive 1"),
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0xc0eb: (MODE_READ, "Select drive 2"),
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0xc0ec: (MODE_READ, "Shift while writing/read data"),
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0xc0ed: (MODE_READ, "Shift while writing/read data"),
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0xc0ee: (MODE_READ, "Enabling disk read mode."),
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0xc0ef: (MODE_READ, "Enabling disk write mode."),
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}
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# Need the ability to intercept execution, e.g. for the C65C sector read routine.
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def IOInterceptor(self, address, value=None):
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access_mode = MODE_READ if (value == None) else MODE_WRITE
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try:
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(mode, result) = self.io_map[address]
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if access_mode & mode:
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print "==== IO EVENT: %s" % result
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else:
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print "**** IO EVENT with unexpected mode: %s" % result
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except KeyError:
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if value:
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print TrapException(address, 'Wrote %02X ("%s")' % (value, chr(value)))
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else:
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print TrapException(address, 'Read')
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def _ReadDiskSector(self, cpu):
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print "Read disk sector from Track $%02X Sector $%02X" % (self.memory[0x41], self.memory[0x3d])
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cpu.pc = 0x801
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def _Wait(self, cpu):
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print "Waiting"
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# TODO: convert addresses to screen coordinates
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# See e.g. https://retrocomputing.stackexchange.com/questions/2534/what-are-the-screen-holes-in-apple-ii-graphics
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def TextPageWriteInterceptor(self, address, value):
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print 'Wrote "%s" to text page address $%04X' % (chr(value & 0x7f), address)
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def TraceWriteInterceptor(self, address, value):
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print 'Wrote "%s" to address $%04X' % (chr(value), address)
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def TraceReadInterceptor(self, address):
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print 'Read from address $%04X' % address
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def Run(self, pc):
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def Run(self, pc, trace=False):
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self.cpu.pc = pc
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old_pc = self.cpu.pc
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while True:
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self.cpu.step(trace=False)
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if self.cpu.pc == pc:
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self.memory_manager.MaybeInterceptExecution(self.cpu, old_pc)
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old_pc = self.cpu.pc
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self.cpu.step(trace=trace)
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if self.cpu.pc == old_pc:
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break
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pc = self.cpu.pc
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def main():
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conn = sqlite3.connect(DB_PATH)
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cursor = conn.cursor()
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boot1 = [
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0x01, 0x8d, 0xe8, 0xc0, 0x8d, 0x51, 0xc0, 0x8d, 0x54, 0xc0, 0xa0, 0x00, 0xa9, 0xa0, 0x99, 0x00,
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0x04, 0x99, 0x00, 0x05, 0x99, 0x00, 0x06, 0x99, 0x00, 0x07, 0xc8, 0xd0, 0xf1, 0xa9, 0x08, 0x85,
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0x01, 0xa9, 0x33, 0x85, 0x00, 0xb1, 0x00, 0xf0, 0x08, 0x09, 0x80, 0x99, 0xaf, 0x05, 0xc8, 0xd0,
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0xec, 0xf0, 0xfe, 0x54, 0x48, 0x49, 0x53, 0x20, 0x44, 0x49, 0x53, 0x4b, 0x20, 0x48, 0x41, 0x53,
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0x20, 0x4e, 0x4f, 0x20, 0x42, 0x4f, 0x4f, 0x54, 0x20, 0x43, 0x4f, 0x44, 0x45, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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]
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# Load the most popular boot1
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# q = cursor.execute(
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# """
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# select boot1_sha1, boot1.data, count(*) from disks
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# join
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# (select sha1, data from boot1) as boot1
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# on disks.boot1_sha1 = boot1.sha1 group by 1 order by 3 desc limit 1
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# """
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# )
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# Dos 3.3
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q = cursor.execute(
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"""
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select data from boot1 where sha1 = '7ab36247fdf62e87f98d2964dd74d6572d17fff0'
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"""
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)
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for r in q:
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(boot1,) = r
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#
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# # boot1 image that prints stuff to the text page without using ROM entrypoints
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# q = cursor.execute(
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# """
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# select data from boot1 where sha1 = '62bda735bcb4a27ffbd833ebb4ff2503b983ea97'
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# """
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# )
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for r in q:
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(boot1,) = r
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apple2 = AppleII()
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apple2.memory[0x800:0x800+len(boot1)] = boot1
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apple2.Run(0x801)
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# Read in Apple IIE ROM image
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rom = bytearray(open("APPLE2E.ROM", "r").read())
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# XXX these should write-trap
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# Slot 6 ROM
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apple2.memory[0xc600:0xc6ff] = rom[0x0600:0x6ff]
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# Main ROM
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apple2.memory[0xd000:0xffff] = rom[0x5000:0x7fff]
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# TODO: why does this not use the 6502 reset vector?
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apple2.cpu.reset()
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apple2.memory[0x800:0x800 + len(boot1)] = bytearray(boot1)
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# Disk II firmware stores next page load address here
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apple2.memory[0x26] = 0x00
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apple2.memory[0x27] = 0x09
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# "3" is used for controller ID
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apple2.memory[0x3c] = 0x03
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# Sector to read
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apple2.memory[0x3d] = 0x00
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# Track to read
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apple2.memory[0x41] = 0x00
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# Booting from slot 6
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apple2.memory[0x2b] = 0x60
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#apple2.Run(0xfa62) # Target of 6502 reset vector
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apple2.Run(0x801, trace=True)
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if __name__ == '__main__':
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main()
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main()
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