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Stefan ArentzandClaude Fable 5
43709fe907
The port had inverted the C ownership chain: the Cpu held no memory, and One/Two implemented a Bus trait and pattern-matched addresses to their peripherals inline. This puts the mem.c design back: - New ewm-core/src/mem.rs: Memory is the mem.c region table — a base-RAM fast path (addr < ram_size) plus RAM/ROM/Device regions walked newest-first (the C list-prepend order). Devices implement the Device trait (the cpu_add_iom handlers + obj pointer) and get the absolute address; typed DeviceHandles give machines access to their peripherals afterwards. - Cpu owns the Memory; step/reset/irq/nmi lose the bus parameter and instruction handlers land on the C typedef shapes (fn(&mut Cpu), fn(&mut Cpu, u8), fn(&mut Cpu, u16)). Cpu::step stamps mem.cycles from counter, replacing the Two.cycles mirror every run loop had to maintain. - Machines shrink to composition, as in ewm_one_init/ewm_two_init: One = RAM + ROM + Pia; Two = RAM + TwoIo (the $C000-$C07F soft switches, moved out of Two with the state they own) + Alc (which now owns the machine ROM it shadows, covering $C08x and $D000-$FFFF) + Dsk + the slot 6 boot ROM region. - The Bus trait and TestBus are gone; CPU tests and benches use a flat 64K Memory, which is what cpu_test.c set up. Zero behavior change: all golden gates pass unchanged (Dormann 6502 + 65C02, the 100k golden trace, machine boots, DOS 3.3 boot + CATALOG, golden screenshot). One documented alignment: One's --memory extras now lose to base RAM like the C fast path (REWRITE.md). Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>