Files
ewm/rust/Cargo.lock
Stefan ArentzandClaude Fable 5 8c158618d5 Phase 2: 65C02, disassembler, and golden-trace harness (#192)
Completes the CPU core port:

- ins.rs: the 65C02 override handlers ((zp) modes, BRA, STZ, PHX/PHY/
  PLX/PLY, TRB/TSB, RMB/SMB, BBR/BBS, INC/DEC A, BIT imm/zpgx/absx,
  JMP (abs,X)) and the override table transcribed verbatim from
  instructions_65C02 — including its 1-cycle NOPs and the stray 0x03
  opcode fields. The table is overlaid onto the 6502 table once, the
  Rust version of cpu_initialize()'s back-fill. C's arity-cast NOPs
  become explicit nop_byte/nop_word wrappers.
- fmt.rs: cpu_format_state, cpu_format_stack, and the disassembler
  from fmt.c, bugs preserved (0x9c prints JMP; BBR/BBS targets are
  computed from pc+2).
- tests/dormann.rs: dormann_65c02 passes at $24a8 after 65,094,140
  cycles — exactly the C emulator's count.
- Golden-trace harness: scripts/gen-golden-trace.{c,sh} builds a
  capture program against the unmodified C sources and records the
  first 100k instructions of the functional test as normalized
  'PC A X Y SP P' lines; checked in gzipped. trace_compare.rs replays
  it on the Rust core and reports the first divergent instruction
  (currently: zero divergence). flate2 is a dev-dependency only.

Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
2026-07-05 09:16:20 -04:00

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