izapple2/cardSaturn.go

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package izapple2
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/*
RAM card with 128Kb. It's like 8 language cards.
See:
http://www.applelogic.org/files/SATURN128MAN.pdf
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*/
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// CardSaturn is a Saturn128 card
type CardSaturn struct {
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cardBase
readState bool
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writeState uint8
altBank bool
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activeBlock uint8
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}
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// NewCardSaturn creates a new CardSaturn
func NewCardSaturn() *CardSaturn {
var c CardSaturn
c.name = "Saturn 128KB Ram Card"
return &c
}
const (
saturnBlocks = 8
)
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func (c *CardSaturn) assign(a *Apple2, slot int) {
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c.readState = false
c.writeState = lcWriteEnabled
c.altBank = true
c.activeBlock = 0
a.mmu.initLanguageRAM(saturnBlocks)
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// TODO: use addCardSoftSwitches()
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for i := uint8(0x0); i <= 0xf; i++ {
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iCopy := i
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c.addCardSoftSwitchR(iCopy, func(*ioC0Page) uint8 {
c.ssAction(iCopy)
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return 0
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}, "SATURNR")
c.addCardSoftSwitchW(iCopy, func(*ioC0Page, uint8) {
c.ssAction(iCopy)
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}, "SATURNW")
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}
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c.cardBase.assign(a, slot)
c.applyState()
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}
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func (c *CardSaturn) ssAction(ss uint8) {
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switch ss {
case 0:
// RAM read, no writes
c.altBank = false
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c.readState = true
c.writeState = lcWriteDisabled
case 1:
// ROM read, RAM write
c.altBank = false
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c.readState = false
c.writeState++
case 2:
// ROM read, no writes
c.altBank = false
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c.readState = false
c.writeState = lcWriteDisabled
case 3:
//RAM read, RAM write
c.altBank = false
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c.readState = true
c.writeState++
case 4:
c.activeBlock = 0
case 5:
c.activeBlock = 1
case 6:
c.activeBlock = 2
case 7:
c.activeBlock = 3
case 8:
// RAM read, no writes
c.altBank = true
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c.readState = true
c.writeState = lcWriteDisabled
case 9:
// ROM read, RAM write
c.altBank = true
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c.readState = false
c.writeState++
case 10:
// ROM read, no writes
c.altBank = true
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c.readState = false
c.writeState = lcWriteDisabled
case 11:
//RAM read, RAM write
c.altBank = true
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c.readState = true
c.writeState++
case 12:
c.activeBlock = 4
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case 13:
c.activeBlock = 5
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case 14:
c.activeBlock = 6
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case 15:
c.activeBlock = 7
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}
if c.writeState > lcWriteEnabled {
c.writeState = lcWriteEnabled
}
c.applyState()
}
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func (c *CardSaturn) applyState() {
c.a.mmu.setLanguageRAMActiveBlock(c.activeBlock)
c.a.mmu.setLanguageRAM(c.readState, c.writeState == lcWriteEnabled, c.altBank)
}