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https://github.com/ivanizag/izapple2.git
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traceBBC fixes
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parent
3c9c3b7625
commit
5d710b36ae
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@ -43,7 +43,7 @@ func newTraceApplecorn(a *Apple2, skipConsole bool) *traceApplecorn {
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t.osbyteNames[0x7d] = "set escape condition"
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t.osbyteNames[0x7d] = "set escape condition"
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t.osbyteNames[0x7e] = "ack detection of ESC"
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t.osbyteNames[0x7e] = "ack detection of ESC"
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t.osbyteNames[0x7f] = "check for end-of-file on an opened file"
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t.osbyteNames[0x7f] = "check for end-of-file on an opened file"
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t.osbyteNames[0x90] = "read ADC channel"
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t.osbyteNames[0x80] = "read ADC channel"
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t.osbyteNames[0x81] = "read key with time lim"
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t.osbyteNames[0x81] = "read key with time lim"
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t.osbyteNames[0x82] = "read high order address"
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t.osbyteNames[0x82] = "read high order address"
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t.osbyteNames[0x83] = "read bottom of user mem"
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t.osbyteNames[0x83] = "read bottom of user mem"
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@ -56,8 +56,13 @@ func newTraceApplecorn(a *Apple2, skipConsole bool) *traceApplecorn {
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}
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}
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func (t *traceApplecorn) inspect() {
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func (t *traceApplecorn) inspect() {
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pc, _ := t.a.cpu.GetPCAndSP()
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if !t.a.mmu.altMainRAMActiveRead {
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inKernel := pc >= applecornKernelStart && t.a.mmu.altMainRAMActiveRead
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// We want to trace only the activity on the Acorn memory space
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return
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}
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pc, sp := t.a.cpu.GetPCAndSP()
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inKernel := pc >= applecornKernelStart
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if !t.wasInKernel && inKernel {
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if !t.wasInKernel && inKernel {
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regA, regX, regY, _ := t.a.cpu.GetAXYP()
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regA, regX, regY, _ := t.a.cpu.GetAXYP()
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@ -89,6 +94,8 @@ func (t *traceApplecorn) inspect() {
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pc = 0xffd1
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pc = 0xffd1
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case t.vector(0x021C): // OSFIND vector
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case t.vector(0x021C): // OSFIND vector
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pc = 0xffce
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pc = 0xffce
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case t.vector(0xfffe): // BRK vector
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pc = 0xfffe
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}
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}
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// Jump area
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// Jump area
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@ -140,7 +147,11 @@ func (t *traceApplecorn) inspect() {
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s = "OSRDCH()"
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s = "OSRDCH()"
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skip = t.skipConsole
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skip = t.skipConsole
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case 0xffe3: // This fallbacks to OSWRCH
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case 0xffe3: // This fallbacks to OSWRCH
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s = "OSASCI(?)"
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ch := ""
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if regA >= 0x20 && regA < 0x7f {
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ch = string(regA)
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}
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s = fmt.Sprintf("OSASCI(A=%02x, '%v')", regA, ch)
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skip = t.skipConsole
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skip = t.skipConsole
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case 0xffe7: // This fallbacks to OSWRCH
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case 0xffe7: // This fallbacks to OSWRCH
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s = "OSNEWL()"
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s = "OSNEWL()"
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@ -171,6 +182,12 @@ func (t *traceApplecorn) inspect() {
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xy := uint16(regX) + uint16(regY)<<8
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xy := uint16(regX) + uint16(regY)<<8
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command := t.getTerminatedString(xy, 0x0d)
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command := t.getTerminatedString(xy, 0x0d)
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s = fmt.Sprintf("OSCLI(\"%s\")", command)
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s = fmt.Sprintf("OSCLI(\"%s\")", command)
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case 0xfffe:
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address := t.a.mmu.peekWord(0x100+uint16(sp+2)) - 1
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faultNumber := t.a.mmu.Peek(address)
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faultMessage := address + 1
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faultString := t.getTerminatedString(faultMessage, 0)
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s = fmt.Sprintf("BRK(number=%v,message='%s')", faultNumber, faultString)
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}
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}
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if s == "UNKNOWN" && t.skipConsole {
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if s == "UNKNOWN" && t.skipConsole {
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@ -198,8 +215,8 @@ func (t *traceApplecorn) inspect() {
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switch t.call.a {
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switch t.call.a {
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case 0: // Read line from input
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case 0: // Read line from input
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lineAddress := t.a.mmu.peekWord(cbAddress)
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lineAddress := t.a.mmu.peekWord(cbAddress)
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line := t.getString(lineAddress, regY)
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line := t.getTerminatedString(lineAddress, '\r')
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s = fmt.Sprintf(",line='%s'", line)
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s = fmt.Sprintf(",line='%s',cbaddress=%04x,lineAddress=%04x", line, cbAddress, lineAddress)
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}
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}
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}
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}
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@ -209,15 +226,6 @@ func (t *traceApplecorn) inspect() {
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t.wasInKernel = inKernel
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t.wasInKernel = inKernel
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}
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}
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func (t *traceApplecorn) getString(address uint16, length uint8) string {
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s := ""
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for i := uint8(0); i < length; i++ {
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ch := t.a.mmu.Peek(address + uint16(i))
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s = s + string(ch)
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}
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return s
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}
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func (t *traceApplecorn) getTerminatedString(address uint16, terminator uint8) string {
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func (t *traceApplecorn) getTerminatedString(address uint16, terminator uint8) string {
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s := ""
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s := ""
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for {
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for {
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