mirror of
https://github.com/ivanizag/izapple2.git
synced 2024-06-12 20:29:45 +00:00
Added the -traceCpu and -traceSS command line switches.
This commit is contained in:
parent
43a5980fd3
commit
68b949d871
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@ -122,6 +122,11 @@ Only valid on SDL mode
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main rom file (default "<internal>/Apple2_Plus.rom")
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main rom file (default "<internal>/Apple2_Plus.rom")
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-saturnCardSlot int
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-saturnCardSlot int
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slot for the 256kb Saturn card. -1 for none (default -1)
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slot for the 256kb Saturn card. -1 for none (default -1)
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-traceCpu
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dump to the console the CPU execution
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-traceSS
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dump to the console the sofswitches calls
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```
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```
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## Building from source
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## Building from source
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@ -20,7 +20,6 @@ type Apple2 struct {
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cg *CharacterGenerator
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cg *CharacterGenerator
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cards [8]card
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cards [8]card
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isApple2e bool
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isApple2e bool
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panicSS bool
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commandChannel chan int
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commandChannel chan int
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cycleDurationNs float64 // Current speed. Inverse of the cpu clock in Ghz
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cycleDurationNs float64 // Current speed. Inverse of the cpu clock in Ghz
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isColor bool
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isColor bool
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@ -37,14 +36,14 @@ const (
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const maxWaitDuration = 100 * time.Millisecond
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const maxWaitDuration = 100 * time.Millisecond
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// Run starts the Apple2 emulation
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// Run starts the Apple2 emulation
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func (a *Apple2) Run(log bool) {
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func (a *Apple2) Run() {
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// Start the processor
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// Start the processor
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a.cpu.Reset()
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a.cpu.Reset()
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referenceTime := time.Now()
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referenceTime := time.Now()
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for {
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for {
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// Run a 6502 step
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// Run a 6502 step
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a.cpu.ExecuteInstruction(log && a.cycleDurationNs != 0)
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a.cpu.ExecuteInstruction()
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// Execute meta commands
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// Execute meta commands
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commandsPending := true
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commandsPending := true
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@ -4,7 +4,7 @@ import "github.com/ivanizag/apple2/core6502"
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// NewApple2 instantiates an apple2
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// NewApple2 instantiates an apple2
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func NewApple2(charRomFile string, clockMhz float64,
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func NewApple2(charRomFile string, clockMhz float64,
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isColor bool, fastMode bool, panicSS bool) *Apple2 {
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isColor bool, fastMode bool) *Apple2 {
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var a Apple2
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var a Apple2
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a.Name = "Apple ][+"
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a.Name = "Apple ][+"
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@ -16,7 +16,6 @@ func NewApple2(charRomFile string, clockMhz float64,
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a.commandChannel = make(chan int, 100)
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a.commandChannel = make(chan int, 100)
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a.isColor = isColor
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a.isColor = isColor
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a.fastMode = fastMode
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a.fastMode = fastMode
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a.panicSS = panicSS
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if clockMhz <= 0 {
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if clockMhz <= 0 {
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// Full speed
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// Full speed
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@ -16,7 +16,7 @@ func main() {
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a.SetKeyboardProvider(fe)
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a.SetKeyboardProvider(fe)
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go fe.textModeGoRoutine(a)
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go fe.textModeGoRoutine(a)
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a.Run(false)
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a.Run()
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}
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}
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/*
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/*
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@ -53,7 +53,18 @@ func MainApple() *Apple2 {
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panicSS := flag.Bool(
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panicSS := flag.Bool(
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"panicss",
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"panicss",
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false,
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false,
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"panic if a not implemented softswitch is used")
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"panic if a not implemented softswitch is used",
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)
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traceCPU := flag.Bool(
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"traceCpu",
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false,
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"dump to the console the CPU execution operations",
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)
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traceSS := flag.Bool(
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"traceSS",
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false,
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"dump to the console the sofswitches calls",
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)
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dumpChars := flag.Bool(
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dumpChars := flag.Bool(
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"dumpChars",
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"dumpChars",
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false,
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false,
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@ -66,7 +77,12 @@ func MainApple() *Apple2 {
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)
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)
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flag.Parse()
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flag.Parse()
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a := NewApple2(*charRomFile, *cpuClock, !*mono, *fastDisk, *panicSS)
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a := NewApple2(*charRomFile, *cpuClock, !*mono, *fastDisk)
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a.cpu.SetTrace(*traceCPU)
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a.io.setTrace(*traceSS)
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a.io.setPanicNotImplemented(*panicSS)
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if *base64a {
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if *base64a {
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NewBase64a(a)
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NewBase64a(a)
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} else {
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} else {
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@ -22,8 +22,9 @@ func TestFunctional(t *testing.T) {
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if log {
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if log {
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fmt.Printf("[ %d ] ", testCase)
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fmt.Printf("[ %d ] ", testCase)
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}
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}
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s.SetTrace(log)
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pc := s.reg.getPC()
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pc := s.reg.getPC()
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s.ExecuteInstruction(log)
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s.ExecuteInstruction()
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if pc == s.reg.getPC() {
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if pc == s.reg.getPC() {
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t.Errorf("Failure in test %v.", testCase)
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t.Errorf("Failure in test %v.", testCase)
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}
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}
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@ -17,6 +17,7 @@ type State struct {
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mem Memory
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mem Memory
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cycles uint64
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cycles uint64
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opcodes *[256]opcode
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opcodes *[256]opcode
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trace bool
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}
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}
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const (
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const (
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@ -43,8 +44,13 @@ func (s *State) executeLine(line []uint8) {
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opcode.action(s, line, opcode)
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opcode.action(s, line, opcode)
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}
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}
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// SetTrace activates tracing of the cpu execution
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func (s *State) SetTrace(trace bool) {
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s.trace = trace
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}
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// ExecuteInstruction transforms the state given after a single instruction is executed.
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// ExecuteInstruction transforms the state given after a single instruction is executed.
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func (s *State) ExecuteInstruction(log bool) {
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func (s *State) ExecuteInstruction() {
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pc := s.reg.getPC()
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pc := s.reg.getPC()
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opcodeID := s.mem.Peek(pc)
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opcodeID := s.mem.Peek(pc)
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opcode := s.opcodes[opcodeID]
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opcode := s.opcodes[opcodeID]
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@ -60,12 +66,13 @@ func (s *State) ExecuteInstruction(log bool) {
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}
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}
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s.reg.setPC(pc)
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s.reg.setPC(pc)
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if log {
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if s.trace {
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//fmt.Printf("%#04x %#02x\n", pc-opcode.bytes, opcodeID)
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fmt.Printf("%#04x %-12s: ", pc-opcode.bytes, lineString(line, opcode))
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fmt.Printf("%#04x %-12s: ", pc-opcode.bytes, lineString(line, opcode))
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}
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}
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opcode.action(s, line, opcode)
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opcode.action(s, line, opcode)
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s.cycles += uint64(opcode.cycles)
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s.cycles += uint64(opcode.cycles)
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if log {
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if s.trace {
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fmt.Printf("%v, [%02x]\n", s.reg, line)
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fmt.Printf("%v, [%02x]\n", s.reg, line)
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}
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}
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}
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}
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@ -181,4 +181,9 @@ var opcodesNMOS6502 = [256]opcode{
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0x70: opcode{"BVS", 2, 2, modeRelative, buildOpBranch(flagV, true)}, // Extra cycles
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0x70: opcode{"BVS", 2, 2, modeRelative, buildOpBranch(flagV, true)}, // Extra cycles
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0xEA: opcode{"NOP", 1, 2, modeImplicit, opNOP},
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0xEA: opcode{"NOP", 1, 2, modeImplicit, opNOP},
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// Undocumented opcodes, see http://bbc.nvg.org/doc/6502OpList.txt
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0x1A: opcode{"NOP", 1, 2, modeImplicit, opNOP}, // INC A in the 65c02
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0xC2: opcode{"NOP", 1, 2, modeImplicit, opNOP}, // Should be HALT?
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0x02: opcode{"NOP", 1, 2, modeImplicit, opNOP}, // Should be HALT?
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}
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}
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26
ioC0Page.go
26
ioC0Page.go
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@ -15,6 +15,8 @@ type ioC0Page struct {
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paddlesStrobeCycle uint64
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paddlesStrobeCycle uint64
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joysticks JoysticksProvider
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joysticks JoysticksProvider
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apple2 *Apple2
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apple2 *Apple2
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trace bool
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panicNotImplemented bool
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}
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}
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type softSwitchR func(io *ioC0Page) uint8
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type softSwitchR func(io *ioC0Page) uint8
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@ -57,6 +59,14 @@ func newIoC0Page(a *Apple2) *ioC0Page {
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return &io
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return &io
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}
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}
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func (p *ioC0Page) setTrace(trace bool) {
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p.trace = trace
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}
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func (p *ioC0Page) setPanicNotImplemented(value bool) {
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p.panicNotImplemented = value
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}
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func (p *ioC0Page) save(w io.Writer) {
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func (p *ioC0Page) save(w io.Writer) {
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binary.Write(w, binary.BigEndian, p.softSwitchesData)
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binary.Write(w, binary.BigEndian, p.softSwitchesData)
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}
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}
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@ -106,23 +116,27 @@ func (p *ioC0Page) peek(address uint16) uint8 {
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pageAddress := uint8(address)
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pageAddress := uint8(address)
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ss := p.softSwitchesR[pageAddress]
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ss := p.softSwitchesR[pageAddress]
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if ss == nil {
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if ss == nil {
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if p.apple2.panicSS {
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if p.panicNotImplemented {
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panic(fmt.Sprintf("Unknown softswitch on read to 0xC0%02x", pageAddress))
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panic(fmt.Sprintf("Unknown softswitch on read to $%04x", address))
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}
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}
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return 0
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return 0
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}
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}
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value := ss(p)
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value := ss(p)
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//fmt.Printf("Peek on $%02x: $%02x\n", address, value)
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if p.trace {
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fmt.Printf("Softswitch peek on $%04x: $%02x\n", address, value)
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}
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return value
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return value
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}
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}
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func (p *ioC0Page) poke(address uint16, value uint8) {
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func (p *ioC0Page) poke(address uint16, value uint8) {
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//fmt.Printf("Poke on $%02x with %02x\n", address, value)
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if p.trace {
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fmt.Printf("Softswtich poke on $%04x with %02x\n", address, value)
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}
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pageAddress := uint8(address)
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pageAddress := uint8(address)
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ss := p.softSwitchesW[pageAddress]
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ss := p.softSwitchesW[pageAddress]
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if ss == nil {
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if ss == nil {
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if p.apple2.panicSS {
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if p.panicNotImplemented {
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panic(fmt.Sprintf("Unknown softswitch on write to 0xC0%02x", pageAddress))
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panic(fmt.Sprintf("Unknown softswitch on write to $%04x", address))
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}
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}
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return
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return
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}
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}
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