mirror of
https://github.com/ivanizag/izapple2.git
synced 2025-01-04 18:30:39 +00:00
Reset LC activation count on writes. To pass a2audit tests
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parent
10d2551b36
commit
696038fa30
@ -50,11 +50,11 @@ func (c *cardLanguage) assign(a *Apple2, slot int) {
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for i := uint8(0x0); i <= 0xf; i++ {
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for i := uint8(0x0); i <= 0xf; i++ {
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iCopy := i
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iCopy := i
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c.addCardSoftSwitchR(iCopy, func(*ioC0Page) uint8 {
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c.addCardSoftSwitchR(iCopy, func(*ioC0Page) uint8 {
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c.ssAction(iCopy)
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c.ssAction(iCopy, false)
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return 0
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return 0
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}, "LANGCARDR")
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}, "LANGCARDR")
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c.addCardSoftSwitchW(iCopy, func(*ioC0Page, uint8) {
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c.addCardSoftSwitchW(iCopy, func(*ioC0Page, uint8) {
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c.ssAction(iCopy)
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c.ssAction(iCopy, true)
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}, "LANGCARDW")
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}, "LANGCARDW")
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}
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}
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@ -62,7 +62,7 @@ func (c *cardLanguage) assign(a *Apple2, slot int) {
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c.applyState()
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c.applyState()
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}
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}
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func (c *cardLanguage) ssAction(ss uint8) {
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func (c *cardLanguage) ssAction(ss uint8, write bool) {
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c.altBank = ((ss >> 3) & 1) == 0
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c.altBank = ((ss >> 3) & 1) == 0
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action := ss & 0x3
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action := ss & 0x3
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switch action {
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switch action {
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@ -73,7 +73,9 @@ func (c *cardLanguage) ssAction(ss uint8) {
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case 1:
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case 1:
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// ROM read, RAM write
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// ROM read, RAM write
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c.readState = false
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c.readState = false
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if !write {
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c.writeState++
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c.writeState++
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}
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case 2:
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case 2:
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// ROM read, no writes
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// ROM read, no writes
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c.readState = false
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c.readState = false
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@ -81,8 +83,16 @@ func (c *cardLanguage) ssAction(ss uint8) {
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case 3:
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case 3:
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//RAM read, RAM write
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//RAM read, RAM write
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c.readState = true
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c.readState = true
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if !write {
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c.writeState++
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c.writeState++
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}
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}
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}
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if write && c.writeState == lcWriteHalfEnabled {
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// UtA2e, 5-23. It is reset by even read access or any write acccess in the $C08x range
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// And https://github.com/zellyn/a2audit/issues/3
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c.writeState = lcWriteDisabled
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}
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if c.writeState > lcWriteEnabled {
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if c.writeState > lcWriteEnabled {
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c.writeState = lcWriteEnabled
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c.writeState = lcWriteEnabled
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