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https://github.com/ivanizag/izapple2.git
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Name all the memory segments
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634a079857
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8ebd745a63
@ -78,7 +78,7 @@ func (a *Apple2) LoadRom(filename string) error {
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}
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romBase := 0x10000 - size
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a.mmu.physicalROM[0] = newMemoryRangeROM(uint16(romBase), data)
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a.mmu.physicalROM[0] = newMemoryRangeROM(uint16(romBase), data, "Main ROM")
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return nil
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}
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@ -47,7 +47,7 @@ func loadBase64aRom(a *Apple2) error {
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// Create banks
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for j := range romBanksBytes {
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a.mmu.physicalROM[j] = newMemoryRange(0xd000, romBanksBytes[j])
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a.mmu.physicalROM[j] = newMemoryRange(0xd000, romBanksBytes[j], fmt.Sprintf("Base64 ROM page %v", j))
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}
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// Start with first bank active
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@ -23,16 +23,16 @@ func (c *cardBase) loadRom(data []uint8) {
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}
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if len(data) == 0x100 {
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// Just 256 bytes in Cs00
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c.romCsxx = newMemoryRangeROM(0, data)
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c.romCsxx = newMemoryRangeROM(0, data, "Slot ROM")
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} else if len(data) == 0x800 {
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// The file has C800 to C8FF
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// The 256 bytes in Cx00 are copied from the first page in C800
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c.romCsxx = newMemoryRangeROM(0, data)
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c.romC8xx = newMemoryRangeROM(0xc800, data)
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c.romCsxx = newMemoryRangeROM(0, data, "Slor ROM")
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c.romC8xx = newMemoryRangeROM(0xc800, data, "Slot C8 ROM")
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} else if len(data) == 0x1000 {
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// The file covers the full Cxxx range. Only showing the page
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// corresponding to the slot used.
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c.romCxxx = newMemoryRangeROM(0xc000, data)
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c.romCxxx = newMemoryRangeROM(0xc000, data, "Slot ROM")
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} else {
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panic("Invalid ROM size")
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}
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@ -71,10 +71,10 @@ func (c *cardInOut) assign(a *Apple2, slot int) {
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}
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}
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c.romCsxx = newMemoryRangeROM(0xC200, data[0:255])
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c.romCsxx = newMemoryRangeROM(0xC200, data[0:255], "InOUt card")
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if slot != 2 {
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// To make ifwork on other slots, patch C2, A0 and A1
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// To make it work on other slots, patch C2, A0 and A1
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panic("Assert failed. Only slot 2 supported for the InOut card")
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}
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c.cardBase.assign(a, slot)
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@ -1,5 +1,7 @@
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package apple2
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import "fmt"
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// See https://fabiensanglard.net/fd_proxy/prince_of_persia/Inside%20the%20Apple%20IIe.pdf
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// See https://i.stack.imgur.com/yn21s.gif
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@ -72,7 +74,7 @@ type memoryHandler interface {
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func newMemoryManager(a *Apple2) *memoryManager {
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var mmu memoryManager
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mmu.apple2 = a
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mmu.physicalMainRAM = newMemoryRange(0, make([]uint8, 0xc000))
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mmu.physicalMainRAM = newMemoryRange(0, make([]uint8, 0xc000), "Main RAM")
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mmu.slotC3ROMActive = true // For II+, this is the default behaviour
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@ -138,23 +140,6 @@ func (mmu *memoryManager) getVideoRAM(ext bool) *memoryRange {
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return mmu.physicalMainRAM
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}
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func (mmu *memoryManager) accessReadCached(address uint16) memoryHandler {
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page := address & 0xff00
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if address&0xff00 == mmu.lastAddressPage {
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//fmt.Printf(" hit %v\n", mmu.apple2.cpu.GetCycles())
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return mmu.lastAddressHandler
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}
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//fmt.Printf("Not hit %v\n", mmu.apple2.cpu.GetCycles())
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mh := mmu.accessRead(address)
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if address&0xf000 != 0xc000 {
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// Do not cache 0xC area as it may reconfigure the MMU
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mmu.lastAddressPage = page
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mmu.lastAddressHandler = mh
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}
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return mh
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}
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func (mmu *memoryManager) accessRead(address uint16) memoryHandler {
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if address <= addressLimitZero {
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return mmu.getPhysicalMainRAM(mmu.altZeroPage)
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@ -266,8 +251,8 @@ func (mmu *memoryManager) initLanguageRAM(groups uint8) {
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mmu.physicalLangRAM = make([]*memoryRange, groups)
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mmu.physicalLangAltRAM = make([]*memoryRange, groups)
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for i := uint8(0); i < groups; i++ {
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mmu.physicalLangRAM[i] = newMemoryRange(0xd000, make([]uint8, 0x3000))
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mmu.physicalLangAltRAM[i] = newMemoryRange(0xd000, make([]uint8, 0x1000))
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mmu.physicalLangRAM[i] = newMemoryRange(0xd000, make([]uint8, 0x3000), fmt.Sprintf("LC RAM block %v", i))
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mmu.physicalLangAltRAM[i] = newMemoryRange(0xd000, make([]uint8, 0x1000), fmt.Sprintf("LC RAM Alt block %v", i))
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}
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}
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@ -276,8 +261,8 @@ func (mmu *memoryManager) initExtendedRAM(groups int) {
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mmu.physicalExtRAM = make([]*memoryRange, groups)
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mmu.physicalExtAltRAM = make([]*memoryRange, groups)
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for i := 0; i < groups; i++ {
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mmu.physicalExtRAM[i] = newMemoryRange(0, make([]uint8, 0x10000))
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mmu.physicalExtAltRAM[i] = newMemoryRange(0xd000, make([]uint8, 0x1000))
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mmu.physicalExtRAM[i] = newMemoryRange(0, make([]uint8, 0x10000), fmt.Sprintf("Extra RAM block %v", i))
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mmu.physicalExtAltRAM[i] = newMemoryRange(0xd000, make([]uint8, 0x1000), fmt.Sprintf("Extra RAM Alt block %v", i))
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}
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}
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@ -1,28 +1,40 @@
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package apple2
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import (
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"fmt"
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)
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type memoryRange struct {
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base uint16
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data []uint8
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basePtr uintptr
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name string
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address string
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//basePtr uintptr
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}
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type memoryRangeROM struct {
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memoryRange
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}
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func newMemoryRange(base uint16, data []uint8) *memoryRange {
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func newMemoryRange(base uint16, data []uint8, name string) *memoryRange {
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var m memoryRange
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m.base = base
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m.data = data
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m.setBase(base)
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m.name = name
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m.address = fmt.Sprintf("%p", &m)
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return &m
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}
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func newMemoryRangeROM(base uint16, data []uint8) *memoryRangeROM {
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func newMemoryRangeROM(base uint16, data []uint8, name string) *memoryRangeROM {
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var m memoryRangeROM
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m.base = base
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m.data = data
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m.setBase(base)
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m.name = name
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m.address = fmt.Sprintf("%p", &m)
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return &m
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}
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@ -56,3 +68,17 @@ func (m *memoryRange) subRange(a, b uint16) []uint8 {
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func (m *memoryRangeROM) poke(address uint16, value uint8) {
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// Ignore
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}
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func identifyMemory(m memoryHandler) string {
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ram, ok := m.(*memoryRange)
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if ok {
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return fmt.Sprintf("RAM 0x%04x %s at %s", ram.base, ram.name, ram.address)
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}
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rom, ok := m.(*memoryRangeROM)
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if ok {
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return fmt.Sprintf("ROM 0x%04x %s at %s", rom.base, ram.name, rom.address)
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}
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return ("Unknown memory")
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}
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