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https://github.com/ivanizag/izapple2.git
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Support for ASL and LSR
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parent
7b1cb65eef
commit
9e73ad1850
45
execute.go
45
execute.go
@ -123,7 +123,7 @@ func buildOpIncDec(addressMode int, inc bool) opFunc {
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}
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}
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func buildRotate(addressMode int, isLeft bool) opFunc {
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func buildShift(addressMode int, isLeft bool, isRotate bool) opFunc {
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return func(s *state, line []uint8, opcode opcode) {
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value, setValue := resolveWithAddressMode(s, line, addressMode)
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@ -132,11 +132,15 @@ func buildRotate(addressMode int, isLeft bool) opFunc {
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if isLeft {
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carry = (value & 0x80) != 0
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value <<= 1
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value += oldCarry
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if isRotate {
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value += oldCarry
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}
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} else {
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carry = (value & 0x01) != 0
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value >>= 1
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value += oldCarry << 7
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if isRotate {
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value += oldCarry << 7
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}
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}
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s.registers.updateFlag(flagC, carry)
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s.registers.updateFlagZN(value)
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@ -185,10 +189,7 @@ SBC
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AND
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ORA
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ASL
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EOR
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LSR
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BIT
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CMP
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@ -210,17 +211,29 @@ PLP
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*/
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var opcodes = [256]opcode{
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0x2A: opcode{"ROL", 1, 2, buildRotate(modeAccumulator, true)},
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0x26: opcode{"ROL", 2, 5, buildRotate(modeZeroPage, true)},
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0x36: opcode{"ROL", 2, 6, buildRotate(modeZeroPageX, true)},
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0x2E: opcode{"ROL", 3, 6, buildRotate(modeAbsolute, true)},
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0x3E: opcode{"ROL", 3, 7, buildRotate(modeAbsoluteX, true)},
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0x2A: opcode{"ROL", 1, 2, buildShift(modeAccumulator, true, true)},
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0x26: opcode{"ROL", 2, 5, buildShift(modeZeroPage, true, true)},
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0x36: opcode{"ROL", 2, 6, buildShift(modeZeroPageX, true, true)},
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0x2E: opcode{"ROL", 3, 6, buildShift(modeAbsolute, true, true)},
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0x3E: opcode{"ROL", 3, 7, buildShift(modeAbsoluteX, true, true)},
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0x6A: opcode{"ROR", 1, 2, buildRotate(modeAccumulator, false)},
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0x66: opcode{"ROR", 2, 5, buildRotate(modeZeroPage, false)},
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0x76: opcode{"ROR", 2, 6, buildRotate(modeZeroPageX, false)},
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0x6E: opcode{"ROR", 3, 6, buildRotate(modeAbsolute, false)},
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0x7E: opcode{"ROR", 3, 7, buildRotate(modeAbsoluteX, false)},
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0x6A: opcode{"ROR", 1, 2, buildShift(modeAccumulator, false, true)},
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0x66: opcode{"ROR", 2, 5, buildShift(modeZeroPage, false, true)},
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0x76: opcode{"ROR", 2, 6, buildShift(modeZeroPageX, false, true)},
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0x6E: opcode{"ROR", 3, 6, buildShift(modeAbsolute, false, true)},
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0x7E: opcode{"ROR", 3, 7, buildShift(modeAbsoluteX, false, true)},
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0x0A: opcode{"ASL", 1, 2, buildShift(modeAccumulator, true, false)},
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0x06: opcode{"ASL", 2, 5, buildShift(modeZeroPage, true, false)},
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0x16: opcode{"ASL", 2, 6, buildShift(modeZeroPageX, true, false)},
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0x0E: opcode{"ASL", 3, 6, buildShift(modeAbsolute, true, false)},
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0x1E: opcode{"ASL", 3, 7, buildShift(modeAbsoluteX, true, false)},
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0x4A: opcode{"LSR", 1, 2, buildShift(modeAccumulator, false, false)},
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0x46: opcode{"LSR", 2, 5, buildShift(modeZeroPage, false, false)},
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0x56: opcode{"LSR", 2, 6, buildShift(modeZeroPageX, false, false)},
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0x4E: opcode{"LSR", 3, 6, buildShift(modeAbsolute, false, false)},
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0x5E: opcode{"LSR", 3, 7, buildShift(modeAbsoluteX, false, false)},
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0x38: opcode{"SEC", 1, 2, buildOpUpdateFlag(flagC, true)},
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0xF8: opcode{"SED", 1, 2, buildOpUpdateFlag(flagD, true)},
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@ -179,7 +179,7 @@ func TestIncDec(t *testing.T) {
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}
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}
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func TestRotate(t *testing.T) {
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func TestShiftRotate(t *testing.T) {
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var s state
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s.registers.setA(0xF0)
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@ -200,6 +200,26 @@ func TestRotate(t *testing.T) {
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if !s.registers.getFlag(flagC) {
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t.Errorf("Error in ROR carry")
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}
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s.registers.setFlag(flagC)
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s.registers.setA(0x81)
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executeLine(&s, []uint8{0x0A})
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if s.registers.getA() != 0x02 {
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t.Errorf("Error in ASL. %v", s.registers)
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}
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if !s.registers.getFlag(flagC) {
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t.Errorf("Error in ASL carry")
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}
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s.registers.setFlag(flagC)
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s.registers.setA(0x02)
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executeLine(&s, []uint8{0x4A})
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if s.registers.getA() != 0x01 {
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t.Errorf("Error in LSR. %v", s.registers)
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}
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if s.registers.getFlag(flagC) {
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t.Errorf("Error in LSR carry")
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}
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}
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func TestClearSetFlag(t *testing.T) {
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