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https://github.com/ivanizag/izapple2.git
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Trace softswitch registrations
This commit is contained in:
parent
3a3c350748
commit
ccd100677e
@ -214,6 +214,8 @@ Only valid on SDL mode
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dump to the console the calls to ProDOS machine language interface calls to $BF00
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dump to the console the calls to ProDOS machine language interface calls to $BF00
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-traceSS
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-traceSS
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dump to the console the sofswitches calls
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dump to the console the sofswitches calls
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-traceSSReg
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dump to the console the sofswitch registrations
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-vidHDSlot int
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-vidHDSlot int
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slot for the VidHD card, only for //e models. -1 for none (default 2)
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slot for the VidHD card, only for //e models. -1 for none (default 2)
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-woz string
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-woz string
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@ -6,42 +6,12 @@ import (
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"github.com/ivanizag/apple2/core6502"
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"github.com/ivanizag/apple2/core6502"
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)
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)
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func newApple2plus() *Apple2 {
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func newApple2() *Apple2 {
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var a Apple2
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var a Apple2
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a.Name = "Apple ][+"
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a.Name = "Pending"
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a.mmu = newMemoryManager(&a)
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a.mmu = newMemoryManager(&a)
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a.cpu = core6502.NewNMOS6502(a.mmu)
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a.io = newIoC0Page(&a)
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a.io = newIoC0Page(&a)
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addApple2SoftSwitches(a.io)
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return &a
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}
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func newApple2e() *Apple2 {
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var a Apple2
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a.Name = "Apple IIe"
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a.isApple2e = true
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a.mmu = newMemoryManager(&a)
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a.cpu = core6502.NewNMOS6502(a.mmu)
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a.io = newIoC0Page(&a)
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a.mmu.initExtendedRAM(1)
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addApple2SoftSwitches(a.io)
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addApple2ESoftSwitches(a.io)
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return &a
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}
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func newApple2eEnhanced() *Apple2 {
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var a Apple2
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a.Name = "Apple //e"
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a.isApple2e = true
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a.mmu = newMemoryManager(&a)
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a.cpu = core6502.NewCMOS65c02(a.mmu)
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a.io = newIoC0Page(&a)
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a.mmu.initExtendedRAM(1)
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addApple2SoftSwitches(a.io)
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addApple2ESoftSwitches(a.io)
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return &a
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return &a
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}
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}
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@ -61,6 +31,30 @@ func (a *Apple2) setup(isColor bool, clockMhz float64, fastMode bool, traceMLI b
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}
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}
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}
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}
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func setApple2plus(a *Apple2) {
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a.Name = "Apple ][+"
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a.cpu = core6502.NewNMOS6502(a.mmu)
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addApple2SoftSwitches(a.io)
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}
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func setApple2e(a *Apple2) {
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a.Name = "Apple IIe"
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a.isApple2e = true
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a.cpu = core6502.NewNMOS6502(a.mmu)
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a.mmu.initExtendedRAM(1)
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addApple2SoftSwitches(a.io)
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addApple2ESoftSwitches(a.io)
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}
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func setApple2eEnhanced(a *Apple2) {
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a.Name = "Apple //e"
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a.isApple2e = true
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a.cpu = core6502.NewCMOS65c02(a.mmu)
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a.mmu.initExtendedRAM(1)
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addApple2SoftSwitches(a.io)
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addApple2ESoftSwitches(a.io)
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}
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func (a *Apple2) insertCard(c card, slot int) {
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func (a *Apple2) insertCard(c card, slot int) {
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c.assign(a, slot)
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c.assign(a, slot)
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a.cards[slot] = c
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a.cards[slot] = c
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@ -109,6 +109,10 @@ func MainApple() *Apple2 {
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"traceSS",
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"traceSS",
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false,
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false,
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"dump to the console the sofswitches calls")
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"dump to the console the sofswitches calls")
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traceSSReg := flag.Bool(
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"traceSSReg",
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false,
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"dump to the console the sofswitch registrations")
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traceHD := flag.Bool(
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traceHD := flag.Bool(
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"traceHD",
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"traceHD",
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false,
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false,
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@ -142,12 +146,18 @@ func MainApple() *Apple2 {
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}
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}
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var a *Apple2
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a := newApple2()
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a.setup(!*mono, *cpuClock, *fastDisk, *traceMLI)
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a.io.setTrace(*traceSS)
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a.io.setTraceRegistrations(*traceSSReg)
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a.io.setPanicNotImplemented(*panicSS)
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a.setProfiling(*profile)
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var charGenMap charColumnMap
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var charGenMap charColumnMap
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initialCharGenPage := 0
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initialCharGenPage := 0
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switch *model {
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switch *model {
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case "2plus":
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case "2plus":
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a = newApple2plus()
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setApple2plus(a)
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if *romFile == defaultInternal {
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if *romFile == defaultInternal {
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*romFile = "<internal>/Apple2_Plus.rom"
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*romFile = "<internal>/Apple2_Plus.rom"
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}
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}
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@ -158,7 +168,7 @@ func MainApple() *Apple2 {
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*vidHDCardSlot = -1
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*vidHDCardSlot = -1
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case "2e":
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case "2e":
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a = newApple2e()
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setApple2e(a)
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if *romFile == defaultInternal {
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if *romFile == defaultInternal {
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*romFile = "<internal>/Apple2e.rom"
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*romFile = "<internal>/Apple2e.rom"
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}
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}
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@ -169,7 +179,7 @@ func MainApple() *Apple2 {
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charGenMap = charGenColumnsMap2e
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charGenMap = charGenColumnsMap2e
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case "2enh":
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case "2enh":
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a = newApple2eEnhanced()
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setApple2eEnhanced(a)
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if *romFile == defaultInternal {
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if *romFile == defaultInternal {
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*romFile = "<internal>/Apple2e_Enhanced.rom"
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*romFile = "<internal>/Apple2e_Enhanced.rom"
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}
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}
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@ -180,7 +190,7 @@ func MainApple() *Apple2 {
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charGenMap = charGenColumnsMap2e
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charGenMap = charGenColumnsMap2e
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case "base64a":
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case "base64a":
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a = newBase64a()
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setBase64a(a)
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if *romFile == defaultInternal {
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if *romFile == defaultInternal {
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err := loadBase64aRom(a)
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err := loadBase64aRom(a)
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if err != nil {
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if err != nil {
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@ -199,11 +209,7 @@ func MainApple() *Apple2 {
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panic("Model not supported")
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panic("Model not supported")
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}
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}
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a.setup(!*mono, *cpuClock, *fastDisk, *traceMLI)
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a.cpu.SetTrace(*traceCPU)
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a.cpu.SetTrace(*traceCPU)
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a.io.setTrace(*traceSS)
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a.io.setPanicNotImplemented(*panicSS)
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a.setProfiling(*profile)
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// Load ROM if not loaded already
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// Load ROM if not loaded already
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if *romFile != "" {
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if *romFile != "" {
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@ -10,18 +10,11 @@ import (
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Copam BASE64A adaptation.
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Copam BASE64A adaptation.
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*/
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*/
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// newBase64a instantiates an apple2
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func setBase64a(a *Apple2) {
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func newBase64a() *Apple2 {
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var a Apple2
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a.Name = "Base 64A"
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a.Name = "Base 64A"
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a.mmu = newMemoryManager(&a)
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a.cpu = core6502.NewNMOS6502(a.mmu)
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a.cpu = core6502.NewNMOS6502(a.mmu)
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a.io = newIoC0Page(&a)
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addApple2SoftSwitches(a.io)
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addApple2SoftSwitches(a.io)
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addBase64aSoftSwitches(a.io)
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addBase64aSoftSwitches(a.io)
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return &a
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}
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}
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const (
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const (
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@ -57,9 +57,13 @@ func (c *cardBase) assign(a *Apple2, slot int) {
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}
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}
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for i := 0; i < 0x10; i++ {
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for i := 0; i < 0x10; i++ {
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if c._ssr[i] != nil {
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a.io.addSoftSwitchR(uint8(0xC80+slot*0x10+i), c._ssr[i], c._ssrName[i])
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a.io.addSoftSwitchR(uint8(0xC80+slot*0x10+i), c._ssr[i], c._ssrName[i])
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}
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if c._ssw[i] != nil {
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a.io.addSoftSwitchW(uint8(0xC80+slot*0x10+i), c._ssw[i], c._sswName[i])
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a.io.addSoftSwitchW(uint8(0xC80+slot*0x10+i), c._ssw[i], c._sswName[i])
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}
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}
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}
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}
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}
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func (c *cardBase) addCardSoftSwitchR(address uint8, ss softSwitchR, name string) {
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func (c *cardBase) addCardSoftSwitchR(address uint8, ss softSwitchR, name string) {
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17
ioC0Page.go
17
ioC0Page.go
@ -16,6 +16,7 @@ type ioC0Page struct {
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joysticks JoysticksProvider
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joysticks JoysticksProvider
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apple2 *Apple2
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apple2 *Apple2
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trace bool
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trace bool
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traceRegistrations bool
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panicNotImplemented bool
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panicNotImplemented bool
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}
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}
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@ -57,6 +58,10 @@ func (p *ioC0Page) setTrace(trace bool) {
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p.trace = trace
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p.trace = trace
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}
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}
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func (p *ioC0Page) setTraceRegistrations(traceRegistrations bool) {
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p.traceRegistrations = traceRegistrations
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}
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func (p *ioC0Page) setPanicNotImplemented(value bool) {
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func (p *ioC0Page) setPanicNotImplemented(value bool) {
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p.panicNotImplemented = value
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p.panicNotImplemented = value
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}
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}
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@ -69,17 +74,17 @@ func (p *ioC0Page) addSoftSwitchRW(address uint8, ss softSwitchR, name string) {
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}
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}
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func (p *ioC0Page) addSoftSwitchR(address uint8, ss softSwitchR, name string) {
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func (p *ioC0Page) addSoftSwitchR(address uint8, ss softSwitchR, name string) {
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//if p.softSwitchesR[address] != nil {
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if p.traceRegistrations {
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// fmt.Printf("Addresss 0x0c%02x is already assigned for read\n", address)
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fmt.Printf("Softswitch registered in $c0%02x for reads as %s\n", address, name)
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//}
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}
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p.softSwitchesR[address] = ss
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p.softSwitchesR[address] = ss
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p.softSwitchesRName[address] = name
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p.softSwitchesRName[address] = name
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}
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}
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func (p *ioC0Page) addSoftSwitchW(address uint8, ss softSwitchW, name string) {
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func (p *ioC0Page) addSoftSwitchW(address uint8, ss softSwitchW, name string) {
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//if p.softSwitchesW[address] != nil {
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if p.traceRegistrations {
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// fmt.Printf("Addresss 0x0c%02x is already assigned for write\n", address)
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fmt.Printf("Softswitch registered in $c0%02x for writes as %s\n", address, name)
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//}
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}
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p.softSwitchesW[address] = ss
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p.softSwitchesW[address] = ss
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p.softSwitchesWName[address] = name
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p.softSwitchesWName[address] = name
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}
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}
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