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Added INX, INY, DEX, DEY
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parent
d376e46596
commit
de72112f90
45
execute.go
45
execute.go
@ -39,7 +39,21 @@ func opNOP(s *state, line []uint8, opcode opcode) {}
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func buildOPTransfer(regSrc int, regDst int) opFunc {
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func buildOPTransfer(regSrc int, regDst int) opFunc {
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return func(s *state, line []uint8, opcode opcode) {
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return func(s *state, line []uint8, opcode opcode) {
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s.registers.setRegister(regDst, s.registers.getRegister(regSrc))
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value := s.registers.getRegister(regSrc)
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s.registers.setRegister(regDst, value)
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// TODO: Update flags (N, Z)
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}
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}
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func buildOpIncDecRegister(reg int, inc bool) opFunc {
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return func(s *state, line []uint8, opcode opcode) {
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value := s.registers.getRegister(reg) + 1
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if inc {
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value++
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} else {
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value--
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}
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s.registers.setRegister(reg, value)
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// TODO: Update flags (N, Z) for all but TXS
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// TODO: Update flags (N, Z) for all but TXS
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}
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}
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}
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}
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@ -85,24 +99,25 @@ func buildOpLoad(addressMode int, regDst int) opFunc {
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}
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}
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var opcodes = [256]opcode{
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var opcodes = [256]opcode{
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0x00: opcode{"BRK", 1, 7, opNOP},
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0x88: opcode{"DEY", 1, 2, buildOpIncDecRegister(regY, false)},
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0x8A: opcode{"TXA", 1, 2, buildOPTransfer(regX, regA)},
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0x98: opcode{"TYA", 1, 2, buildOPTransfer(regY, regA)},
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0x9A: opcode{"TXS", 1, 2, buildOPTransfer(regX, regSP)},
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0xA0: opcode{"LDY", 2, 2, buildOpLoad(modeImmediate, regY)},
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0xA0: opcode{"LDY", 2, 2, buildOpLoad(modeImmediate, regY)},
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0xA1: opcode{"LDX", 2, 6, buildOpLoad(modeIndexedIndirectX, regA)},
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0xA1: opcode{"LDX", 2, 6, buildOpLoad(modeIndexedIndirectX, regA)},
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0xA2: opcode{"LDX", 2, 2, buildOpLoad(modeImmediate, regX)},
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0xA2: opcode{"LDX", 2, 2, buildOpLoad(modeImmediate, regX)},
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0xA4: opcode{"LDY", 2, 3, buildOpLoad(modeZeroPage, regY)},
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0xA4: opcode{"LDY", 2, 3, buildOpLoad(modeZeroPage, regY)},
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0xA5: opcode{"LDA", 2, 3, buildOpLoad(modeZeroPage, regA)},
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0xA5: opcode{"LDA", 2, 3, buildOpLoad(modeZeroPage, regA)},
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0xA6: opcode{"LDX", 2, 3, buildOpLoad(modeZeroPage, regX)},
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0xA6: opcode{"LDX", 2, 3, buildOpLoad(modeZeroPage, regX)},
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0xA9: opcode{"LDA", 2, 2, buildOpLoad(modeImmediate, regA)},
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0xAA: opcode{"TAX", 1, 2, buildOPTransfer(regA, regX)},
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0xA8: opcode{"TAY", 1, 2, buildOPTransfer(regA, regY)},
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0xA8: opcode{"TAY", 1, 2, buildOPTransfer(regA, regY)},
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0xBA: opcode{"TSX", 1, 2, buildOPTransfer(regSP, regX)},
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0xA9: opcode{"LDA", 2, 2, buildOpLoad(modeImmediate, regA)},
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0x8A: opcode{"TXA", 1, 2, buildOPTransfer(regX, regA)},
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0xAA: opcode{"TAX", 1, 2, buildOPTransfer(regA, regX)},
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0x9A: opcode{"TXS", 1, 2, buildOPTransfer(regX, regSP)},
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0x98: opcode{"TYA", 1, 2, buildOPTransfer(regY, regA)},
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0xAC: opcode{"LDY", 3, 4, buildOpLoad(modeAbsolute, regY)},
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0xAC: opcode{"LDY", 3, 4, buildOpLoad(modeAbsolute, regY)},
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0xAD: opcode{"LDA", 3, 4, buildOpLoad(modeAbsolute, regA)},
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0xAD: opcode{"LDA", 3, 4, buildOpLoad(modeAbsolute, regA)},
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@ -115,9 +130,19 @@ var opcodes = [256]opcode{
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0xB6: opcode{"LDX", 2, 4, buildOpLoad(modeZeroPageY, regX)},
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0xB6: opcode{"LDX", 2, 4, buildOpLoad(modeZeroPageY, regX)},
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0xB9: opcode{"LDA", 3, 4, buildOpLoad(modeAbsoluteY, regA)}, // Extra cycles
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0xB9: opcode{"LDA", 3, 4, buildOpLoad(modeAbsoluteY, regA)}, // Extra cycles
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0xBA: opcode{"TSX", 1, 2, buildOPTransfer(regSP, regX)},
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0xBC: opcode{"LDY", 3, 4, buildOpLoad(modeAbsoluteX, regY)}, // Extra cycles
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0xBC: opcode{"LDY", 3, 4, buildOpLoad(modeAbsoluteX, regY)}, // Extra cycles
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0xBD: opcode{"LDA", 3, 4, buildOpLoad(modeAbsoluteX, regA)}, // Extra cycles
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0xBD: opcode{"LDA", 3, 4, buildOpLoad(modeAbsoluteX, regA)}, // Extra cycles
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0xBE: opcode{"LDX", 3, 4, buildOpLoad(modeAbsoluteY, regX)}, // Extra cycles
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0xBE: opcode{"LDX", 3, 4, buildOpLoad(modeAbsoluteY, regX)}, // Extra cycles
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0xC8: opcode{"INY", 1, 2, buildOpIncDecRegister(regY, true)},
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0xCA: opcode{"DEX", 1, 2, buildOpIncDecRegister(regX, false)},
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0xE8: opcode{"INX", 1, 2, buildOpIncDecRegister(regX, true)},
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0xEA: opcode{"NOP", 1, 2, opNOP},
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}
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}
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func executeLine(s *state, line []uint8) {
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func executeLine(s *state, line []uint8) {
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