mirror of
https://github.com/ivanizag/izapple2.git
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Emulation of the 65c02 processor variant.
This commit is contained in:
Ivan Izaguirre
parent
f92bc2b08e
commit
df41114043
@ -1,33 +0,0 @@
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package core6502
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import (
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"fmt"
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"testing"
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)
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func TestFunctional(t *testing.T) {
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m := new(FlatMemory)
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s := NewNMOS6502(m)
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// Test suite from https://github.com/Klaus2m5/6502_65C02_functional_tests
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m.loadBinary("testdata/6502_functional_test.bin")
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s.reg.setPC(0x0400)
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for true {
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testCase := s.mem.Peek(0x0200)
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if testCase >= 240 {
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break
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}
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log := testCase > 43
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if log {
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fmt.Printf("[ %d ] ", testCase)
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}
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s.SetTrace(log)
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pc := s.reg.getPC()
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s.ExecuteInstruction()
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if pc == s.reg.getPC() {
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t.Errorf("Failure in test %v.", testCase)
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}
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}
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}
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@ -1,5 +1,7 @@
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package core6502
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import "fmt"
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const (
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modeImplicit = iota + 1
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modeImplicitX
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@ -16,6 +18,10 @@ const (
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modeIndirect
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modeIndexedIndirectX
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modeIndirectIndexedY
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// Added on the 65c02
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modeIndirectZeroPage
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modeAbsoluteIndexedIndirectX
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modeZeroPageAndRelative
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)
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func getWordInLine(line []uint8) uint16 {
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@ -84,6 +90,22 @@ func resolve(s *State, line []uint8, opcode opcode) (getValue func() uint8, setV
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case modeIndirectIndexedY:
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address = getZeroPageWord(s.mem, line[1]) +
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uint16(s.reg.getY())
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// 65c02 additions
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case modeIndirectZeroPage:
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address = getZeroPageWord(s.mem, line[1])
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case modeAbsoluteIndexedIndirectX:
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addressAddress := getWordInLine(line) + uint16(s.reg.getX())
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address = getWord(s.mem, addressAddress)
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case modeRelative:
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// This assumes that PC is already pointing to the next instruction
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address = s.reg.getPC() + uint16(int8(line[1])) // Note: line[1] is signed
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case modeZeroPageAndRelative:
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// Two addressing modes combined. We refer to the second one, relative,
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// placed one byte after the zeropage reference
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address = s.reg.getPC() + uint16(int8(line[2])) // Note: line[2] is signed
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default:
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panic("Assert failed. Missing addressing mode")
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}
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if hasAddress {
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@ -101,3 +123,47 @@ func resolve(s *State, line []uint8, opcode opcode) (getValue func() uint8, setV
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}
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return
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}
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func lineString(line []uint8, opcode opcode) string {
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t := opcode.name
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switch opcode.addressMode {
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case modeImplicit:
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case modeImplicitX:
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case modeImplicitY:
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//Nothing
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case modeAccumulator:
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t += fmt.Sprintf(" A")
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case modeImmediate:
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t += fmt.Sprintf(" #%02x", line[1])
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case modeZeroPage:
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t += fmt.Sprintf(" $%02x", line[1])
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case modeZeroPageX:
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t += fmt.Sprintf(" $%02x,X", line[1])
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case modeZeroPageY:
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t += fmt.Sprintf(" $%02x,Y", line[1])
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case modeRelative:
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t += fmt.Sprintf(" *%+x", int8(line[1]))
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case modeAbsolute:
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t += fmt.Sprintf(" $%04x", getWordInLine(line))
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case modeAbsoluteX:
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t += fmt.Sprintf(" $%04x,X", getWordInLine(line))
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case modeAbsoluteY:
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t += fmt.Sprintf(" $%04x,Y", getWordInLine(line))
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case modeIndirect:
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t += fmt.Sprintf(" ($%04x)", getWordInLine(line))
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case modeIndexedIndirectX:
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t += fmt.Sprintf(" ($%02x,X)", line[1])
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case modeIndirectIndexedY:
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t += fmt.Sprintf(" ($%02x),Y", line[1])
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// 65c02 additions:
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case modeIndirectZeroPage:
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t += fmt.Sprintf(" ($%02x)", line[1])
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case modeAbsoluteIndexedIndirectX:
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t += fmt.Sprintf(" ($%04x,X)", getWordInLine(line))
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case modeZeroPageAndRelative:
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t += fmt.Sprintf(" $%02x *%+x", line[1], int8(line[2]))
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default:
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t += "UNKNOWN MODE"
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}
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return t
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}
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165
core6502/cmos65c02.go
Normal file
165
core6502/cmos65c02.go
Normal file
@ -0,0 +1,165 @@
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package core6502
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/*
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For the diffrences with NMOS6502 see:
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http://6502.org/tutorials/65c02opcodes.html
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http://wilsonminesco.com/NMOS-CMOSdif/
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http://www.obelisk.me.uk/65C02/reference.html
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http://www.obelisk.me.uk/65C02/addressing.html
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http://anyplatform.net/media/guides/cpus/65xx%20Processor%20Data.txt
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*/
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// NewCMOS65c02 returns an initialized 65c02
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func NewCMOS65c02(m Memory) *State {
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var s State
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s.mem = m
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var opcodes [256]opcode
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for i := 0; i < 256; i++ {
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opcodes[i] = opcodesNMOS6502[i]
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if opcodes65c02Delta[i].cycles != 0 {
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opcodes[i] = opcodes65c02Delta[i]
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}
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}
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add65c02NOPs(&opcodes)
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s.opcodes = &opcodes
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return &s
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}
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func add65c02NOPs(opcodes *[256]opcode) {
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nop11 := opcode{"NOP", 1, 1, modeImplicit, opNOP}
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nop22 := opcode{"NOP", 2, 2, modeImmediate, opNOP}
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nop23 := opcode{"NOP", 2, 3, modeImmediate, opNOP}
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nop24 := opcode{"NOP", 2, 4, modeImmediate, opNOP}
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nop34 := opcode{"NOP", 3, 4, modeAbsolute, opNOP}
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nop38 := opcode{"NOP", 3, 8, modeAbsolute, opNOP}
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opcodes[0x02] = nop22
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opcodes[0x22] = nop22
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opcodes[0x42] = nop22
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opcodes[0x62] = nop22
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opcodes[0x82] = nop22
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opcodes[0xc2] = nop22
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opcodes[0xe2] = nop22
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opcodes[0x44] = nop23
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opcodes[0x54] = nop24
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opcodes[0xD4] = nop24
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opcodes[0xF4] = nop24
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opcodes[0x5c] = nop38
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opcodes[0xdc] = nop34
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opcodes[0xfc] = nop34
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for i := 0; i < 0x100; i = i + 0x10 {
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opcodes[i+0x03] = nop11
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// RMB and SMB; opcodes[i+0x07] = nop11
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opcodes[i+0x0b] = nop11
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// BBR and BBS: opcodes[i+0x0f] = nop11
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}
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}
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var opcodes65c02Delta = [256]opcode{
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// Functional difference
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0x00: opcode{"BRK", 1, 7, modeImplicit, opBRKAlt},
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0x24: opcode{"BIT", 2, 3, modeZeroPage, opBIT},
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0x2C: opcode{"BIT", 3, 3, modeAbsolute, opBIT},
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// Fixed BCD arithmetic flags
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0x69: opcode{"ADC", 2, 2, modeImmediate, opADCAlt},
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0x65: opcode{"ADC", 2, 3, modeZeroPage, opADCAlt},
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0x75: opcode{"ADC", 2, 4, modeZeroPageX, opADCAlt},
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0x6D: opcode{"ADC", 3, 4, modeAbsolute, opADCAlt},
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0x7D: opcode{"ADC", 3, 4, modeAbsoluteX, opADCAlt},
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0x79: opcode{"ADC", 3, 4, modeAbsoluteY, opADCAlt},
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0x61: opcode{"ADC", 2, 6, modeIndexedIndirectX, opADCAlt},
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0x71: opcode{"ADC", 2, 5, modeIndirectIndexedY, opADCAlt},
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0xE9: opcode{"SBC", 2, 2, modeImmediate, opSBCAlt},
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0xE5: opcode{"SBC", 2, 3, modeZeroPage, opSBCAlt},
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0xF5: opcode{"SBC", 2, 4, modeZeroPageX, opSBCAlt},
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0xED: opcode{"SBC", 3, 4, modeAbsolute, opSBCAlt},
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0xFD: opcode{"SBC", 3, 4, modeAbsoluteX, opSBCAlt},
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0xF9: opcode{"SBC", 3, 4, modeAbsoluteY, opSBCAlt},
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0xE1: opcode{"SBC", 2, 6, modeIndexedIndirectX, opSBCAlt},
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0xF1: opcode{"SBC", 2, 5, modeIndirectIndexedY, opSBCAlt},
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// Different cycle count
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0x1e: opcode{"ASL", 3, 6, modeAbsoluteX, buildOpShift(true, false)},
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0x3e: opcode{"ROL", 3, 6, modeAbsoluteX, buildOpShift(true, true)},
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0x5e: opcode{"LSR", 3, 6, modeAbsoluteX, buildOpShift(false, false)},
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0x7e: opcode{"ROR", 3, 6, modeAbsoluteX, buildOpShift(false, true)},
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// New indirect zero page addresssing mode
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0x12: opcode{"ORA", 2, 5, modeIndirectZeroPage, buildOpLogic(operationOr)},
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0x32: opcode{"AND", 2, 5, modeIndirectZeroPage, buildOpLogic(operationAnd)},
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0x52: opcode{"EOR", 2, 5, modeIndirectZeroPage, buildOpLogic(operationXor)},
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0x72: opcode{"ADC", 2, 5, modeIndirectZeroPage, opADCAlt},
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0x92: opcode{"STA", 2, 5, modeIndirectZeroPage, buildOpStore(regA)},
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0xb2: opcode{"LDA", 2, 5, modeIndirectZeroPage, buildOpLoad(regA)},
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0xd2: opcode{"CMP", 2, 5, modeIndirectZeroPage, buildOpCompare(regA)},
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0xf2: opcode{"SBC", 2, 5, modeIndirectZeroPage, opSBCAlt},
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// New addressing options
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0x89: opcode{"BIT", 2, 2, modeImmediate, opBIT},
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0x34: opcode{"BIT", 2, 4, modeZeroPageX, opBIT},
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0x3c: opcode{"BIT", 3, 4, modeAbsoluteX, opBIT},
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0x1a: opcode{"INC", 1, 2, modeAccumulator, buildOpIncDec(true)},
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0x3a: opcode{"DEC", 1, 2, modeAccumulator, buildOpIncDec(false)},
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0x7c: opcode{"JMP", 3, 6, modeAbsoluteIndexedIndirectX, opJMP},
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// Additional instructions: BRA, PHX, PHY, PLX, PLY, STZ, TRB, TSB
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0xda: opcode{"PHX", 1, 3, modeImplicit, buildOpPush(regX)},
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0x5a: opcode{"PHY", 1, 3, modeImplicit, buildOpPush(regY)},
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0xfa: opcode{"PLX", 1, 4, modeImplicit, buildOpPull(regX)},
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0x7a: opcode{"PLY", 1, 4, modeImplicit, buildOpPull(regY)},
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0x80: opcode{"BRA", 2, 4, modeRelative, opJMP},
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0x64: opcode{"STZ", 2, 3, modeZeroPage, opSTZ},
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0x74: opcode{"STZ", 2, 4, modeZeroPageX, opSTZ},
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0x9c: opcode{"STZ", 3, 4, modeAbsolute, opSTZ},
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0x9e: opcode{"STZ", 3, 5, modeAbsoluteX, opSTZ},
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0x14: opcode{"TRB", 2, 5, modeZeroPage, opTRB},
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0x1c: opcode{"TRB", 3, 6, modeAbsolute, opTRB},
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0x04: opcode{"TSB", 2, 5, modeZeroPage, opTSB},
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0x0c: opcode{"TSB", 3, 6, modeAbsolute, opTSB},
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// Additional in Rockwell 65c02 and WDC 65c02?
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// They have a double addressing mode: zeropage and relative.
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0x0f: opcode{"BBR0", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(0, false)},
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0x1f: opcode{"BBR1", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(1, false)},
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0x2f: opcode{"BBR2", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(2, false)},
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0x3f: opcode{"BBR3", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(3, false)},
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0x4f: opcode{"BBR4", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(4, false)},
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0x5f: opcode{"BBR5", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(5, false)},
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0x6f: opcode{"BBR6", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(6, false)},
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0x7f: opcode{"BBR7", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(7, false)},
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0x8f: opcode{"BBS0", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(0, true)},
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0x9f: opcode{"BBS1", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(1, true)},
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0xaf: opcode{"BBS2", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(2, true)},
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0xbf: opcode{"BBS3", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(3, true)},
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0xcf: opcode{"BBS4", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(4, true)},
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0xdf: opcode{"BBS5", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(5, true)},
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0xef: opcode{"BBS6", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(6, true)},
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0xff: opcode{"BBS7", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(7, true)},
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0x07: opcode{"RMB0", 2, 5, modeZeroPage, buildOpSetBit(0, false)},
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0x17: opcode{"RMB1", 2, 5, modeZeroPage, buildOpSetBit(1, false)},
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0x27: opcode{"RMB2", 2, 5, modeZeroPage, buildOpSetBit(2, false)},
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0x37: opcode{"RMB3", 2, 5, modeZeroPage, buildOpSetBit(3, false)},
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0x47: opcode{"RMB4", 2, 5, modeZeroPage, buildOpSetBit(4, false)},
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0x57: opcode{"RMB5", 2, 5, modeZeroPage, buildOpSetBit(5, false)},
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0x67: opcode{"RMB6", 2, 5, modeZeroPage, buildOpSetBit(6, false)},
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0x77: opcode{"RMB7", 2, 5, modeZeroPage, buildOpSetBit(7, false)},
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0x87: opcode{"SMB0", 2, 5, modeZeroPage, buildOpSetBit(0, true)},
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0x97: opcode{"SMB1", 2, 5, modeZeroPage, buildOpSetBit(1, true)},
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0xa7: opcode{"SMB2", 2, 5, modeZeroPage, buildOpSetBit(2, true)},
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0xb7: opcode{"SMB3", 2, 5, modeZeroPage, buildOpSetBit(3, true)},
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0xc7: opcode{"SMB4", 2, 5, modeZeroPage, buildOpSetBit(4, true)},
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0xd7: opcode{"SMB5", 2, 5, modeZeroPage, buildOpSetBit(5, true)},
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0xe7: opcode{"SMB6", 2, 5, modeZeroPage, buildOpSetBit(6, true)},
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0xf7: opcode{"SMB7", 2, 5, modeZeroPage, buildOpSetBit(7, true)},
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// Maybe additional Rockwell: STP, WAI
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}
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32
core6502/cmos65c02_test.go
Normal file
32
core6502/cmos65c02_test.go
Normal file
@ -0,0 +1,32 @@
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package core6502
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import (
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"testing"
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)
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func TestCMOs65c02NoUndocumented(t *testing.T) {
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m := new(FlatMemory)
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s := NewCMOS65c02(m)
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for i := 0; i < 256; i++ {
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if s.opcodes[i].cycles == 0 {
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t.Errorf("Opcode missing for $%02x.", i)
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}
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}
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}
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func TestCMOS65c02asNMOS(t *testing.T) {
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m := new(FlatMemory)
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s := NewCMOS65c02(m)
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m.loadBinary("testdata/6502_functional_test.bin")
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executeSuite(t, s, 0x200, 240, false, 255)
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}
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func TestCMOS65c02(t *testing.T) {
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m := new(FlatMemory)
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s := NewCMOS65c02(m)
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m.loadBinary("testdata/65C02_extended_opcodes_test.bin")
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executeSuite(t, s, 0x202, 240, false, 255)
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}
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@ -63,7 +63,7 @@ func (s *State) ExecuteInstruction() {
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if s.trace {
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//fmt.Printf("%#04x %#02x\n", pc-opcode.bytes, opcodeID)
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fmt.Printf("%#04x %-12s: ", pc-opcode.bytes, lineString(line, opcode))
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fmt.Printf("%#04x %-13s: ", pc-opcode.bytes, lineString(line, opcode))
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}
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opcode.action(s, line, opcode)
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s.cycles += uint64(opcode.cycles)
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@ -84,6 +84,16 @@ func (s *State) GetCycles() uint64 {
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return s.cycles
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}
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// SetTrace activates tracing of the cpu execution
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func (s *State) SetTrace(trace bool) {
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s.trace = trace
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}
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// GetTrace gets trhe tracing state of the cpu execution
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func (s *State) GetTrace() bool {
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return s.trace
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}
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// Save saves the CPU state (registers and cycle counter)
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func (s *State) Save(w io.Writer) error {
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err := binary.Write(w, binary.BigEndian, s.cycles)
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@ -109,50 +119,3 @@ func (s *State) Load(r io.Reader) error {
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}
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return nil
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}
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func lineString(line []uint8, opcode opcode) string {
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t := opcode.name
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switch opcode.addressMode {
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case modeImplicit:
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case modeImplicitX:
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case modeImplicitY:
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//Nothing
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case modeAccumulator:
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t += fmt.Sprintf(" A")
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case modeImmediate:
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t += fmt.Sprintf(" #%02x", line[1])
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case modeZeroPage:
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t += fmt.Sprintf(" $%02x", line[1])
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case modeZeroPageX:
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t += fmt.Sprintf(" $%02x,X", line[1])
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case modeZeroPageY:
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t += fmt.Sprintf(" $%02x,Y", line[1])
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case modeRelative:
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t += fmt.Sprintf(" *%+x", int8(line[1]))
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case modeAbsolute:
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t += fmt.Sprintf(" $%04x", getWordInLine(line))
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case modeAbsoluteX:
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t += fmt.Sprintf(" $%04x,X", getWordInLine(line))
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case modeAbsoluteY:
|
||||
t += fmt.Sprintf(" $%04x,Y", getWordInLine(line))
|
||||
case modeIndirect:
|
||||
t += fmt.Sprintf(" ($%04x)", getWordInLine(line))
|
||||
case modeIndexedIndirectX:
|
||||
t += fmt.Sprintf(" ($%02x,X)", line[1])
|
||||
case modeIndirectIndexedY:
|
||||
t += fmt.Sprintf(" ($%02x),Y", line[1])
|
||||
default:
|
||||
t += "UNKNOWN MODE"
|
||||
}
|
||||
return t
|
||||
}
|
||||
|
||||
// SetTrace activates tracing of the cpu execution
|
||||
func (s *State) SetTrace(trace bool) {
|
||||
s.trace = trace
|
||||
}
|
||||
|
||||
// GetTrace gets trhe tracing state of the cpu execution
|
||||
func (s *State) GetTrace() bool {
|
||||
return s.trace
|
||||
}
|
||||
|
||||
@ -483,5 +483,3 @@ func TestStack(t *testing.T) {
|
||||
t.Errorf("Error in PLP, %v", s.reg)
|
||||
}
|
||||
}
|
||||
|
||||
// TODO: Tests for BRK, JMP, JSR, RTI, RTS
|
||||
|
||||
@ -16,10 +16,10 @@ var opcodesNMOS6502 = [256]opcode{
|
||||
0x40: opcode{"RTI", 1, 6, modeImplicit, opRTI},
|
||||
0x60: opcode{"RTS", 1, 6, modeImplicit, opRTS},
|
||||
|
||||
0x48: opcode{"PHA", 1, 3, modeImplicit, opPHA},
|
||||
0x08: opcode{"PHP", 1, 3, modeImplicit, opPHP},
|
||||
0x68: opcode{"PLA", 1, 4, modeImplicit, opPLA},
|
||||
0x28: opcode{"PLP", 1, 4, modeImplicit, opPLP},
|
||||
0x48: opcode{"PHA", 1, 3, modeImplicit, buildOpPush(regA)},
|
||||
0x08: opcode{"PHP", 1, 3, modeImplicit, buildOpPush(regP)},
|
||||
0x68: opcode{"PLA", 1, 4, modeImplicit, buildOpPull(regA)},
|
||||
0x28: opcode{"PLP", 1, 4, modeImplicit, buildOpPull(regP)},
|
||||
|
||||
0x09: opcode{"ORA", 2, 2, modeImmediate, buildOpLogic(operationOr)},
|
||||
0x05: opcode{"ORA", 2, 3, modeZeroPage, buildOpLogic(operationOr)},
|
||||
|
||||
38
core6502/nmos6502_test.go
Normal file
38
core6502/nmos6502_test.go
Normal file
@ -0,0 +1,38 @@
|
||||
package core6502
|
||||
|
||||
import (
|
||||
"fmt"
|
||||
"testing"
|
||||
)
|
||||
|
||||
func TestNMOS6502(t *testing.T) {
|
||||
m := new(FlatMemory)
|
||||
s := NewNMOS6502(m)
|
||||
|
||||
m.loadBinary("testdata/6502_functional_test.bin")
|
||||
executeSuite(t, s, 0x200, 240, false, 255)
|
||||
}
|
||||
|
||||
// To execute test suites from https://github.com/Klaus2m5/6502_65C02_functional_tests
|
||||
func executeSuite(t *testing.T, s *State, stepAddress uint16, steps uint8, showStep bool, traceCPUStep uint8) {
|
||||
s.reg.setPC(0x0400)
|
||||
currentStep := uint8(255)
|
||||
for true {
|
||||
testCase := s.mem.Peek(stepAddress)
|
||||
if testCase != currentStep {
|
||||
currentStep = testCase
|
||||
if showStep {
|
||||
fmt.Printf("[ Step %d ]\n", testCase)
|
||||
}
|
||||
s.SetTrace(testCase == traceCPUStep)
|
||||
}
|
||||
if testCase >= steps {
|
||||
break
|
||||
}
|
||||
pc := s.reg.getPC()
|
||||
s.ExecuteInstruction()
|
||||
if pc == s.reg.getPC() {
|
||||
t.Fatalf("Failure in test %v.", testCase)
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -70,13 +70,37 @@ func buildOpUpdateFlag(flag uint8, value bool) opFunc {
|
||||
}
|
||||
}
|
||||
|
||||
func buildOpBranch(flag uint8, value bool) opFunc {
|
||||
func buildOpBranch(flag uint8, test bool) opFunc {
|
||||
return func(s *State, line []uint8, opcode opcode) {
|
||||
if s.reg.getFlag(flag) == value {
|
||||
// This assumes that PC is already pointing to the next instruction
|
||||
pc := s.reg.getPC()
|
||||
pc += uint16(int8(line[1]))
|
||||
s.reg.setPC(pc)
|
||||
if s.reg.getFlag(flag) == test {
|
||||
address := resolveAddress(s, line, opcode)
|
||||
s.reg.setPC(address)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
func buildOpBranchOnBit(bit uint8, test bool) opFunc {
|
||||
return func(s *State, line []uint8, opcode opcode) {
|
||||
// Note that those operations have two addressing modes:
|
||||
// one for the zero page value, another for the relative jump.
|
||||
// We will have to resolve the first one here.
|
||||
value := s.mem.Peek(uint16(line[1]))
|
||||
bitValue := ((value >> bit) & 1) == 1
|
||||
|
||||
if bitValue == test {
|
||||
address := resolveAddress(s, line, opcode)
|
||||
s.reg.setPC(address)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
func buildOpSetBit(bit uint8, set bool) opFunc {
|
||||
return func(s *State, line []uint8, opcode opcode) {
|
||||
value, setValue := resolveGetSetValue(s, line, opcode)
|
||||
if set {
|
||||
setValue(value | (1 << bit))
|
||||
} else {
|
||||
setValue(value &^ (1 << bit))
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -84,10 +108,26 @@ func buildOpBranch(flag uint8, value bool) opFunc {
|
||||
func opBIT(s *State, line []uint8, opcode opcode) {
|
||||
value := resolveValue(s, line, opcode)
|
||||
acc := s.reg.getA()
|
||||
// Future note: The immediate addressing mode (65C02 or 65816 only) does not affect V.
|
||||
s.reg.updateFlag(flagZ, value&acc == 0)
|
||||
s.reg.updateFlag(flagN, value&(1<<7) != 0)
|
||||
s.reg.updateFlag(flagV, value&(1<<6) != 0)
|
||||
// The immediate addressing mode (65C02 or 65816 only) does not affect N & V.
|
||||
if opcode.addressMode != modeImmediate {
|
||||
s.reg.updateFlag(flagN, value&(1<<7) != 0)
|
||||
s.reg.updateFlag(flagV, value&(1<<6) != 0)
|
||||
}
|
||||
}
|
||||
|
||||
func opTRB(s *State, line []uint8, opcode opcode) {
|
||||
value, setValue := resolveGetSetValue(s, line, opcode)
|
||||
a := s.reg.getA()
|
||||
s.reg.updateFlag(flagZ, (value&a) == 0)
|
||||
setValue(value &^ a)
|
||||
}
|
||||
|
||||
func opTSB(s *State, line []uint8, opcode opcode) {
|
||||
value, setValue := resolveGetSetValue(s, line, opcode)
|
||||
a := s.reg.getA()
|
||||
s.reg.updateFlag(flagZ, (value&a) == 0)
|
||||
setValue(value | a)
|
||||
}
|
||||
|
||||
func buildOpCompare(reg int) opFunc {
|
||||
@ -140,6 +180,12 @@ func opADC(s *State, line []uint8, opcode opcode) {
|
||||
s.reg.updateFlag(flagV, signedTotal < -128 || signedTotal > 127)
|
||||
}
|
||||
|
||||
func opADCAlt(s *State, line []uint8, opcode opcode) {
|
||||
opADC(s, line, opcode)
|
||||
// The Z and N flags on BCD are fixed in 65c02.
|
||||
s.reg.updateFlagZN(s.reg.getA())
|
||||
}
|
||||
|
||||
func opSBC(s *State, line []uint8, opcode opcode) {
|
||||
value := resolveValue(s, line, opcode)
|
||||
aValue := s.reg.getA()
|
||||
@ -168,6 +214,12 @@ func opSBC(s *State, line []uint8, opcode opcode) {
|
||||
s.reg.updateFlag(flagV, signedTotal < -128 || signedTotal > 127)
|
||||
}
|
||||
|
||||
func opSBCAlt(s *State, line []uint8, opcode opcode) {
|
||||
opSBC(s, line, opcode)
|
||||
// The Z and N flags on BCD are fixed in 65c02.
|
||||
s.reg.updateFlagZN(s.reg.getA())
|
||||
}
|
||||
|
||||
const stackAddress uint16 = 0x0100
|
||||
|
||||
func pushByte(s *State, value uint8) {
|
||||
@ -193,23 +245,24 @@ func pullWord(s *State) uint16 {
|
||||
|
||||
}
|
||||
|
||||
func opPLA(s *State, line []uint8, opcode opcode) {
|
||||
value := pullByte(s)
|
||||
s.reg.setA(value)
|
||||
s.reg.updateFlagZN(value)
|
||||
func buildOpPull(regDst int) opFunc {
|
||||
return func(s *State, line []uint8, opcode opcode) {
|
||||
value := pullByte(s)
|
||||
s.reg.setRegister(regDst, value)
|
||||
if regDst != regP {
|
||||
s.reg.updateFlagZN(value)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
func opPLP(s *State, line []uint8, opcode opcode) {
|
||||
value := pullByte(s)
|
||||
s.reg.setP(value)
|
||||
}
|
||||
|
||||
func opPHA(s *State, line []uint8, opcode opcode) {
|
||||
pushByte(s, s.reg.getA())
|
||||
}
|
||||
|
||||
func opPHP(s *State, line []uint8, opcode opcode) {
|
||||
pushByte(s, s.reg.getP()|(flagB+flag5))
|
||||
func buildOpPush(regSrc int) opFunc {
|
||||
return func(s *State, line []uint8, opcode opcode) {
|
||||
value := s.reg.getRegister(regSrc)
|
||||
if regSrc == regP {
|
||||
value |= flagB + flag5
|
||||
}
|
||||
pushByte(s, value)
|
||||
}
|
||||
}
|
||||
|
||||
func opJMP(s *State, line []uint8, opcode opcode) {
|
||||
@ -240,3 +293,18 @@ func opBRK(s *State, line []uint8, opcode opcode) {
|
||||
s.reg.setFlag(flagI)
|
||||
s.reg.setPC(getWord(s.mem, vectorBreak))
|
||||
}
|
||||
|
||||
func opBRKAlt(s *State, line []uint8, opcode opcode) {
|
||||
opBRK(s, line, opcode)
|
||||
/*
|
||||
The only difference in the BRK instruction on the 65C02 and the 6502
|
||||
is that the 65C02 clears the D (decimal) flag on the 65C02, whereas
|
||||
the D flag is not affected on the 6502.
|
||||
*/
|
||||
s.reg.clearFlag(flagD)
|
||||
}
|
||||
|
||||
func opSTZ(s *State, line []uint8, opcode opcode) {
|
||||
setValue := resolveSetValue(s, line, opcode)
|
||||
setValue(0)
|
||||
}
|
||||
|
||||
BIN
core6502/testdata/65C02_extended_opcodes_test.bin
vendored
Normal file
BIN
core6502/testdata/65C02_extended_opcodes_test.bin
vendored
Normal file
Binary file not shown.
11510
core6502/testdata/65C02_extended_opcodes_test.lst
vendored
Normal file
11510
core6502/testdata/65C02_extended_opcodes_test.lst
vendored
Normal file
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user