mirror of
https://github.com/ivanizag/izapple2.git
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307 lines
9.6 KiB
Go
307 lines
9.6 KiB
Go
package izapple2
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import "fmt"
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// See https://fabiensanglard.net/fd_proxy/prince_of_persia/Inside%20the%20Apple%20IIe.pdf
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// See https://i.stack.imgur.com/yn21s.gif
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type memoryManager struct {
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apple2 *Apple2
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// Main RAM area: 0x0000 to 0xbfff
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physicalMainRAM *memoryRange // 0x0000 to 0xbfff, Up to 48 Kb
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// Slots area: 0xc000 to 0xcfff
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cardsROM [8]memoryHandler //0xcs00 to 0xcSff. 256 bytes for each card
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cardsROMExtra [8]memoryHandler // 0xc800 to 0xcfff. 2048 bytes for each card
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// Upper area ROM: 0xc000 to 0xffff (or 0xd000 to 0xffff on the II+)
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physicalROM [4]memoryHandler // 0xc000 (or 0xd000) to 0xffff, 16 (or 12) Kb. Up to four banks
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// Language card upper area RAM: 0xd000 to 0xffff. One bank for regular LC cards, up to 8 with Saturn
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physicalLangRAM []*memoryRange // 0xd000 to 0xffff, 12KB. Up to 8 banks.
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physicalLangAltRAM []*memoryRange // 0xd000 to 0xdfff, 4KB. Up to 8 banks.
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// Extended RAM: 0x0000 to 0xffff (with 4Kb moved from 0xc000 to 0xd000 alt). One bank for extended Apple 2e card, up to 256 with RamWorks
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physicalExtRAM []*memoryRange // 0x0000 to 0xffff. 60Kb, 0xc000 to 0xcfff not used. Up to 256 banks
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physicalExtAltRAM []*memoryRange // 0xd000 to 0xdfff, 4Kb. Up to 256 banks.
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// Configuration switches, Language cards
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lcSelectedBlock uint8 // Language card block selected. Usually, allways 0. But Saturn has 8
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lcActiveRead bool // Upper RAM active for read
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lcActiveWrite bool // Upper RAM active for read
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lcAltBank bool // Alternate
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// Configuration switches, Apple //e
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altZeroPage bool // Use extra RAM from 0x0000 to 0x01ff. And additional language card block
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altMainRAMActiveRead bool // Use extra RAM from 0x0200 to 0xbfff for read
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altMainRAMActiveWrite bool // Use extra RAM from 0x0200 to 0xbfff for write
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store80Active bool // Special pagination for text and graphics areas
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slotC3ROMActive bool // Apple2e slot 3 ROM shadow
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intCxROMActive bool // Apple2e slots internal ROM shadow
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intC8ROMActive bool // C8Rom associated to the internal slot 3. Softswitch not directly accessible. See UtA2e 5-28
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activeSlot uint8 // Active slot owner of 0xc800 to 0xcfff
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extendedRAMBlock uint8 // Block used for entended memory for RAMWorks cards
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// Configuration switches, Base64A
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romPage uint8 // Active ROM page
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// Resolution cache
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lastAddressPage uint16 // The first byte is the page. The second is zero when the cached is valid.
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lastAddressHandler memoryHandler
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}
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const (
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ioC8Off uint16 = 0xcfff
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addressLimitZero uint16 = 0x01ff
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addressStartText uint16 = 0x0400
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addressLimitText uint16 = 0x07ff
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addressStartHgr uint16 = 0x2000
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addressLimitHgr uint16 = 0x3fff
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addressLimitMainRAM uint16 = 0xbfff
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addressLimitIO uint16 = 0xc0ff
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addressLimitSlots uint16 = 0xc7ff
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addressLimitSlotsExtra uint16 = 0xcfff
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addressLimitDArea uint16 = 0xdfff
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invalidAddressPage uint16 = 0x0001
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)
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type memoryHandler interface {
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peek(uint16) uint8
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poke(uint16, uint8)
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}
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func newMemoryManager(a *Apple2) *memoryManager {
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var mmu memoryManager
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mmu.apple2 = a
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mmu.physicalMainRAM = newMemoryRange(0, make([]uint8, 0xc000), "Main RAM")
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mmu.slotC3ROMActive = true // For II+, this is the default behaviour
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return &mmu
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}
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func (mmu *memoryManager) accessCArea(address uint16) memoryHandler {
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slot := uint8((address >> 8) & 0x0f)
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// Internal IIe slot 3
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if (address <= addressLimitSlots) && !mmu.slotC3ROMActive && (slot == 3) {
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mmu.intC8ROMActive = true
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return mmu.physicalROM[mmu.romPage]
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}
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// Internal IIe CxROM
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if mmu.intCxROMActive {
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return mmu.physicalROM[mmu.romPage]
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}
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// First slot area
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if slot <= 7 {
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mmu.activeSlot = slot
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mmu.intC8ROMActive = false
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return mmu.cardsROM[slot]
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}
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// Extra slot area reset
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if address == ioC8Off {
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// Reset extra slot area owner
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mmu.activeSlot = 0
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mmu.intC8ROMActive = false
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}
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// Extra slot area
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if mmu.intC8ROMActive {
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return mmu.physicalROM[mmu.romPage]
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}
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return mmu.cardsROMExtra[mmu.activeSlot]
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}
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func (mmu *memoryManager) accessUpperRAMArea(address uint16) memoryHandler {
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if mmu.altZeroPage {
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// Use extended RAM
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block := mmu.extendedRAMBlock
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if mmu.lcAltBank && address <= addressLimitDArea {
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return mmu.physicalExtAltRAM[block]
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}
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return mmu.physicalExtRAM[mmu.extendedRAMBlock]
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}
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// Use language card
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block := mmu.lcSelectedBlock
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if mmu.lcAltBank && address <= addressLimitDArea {
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return mmu.physicalLangAltRAM[block]
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}
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return mmu.physicalLangRAM[block]
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}
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func (mmu *memoryManager) getPhysicalMainRAM(ext bool) memoryHandler {
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if ext {
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return mmu.physicalExtRAM[mmu.extendedRAMBlock]
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}
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return mmu.physicalMainRAM
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}
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func (mmu *memoryManager) getVideoRAM(ext bool) *memoryRange {
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if ext {
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// The video memory uses the first extended RAM block, even with RAMWorks
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return mmu.physicalExtRAM[0]
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}
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return mmu.physicalMainRAM
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}
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func (mmu *memoryManager) accessRead(address uint16) memoryHandler {
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if address <= addressLimitZero {
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return mmu.getPhysicalMainRAM(mmu.altZeroPage)
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}
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if mmu.store80Active && address <= addressLimitHgr {
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altPage := mmu.apple2.io.isSoftSwitchActive(ioFlagSecondPage) // TODO: move flag to mmu property like the store80
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if address >= addressStartText && address <= addressLimitText {
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return mmu.getPhysicalMainRAM(altPage)
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}
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hires := mmu.apple2.io.isSoftSwitchActive(ioFlagHiRes)
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if hires && address >= addressStartHgr && address <= addressLimitHgr {
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return mmu.getPhysicalMainRAM(altPage)
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}
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}
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if address <= addressLimitMainRAM {
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return mmu.getPhysicalMainRAM(mmu.altMainRAMActiveRead)
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}
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if address <= addressLimitIO {
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mmu.lastAddressPage = invalidAddressPage
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return mmu.apple2.io
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}
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if address <= addressLimitSlotsExtra {
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return mmu.accessCArea(address)
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}
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if mmu.lcActiveRead {
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return mmu.accessUpperRAMArea(address)
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}
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return mmu.physicalROM[mmu.romPage]
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}
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func (mmu *memoryManager) accessWrite(address uint16) memoryHandler {
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if address <= addressLimitZero {
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return mmu.getPhysicalMainRAM(mmu.altZeroPage)
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}
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if address <= addressLimitHgr && mmu.store80Active {
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altPage := mmu.apple2.io.isSoftSwitchActive(ioFlagSecondPage)
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if address >= addressStartText && address <= addressLimitText {
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return mmu.getPhysicalMainRAM(altPage)
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}
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hires := mmu.apple2.io.isSoftSwitchActive(ioFlagHiRes)
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if hires && address >= addressStartHgr && address <= addressLimitHgr {
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return mmu.getPhysicalMainRAM(altPage)
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}
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}
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if address <= addressLimitMainRAM {
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return mmu.getPhysicalMainRAM(mmu.altMainRAMActiveWrite)
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}
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if address <= addressLimitIO {
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mmu.lastAddressPage = invalidAddressPage
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return mmu.apple2.io
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}
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if address <= addressLimitSlotsExtra {
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return mmu.accessCArea(address)
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}
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if mmu.lcActiveWrite {
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return mmu.accessUpperRAMArea(address)
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}
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return mmu.physicalROM[mmu.romPage]
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}
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// Peek returns the data on the given address
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func (mmu *memoryManager) Peek(address uint16) uint8 {
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mh := mmu.accessRead(address)
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if mh == nil {
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return 0xf4 // Or some random number
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}
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return mh.peek(address)
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}
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// Peek returns the data on the given address optimized for more local requests
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func (mmu *memoryManager) PeekCode(address uint16) uint8 {
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page := address & 0xff00
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var mh memoryHandler
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if page == mmu.lastAddressPage {
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mh = mmu.lastAddressHandler
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} else {
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mh = mmu.accessRead(address)
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if address&0xf000 != 0xc000 {
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// Do not cache 0xC area as it may reconfigure the MMU
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mmu.lastAddressPage = page
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mmu.lastAddressHandler = mh
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}
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}
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if mh == nil {
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return 0xf4 // Or some random number
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}
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return mh.peek(address)
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}
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// Poke sets the data at the given address
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func (mmu *memoryManager) Poke(address uint16, value uint8) {
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mh := mmu.accessWrite(address)
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if mh != nil {
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mh.poke(address, value)
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}
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}
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// Memory initialization
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func (mmu *memoryManager) setCardROM(slot int, mh memoryHandler) {
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mmu.cardsROM[slot] = mh
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}
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func (mmu *memoryManager) setCardROMExtra(slot int, mh memoryHandler) {
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mmu.cardsROMExtra[slot] = mh
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}
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func (mmu *memoryManager) initLanguageRAM(groups uint8) {
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// Apple II+ language card or Saturn (up to 8 groups)
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mmu.physicalLangRAM = make([]*memoryRange, groups)
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mmu.physicalLangAltRAM = make([]*memoryRange, groups)
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for i := uint8(0); i < groups; i++ {
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mmu.physicalLangRAM[i] = newMemoryRange(0xd000, make([]uint8, 0x3000), fmt.Sprintf("LC RAM block %v", i))
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mmu.physicalLangAltRAM[i] = newMemoryRange(0xd000, make([]uint8, 0x1000), fmt.Sprintf("LC RAM Alt block %v", i))
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}
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}
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func (mmu *memoryManager) initExtendedRAM(groups int) {
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// Apple IIe 80 col card with 64Kb style RAM or RAMWorks (up to 256 banks)
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mmu.physicalExtRAM = make([]*memoryRange, groups)
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mmu.physicalExtAltRAM = make([]*memoryRange, groups)
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for i := 0; i < groups; i++ {
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mmu.physicalExtRAM[i] = newMemoryRange(0, make([]uint8, 0x10000), fmt.Sprintf("Extra RAM block %v", i))
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mmu.physicalExtAltRAM[i] = newMemoryRange(0xd000, make([]uint8, 0x1000), fmt.Sprintf("Extra RAM Alt block %v", i))
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}
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}
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// Memory configuration
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func (mmu *memoryManager) setActiveROMPage(page uint8) {
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mmu.romPage = page
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}
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func (mmu *memoryManager) getActiveROMPage() uint8 {
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return mmu.romPage
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}
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func (mmu *memoryManager) setLanguageRAM(readActive bool, writeActive bool, altBank bool) {
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mmu.lcActiveRead = readActive
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mmu.lcActiveWrite = writeActive
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mmu.lcAltBank = altBank
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}
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func (mmu *memoryManager) setLanguageRAMActiveBlock(block uint8) {
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block = block % uint8(len(mmu.physicalLangRAM))
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mmu.lcSelectedBlock = block
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}
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func (mmu *memoryManager) setExtendedRAMActiveBlock(block uint8) {
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if int(block) >= len(mmu.physicalExtRAM) {
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// How does the real hardware reacts?
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block = 0
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}
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mmu.extendedRAMBlock = block
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}
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