first public release
This commit is contained in:
ArthurFerreira2
GitHub
parent
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all:reinette-II
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reinette-II:reinette-II.c
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gcc -Wall -O3 reinette-II.c -o reinette-II -lncurses
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Binary file not shown.
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// Reinette II, emulates the Apple II computer
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// Copyright 2018 Arthur Ferreira
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// Last modified 19th of March 2019
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#include <stdlib.h>
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#include <ncurses.h>
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#include <unistd.h> // for usleep()
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#define ROMSTART 0xD000
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#define ROMSIZE 0x3000 // 12KB
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#define RAMSIZE 0xC000 // 48KB
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#define CARRY 0x01
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#define ZERO 0x02
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#define INTERRUPT 0x04
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#define DECIMAL 0x08
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#define BREAK 0x10
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#define UNDEFINED 0x20
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#define OVERFLOW 0x40
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#define SIGN 0x80
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uint8_t rom[ROMSIZE];
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uint8_t ram[RAMSIZE];
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struct Operand{
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bool setAcc;
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uint16_t value, address;
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}ope;
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struct Register{
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uint8_t A,X,Y,SR,SP;
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uint16_t PC;
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}reg;
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uint8_t key;
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bool videoNeedsRefresh;
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// MEMORY AND I/O
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static uint8_t readMem(uint16_t address){
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static uint8_t queries=0; // slow down emulation when looping for a keypress
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if (address < RAMSIZE) return(ram[address]);
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else if (address >= ROMSTART) return(rom[address - ROMSTART]);
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else if (address == 0xC000) { // KBD
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if (! ++queries) usleep(100); // sleep 100ms every 256 requests
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return(key);
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}
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else if (address == 0xC010){ // KBDSTRB
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key &= 0x7F; // unset bit 7
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return(key);
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}
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else return(0); // catch all
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}
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static void writeMem(uint16_t address, uint8_t value){
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if (address>=0x400 && address<=0x7FF) videoNeedsRefresh = true;
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if (address < RAMSIZE) ram[address] = value;
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else if (address == 0xC010) key &= 0x7F; // KBDSTRB, similar as in readMem
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}
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// RESET
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static void reset(){
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reg.PC = readMem(0xFFFC) | (readMem(0xFFFD) << 8);
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reg.SP = 0xFF;
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reg.SR |= UNDEFINED;
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ope.setAcc = false;
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ope.value = 0;
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ope.address = 0;
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}
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// STACK, SIGN AND ZERO FLAGS ROUTINES
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static void push(uint8_t value){
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writeMem(0x100 + reg.SP--, value);
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}
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uint8_t pull(){
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return(readMem(0x100 + ++reg.SP));
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}
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static void setSZ(uint8_t value){ // update both the Sign & Zero FLAGS
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if (value & 0x00FF) reg.SR &= ~ZERO;
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else reg.SR |= ZERO;
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if (value & 0x80) reg.SR |= SIGN;
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else reg.SR &= ~SIGN;
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}
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// ADDRESSING MODES
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static void IMP(){ // IMPlicit
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}
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static void ACC(){ // ACCumulator
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ope.value = reg.A;
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ope.setAcc = true;
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}
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static void IMM(){ // IMMediate
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ope.address = reg.PC++;
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ope.value = readMem(ope.address);
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}
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static void ZPG(){ // Zero PaGe
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ope.address = readMem(reg.PC++);
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ope.value = readMem(ope.address);
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}
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static void ZPX(){ // Zero Page,X
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ope.address = (readMem(reg.PC++) + reg.X) & 0xFF;
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ope.value = readMem(ope.address);
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}
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static void ZPY(){ // Zero Page,Y
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ope.address = (readMem(reg.PC++) + reg.Y) & 0xFF;
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ope.value = readMem(ope.address);
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}
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static void REL(){ // RELative (for branch instructions)
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ope.address = readMem(reg.PC++);
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if (ope.address & 0x80) ope.address |= 0xFF00; // branch backward
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}
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static void ABS(){ // ABSolute
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ope.address = readMem(reg.PC) | (readMem(reg.PC + 1) << 8);
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ope.value = readMem(ope.address);
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reg.PC += 2;
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}
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static void ABX(){ // ABsolute,X
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ope.address = (readMem(reg.PC) | (readMem(reg.PC + 1) << 8)) + reg.X;
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ope.value = readMem(ope.address);
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reg.PC += 2;
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}
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static void ABY(){ // ABsolute,Y
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ope.address = (readMem(reg.PC) | (readMem(reg.PC + 1) << 8)) + reg.Y;
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ope.value = readMem(ope.address);
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reg.PC += 2;
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}
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static void IND(){ // INDirect - JMP ($ABCD) with page-boundary wraparound bug
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uint16_t vector1 = readMem(reg.PC) | (readMem(reg.PC + 1) << 8);
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uint16_t vector2 = (vector1 & 0xFF00) | ((vector1 + 1) & 0x00FF);
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ope.address = readMem(vector1) | (readMem(vector2) << 8);
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ope.value = readMem(ope.address);
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reg.PC += 2;
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}
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static void IDX(){ // InDexed indirect X
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uint16_t vector1 = ((readMem(reg.PC++) + reg.X) & 0xFF);
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ope.address = readMem(vector1 & 0x00FF)|(readMem((vector1+1) & 0x00FF) << 8);
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ope.value = readMem(ope.address);
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}
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static void IDY(){ // InDirect Indexed Y
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uint16_t vector1 = readMem(reg.PC++);
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uint16_t vector2 = (vector1 & 0xFF00) | ((vector1 + 1) & 0x00FF);
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ope.address = (readMem(vector1) | (readMem(vector2) << 8)) + reg.Y;
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ope.value = readMem(ope.address);
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}
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// INSTRUCTIONS
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static void NOP(){ // NO Operation
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}
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static void BRK(){ // BReaK
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push(((++reg.PC) >> 8) & 0xFF);
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push(reg.PC & 0xFF);
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push(reg.SR | BREAK);
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reg.SR |= INTERRUPT;
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reg.PC = readMem(0xFFFE) | (readMem(0xFFFF) << 8);
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}
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static void CLD(){ // CLear Decimal
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reg.SR &= ~DECIMAL;
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}
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static void SED(){ // SEt Decimal
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reg.SR |= DECIMAL;
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}
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static void CLC(){ // CLear Carry
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reg.SR &= ~CARRY;
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}
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static void SEC(){ // SEt Carry
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reg.SR |= CARRY;
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}
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static void CLI(){ // CLear Interrupt
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reg.SR &= ~INTERRUPT;
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}
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static void SEI(){ // SEt Interrupt
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reg.SR |= INTERRUPT;
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}
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static void CLV(){ // CLear oVerflow
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reg.SR &= ~OVERFLOW;
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}
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static void LDA(){ // LoaD Accumulator
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reg.A = ope.value;
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setSZ(reg.A);
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}
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static void LDX(){ // LoaD X
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reg.X = ope.value;
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setSZ(reg.X);
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}
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static void LDY(){ // LoaD Y
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reg.Y = ope.value;
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setSZ(reg.Y);
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}
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static void STA(){ // STore Accumulator
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writeMem(ope.address, reg.A);
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}
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static void STX(){ // STore X
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writeMem(ope.address, reg.X);
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}
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static void STY(){ // STore Y
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writeMem(ope.address, reg.Y);
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}
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static void DEC(){ // DECrement
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writeMem(ope.address, --ope.value);
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setSZ(ope.value);
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}
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static void DEX(){ // DEcrement X
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setSZ(--reg.X);
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}
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static void DEY(){ // DEcrement Y
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setSZ(--reg.Y);
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}
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static void INC(){ // INCrement
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writeMem(ope.address, ++ope.value);
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setSZ(ope.value);
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}
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static void INX(){ // INcrement X
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setSZ(++reg.X);
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}
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static void INY(){ // INcrement Y
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setSZ(++reg.Y);
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}
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static void TAX(){ // Transfer Accumulator to X
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reg.X = reg.A;
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setSZ(reg.X);
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}
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static void TAY(){ // Transfer Accumulator to Y
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reg.Y = reg.A;
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setSZ(reg.Y);
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}
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static void TXA(){ // Transfer X to Accumulator
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reg.A = reg.X;
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setSZ(reg.A);
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}
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static void TYA(){ // Transfer Y to Accumulator
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reg.A = reg.Y;
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setSZ(reg.A);
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}
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static void TSX(){ // Transfer Sp to X
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reg.X = reg.SP;
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setSZ(reg.X);
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}
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static void TXS(){ // Transfer X to Sp
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reg.SP = reg.X;
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}
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static void BEQ(){ // Branch on EQual (zero set)
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if (reg.SR & ZERO) reg.PC += ope.address;
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}
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static void BNE(){ // Branch on Not Equal (zero clear)
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if (!(reg.SR & ZERO)) reg.PC += ope.address;
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}
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static void BMI(){ // Branch if MInus (ie when negative, when SIGN is set)
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if (reg.SR & SIGN) reg.PC += ope.address;
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}
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static void BPL(){ // Branch if PLus (ie when positive, when SIGN is clear)
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if (!(reg.SR & SIGN)) reg.PC += ope.address;
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}
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static void BVS(){ // Branch on oVerflow Set
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if (reg.SR & OVERFLOW) reg.PC += ope.address;
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}
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static void BVC(){ // Branch on oVerflow Clear
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if (!(reg.SR & OVERFLOW)) reg.PC += ope.address;
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}
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static void BCS(){ // Branch on Carry Set
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if (reg.SR & CARRY) reg.PC +=ope.address;
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}
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static void BCC(){ // Branch on Carry Clear
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if (!(reg.SR & CARRY)) reg.PC += ope.address;
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}
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static void PHA(){ // PusH A to the stack
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push(reg.A);
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}
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static void PLA(){ // PulL stack into A
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reg.A = pull();
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setSZ(reg.A);
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}
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static void PHP(){ // PusH Programm (Status) register to the stack
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push(reg.SR | BREAK);
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}
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static void PLP(){ // PulL stack into Programm (SR) register
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reg.SR = pull() | UNDEFINED;
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}
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static void JMP(){ // JuMP
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reg.PC = ope.address;
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}
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static void JSR(){ // Jump Sub-Routine
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push((--reg.PC >> 8) & 0xFF);
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push(reg.PC & 0xFF);
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reg.PC = ope.address;
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}
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static void RTS(){ // ReTurn from Sub-routine
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reg.PC = (pull() | (pull() << 8)) + 1;
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}
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static void RTI(){ // ReTurn from Interrupt
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reg.SR = pull();
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reg.PC = pull() | (pull() << 8);
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}
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static void CMP(){ // Compare with A
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setSZ(reg.A - ope.value);
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if (reg.A >= ope.value) reg.SR |= CARRY;
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else reg.SR &= ~CARRY;
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}
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static void CPX(){ // Compare with X
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setSZ(reg.X - ope.value);
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if (reg.X >= ope.value) reg.SR |= CARRY;
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else reg.SR &= ~CARRY;
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}
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static void CPY(){ // Compare with Y
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setSZ(reg.Y - ope.value);
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if (reg.Y >= ope.value) reg.SR |= CARRY;
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else reg.SR &= ~CARRY;
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}
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static void AND(){ // AND with A
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reg.A &= ope.value;
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setSZ(reg.A);
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}
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static void ORA(){ // OR with A
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reg.A |= ope.value;
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setSZ(reg.A);
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}
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static void EOR(){ // Exclusive Or with A
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reg.A ^= ope.value;
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setSZ(reg.A);
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}
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static void BIT(){ // BIT with A - http://www.6502.org/tutorials/vflag.html
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if (reg.A & ope.value) reg.SR &= ~ZERO;
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else reg.SR |= ZERO;
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reg.SR = (reg.SR & 0x3F) | (ope.value & 0xC0); // update SIGN & OVERFLOW
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}
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static void makeUpdates(uint8_t val){
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if (ope.setAcc) reg.A = val;
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else writeMem(ope.address, val);
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ope.setAcc = false;
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setSZ(val);
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}
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static void ASL(){ // Arithmetic Shift Left
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uint16_t result = (ope.value << 1);
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if (result & 0xFF00) reg.SR |= CARRY;
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else reg.SR &= ~CARRY;
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makeUpdates((uint8_t)(result & 0xFF));
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}
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static void LSR(){ // Logical Shift Right
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if (ope.value & 1) reg.SR |= CARRY;
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else reg.SR &= ~CARRY;
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makeUpdates((uint8_t)((ope.value >> 1) & 0xFF));
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}
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static void ROL(){ // ROtate Left
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uint16_t result = ((ope.value << 1) | (reg.SR & CARRY));
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if (result & 0x100) reg.SR |= CARRY;
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else reg.SR &= ~CARRY;
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makeUpdates((uint8_t)(result & 0xFF));
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}
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static void ROR(){ // ROtate Right
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uint16_t result = (ope.value >> 1) | ((reg.SR & CARRY) << 7);
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if (ope.value & 0x1) reg.SR |= CARRY;
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else reg.SR &= ~CARRY;
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makeUpdates((uint8_t)(result & 0xFF));
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}
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static void ADC(){ // ADd with Carry
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uint16_t result = reg.A + ope.value + (reg.SR & CARRY);
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setSZ(result);
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if (((result)^(reg.A ))&((result)^(ope.value))&0x0080) reg.SR |= OVERFLOW;
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else reg.SR &= ~OVERFLOW;
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if (reg.SR&DECIMAL) result += ((((result+0x66)^reg.A^ope.value)>>3)&0x22)*3;
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if (result & 0xFF00) reg.SR |= CARRY;
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else reg.SR &= ~CARRY;
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reg.A = (result & 0xFF);
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}
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static void SBC(){ // SuBtract with Carry
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ope.value ^= 0xFF;
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if (reg.SR & DECIMAL) ope.value -= 0x0066;
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uint16_t result = reg.A + ope.value + (reg.SR & CARRY);
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setSZ(result);
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if (((result)^(reg.A ))&((result)^(ope.value))&0x0080) reg.SR |= OVERFLOW;
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else reg.SR &= ~OVERFLOW;
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if (reg.SR&DECIMAL) result += ((((result+0x66)^reg.A^ope.value)>>3)&0x22)*3;
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if (result & 0xFF00) reg.SR |= CARRY;
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else reg.SR &= ~CARRY;
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reg.A = (result & 0xFF);
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}
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static void UND(){ // UNDefined (not a valid or supported 6502 opcode)
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printw("\n\n~ Illegal Instruction At Address $%04X ~\n", reg.PC - 1);
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BRK();
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}
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// JUMP TABLES
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static void (*instruction[])(void) = {
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BRK, ORA, UND, UND, UND, ORA, ASL, UND, PHP, ORA, ASL, UND, UND, ORA, ASL, UND,
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BPL, ORA, UND, UND, UND, ORA, ASL, UND, CLC, ORA, UND, UND, UND, ORA, ASL, UND,
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JSR, AND, UND, UND, BIT, AND, ROL, UND, PLP, AND, ROL, UND, BIT, AND, ROL, UND,
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BMI, AND, UND, UND, UND, AND, ROL, UND, SEC, AND, UND, UND, UND, AND, ROL, UND,
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RTI, EOR, UND, UND, UND, EOR, LSR, UND, PHA, EOR, LSR, UND, JMP, EOR, LSR, UND,
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BVC, EOR, UND, UND, UND, EOR, LSR, UND, CLI, EOR, UND, UND, UND, EOR, LSR, UND,
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RTS, ADC, UND, UND, UND, ADC, ROR, UND, PLA, ADC, ROR, UND, JMP, ADC, ROR, UND,
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BVS, ADC, UND, UND, UND, ADC, ROR, UND, SEI, ADC, UND, UND, UND, ADC, ROR, UND,
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UND, STA, UND, UND, STY, STA, STX, UND, DEY, UND, TXA, UND, STY, STA, STX, UND,
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||||
BCC, STA, UND, UND, STY, STA, STX, UND, TYA, STA, TXS, UND, UND, STA, UND, UND,
|
||||
LDY, LDA, LDX, UND, LDY, LDA, LDX, UND, TAY, LDA, TAX, UND, LDY, LDA, LDX, UND,
|
||||
BCS, LDA, UND, UND, LDY, LDA, LDX, UND, CLV, LDA, TSX, UND, LDY, LDA, LDX, UND,
|
||||
CPY, CMP, UND, UND, CPY, CMP, DEC, UND, INY, CMP, DEX, UND, CPY, CMP, DEC, UND,
|
||||
BNE, CMP, UND, UND, UND, CMP, DEC, UND, CLD, CMP, UND, UND, UND, CMP, DEC, UND,
|
||||
CPX, SBC, UND, UND, CPX, SBC, INC, UND, INX, SBC, NOP, UND, CPX, SBC, INC, UND,
|
||||
BEQ, SBC, UND, UND, UND, SBC, INC, UND, SED, SBC, UND, UND, UND, SBC, INC, UND
|
||||
};
|
||||
|
||||
static void (*addressing[])(void) = {
|
||||
IMP, IDX, IMP, IMP, IMP, ZPG, ZPG, IMP, IMP, IMM, ACC, IMP, IMP, ABS, ABS, IMP,
|
||||
REL, IDY, IMP, IMP, IMP, ZPX, ZPX, IMP, IMP, ABY, IMP, IMP, IMP, ABX, ABX, IMP,
|
||||
ABS, IDX, IMP, IMP, ZPG, ZPG, ZPG, IMP, IMP, IMM, ACC, IMP, ABS, ABS, ABS, IMP,
|
||||
REL, IDY, IMP, IMP, IMP, ZPX, ZPX, IMP, IMP, ABY, IMP, IMP, IMP, ABX, ABX, IMP,
|
||||
IMP, IDX, IMP, IMP, IMP, ZPG, ZPG, IMP, IMP, IMM, ACC, IMP, ABS, ABS, ABS, IMP,
|
||||
REL, IDY, IMP, IMP, IMP, ZPX, ZPX, IMP, IMP, ABY, IMP, IMP, IMP, ABX, ABX, IMP,
|
||||
IMP, IDX, IMP, IMP, IMP, ZPG, ZPG, IMP, IMP, IMM, ACC, IMP, IND, ABS, ABS, IMP,
|
||||
REL, IDY, IMP, IMP, IMP, ZPX, ZPX, IMP, IMP, ABY, IMP, IMP, IMP, ABX, ABX, IMP,
|
||||
IMP, IDX, IMP, IMP, ZPG, ZPG, ZPG, IMP, IMP, IMP, IMP, IMP, ABS, ABS, ABS, IMP,
|
||||
REL, IDY, IMP, IMP, ZPX, ZPX, ZPY, IMP, IMP, ABY, IMP, IMP, IMP, ABX, IMP, IMP,
|
||||
IMM, IDX, IMM, IMP, ZPG, ZPG, ZPG, IMP, IMP, IMM, IMP, IMP, ABS, ABS, ABS, IMP,
|
||||
REL, IDY, IMP, IMP, ZPX, ZPX, ZPY, IMP, IMP, ABY, IMP, IMP, ABX, ABX, ABY, IMP,
|
||||
IMM, IDX, IMP, IMP, ZPG, ZPG, ZPG, IMP, IMP, IMM, IMP, IMP, ABS, ABS, ABS, IMP,
|
||||
REL, IDY, IMP, IMP, IMP, ZPX, ZPX, IMP, IMP, ABY, IMP, IMP, IMP, ABX, ABX, IMP,
|
||||
IMM, IDX, IMP, IMP, ZPG, ZPG, ZPG, IMP, IMP, IMM, IMP, IMP, ABS, ABS, ABS, IMP,
|
||||
REL, IDY, IMP, IMP, IMP, ZPX, ZPX, IMP, IMP, ABY, IMP, IMP, IMP, ABX, ABX, IMP
|
||||
};
|
||||
|
||||
static int baseForLines[24] = { // helper for video generation
|
||||
0x400, 0x480, 0x500, 0x580, 0x600, 0x680, 0x700, 0x780,
|
||||
0x428, 0x4A8, 0x528, 0x5A8, 0x628, 0x6A8, 0x728, 0x7A8,
|
||||
0x450, 0x4D0, 0x550, 0x5D0, 0x650, 0x6D0, 0x750, 0x7D0
|
||||
};
|
||||
|
||||
|
||||
// PROGRAM ENTRY POINT
|
||||
|
||||
int main(int argc, char *argv[]) {
|
||||
int ch = 0;
|
||||
uint8_t opcode = 0;
|
||||
uint8_t character = 0;
|
||||
|
||||
// ncurses initialization
|
||||
initscr();
|
||||
raw();
|
||||
noecho();
|
||||
curs_set(0);
|
||||
qiflush();
|
||||
keypad (stdscr, TRUE);
|
||||
nodelay (stdscr, TRUE);
|
||||
scrollok(stdscr, TRUE);
|
||||
|
||||
// load the ROM
|
||||
FILE *f=fopen("apple2.rom","rb");
|
||||
if (f != NULL) fread(rom, sizeof(uint8_t), ROMSIZE, f);
|
||||
fclose(f);
|
||||
|
||||
// processor reset
|
||||
reset();
|
||||
|
||||
// main loop
|
||||
while(1){
|
||||
for (int i=0; i<100; i++){ // execute 100 instructions before a kbd scan
|
||||
opcode = readMem(reg.PC++); // FETCH and increment the Program Counter
|
||||
addressing[opcode](); // DECODE operands against the addressing mode
|
||||
instruction[opcode](); // EXECUTE the instruction
|
||||
|
||||
// DEBUG : print registers values and keypressed
|
||||
//move(25,0); // at bottom of screen
|
||||
//printw("PC-%04X A-%02X X-%02X Y-%02X S-%02X P-%02X KEY-%02X",reg.PC ,reg.A, reg.X, reg.Y, reg.SP, reg.SR, key);
|
||||
}
|
||||
usleep(225); // 225ms for 100 instructions gives roughly the original speed
|
||||
|
||||
// keyboard controller
|
||||
if (key < 0x80 && (ch = getch()) != ERR){ // non blocking read
|
||||
if (ch == KEY_F( 9)) reset(); // F09, reset
|
||||
else if (ch == KEY_F(10)) BRK(); // F10, break
|
||||
else if (ch == KEY_F(12)) { // F12, exit program
|
||||
endwin(); // reset terminal
|
||||
exit(0); // and terminate
|
||||
}
|
||||
else { // the key is sent to the emulator after some translations
|
||||
switch(key=(uint8_t)ch){
|
||||
case 0x0A: key = 0x0D; break; // LF to CR
|
||||
case 0x04: key = 0x08; break; // LEFT to BS
|
||||
case 0x05: key = 0x15; break; // RIGHT to LF
|
||||
case 0x07: key = 0x08; break; // BELL to BS
|
||||
}
|
||||
key |= 0x80; // set bit 7
|
||||
}
|
||||
}
|
||||
|
||||
// video controller only supports page 1 text mode
|
||||
if (videoNeedsRefresh){ // content changed
|
||||
move(0, 0);
|
||||
for(int line=0; line<24; line++){ // for each row
|
||||
for(int col=0; col<40; col++){ // for each column
|
||||
character = ram[baseForLines[line]+col]; // read video memory
|
||||
if (character == '`') character = '_'; // change cursor
|
||||
if (character < 0x40) attrset(A_REVERSE); // set REVERSE
|
||||
else if (character > 0x7F) attrset(A_NORMAL); // set NORMAL
|
||||
else attrset(A_BLINK); // set FLASHING
|
||||
character &= 0x7F; // unset bit 7
|
||||
if (character > 0x5F) character &= 0x3F; // shifts to obtain
|
||||
if (character < 0x20) character |= 0x40; // the ASCII codes
|
||||
printw("%c", character); // print character
|
||||
|
||||
}
|
||||
printw("%c", 0x0A); // carriage return
|
||||
}
|
||||
videoNeedsRefresh = false;
|
||||
attrset(A_NORMAL);
|
||||
}
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue