mirror of
https://github.com/edmccard/twoapple-reboot.git
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Add opcodes to new cpu (BRK)
This commit is contained in:
edmccard
parent
d3a95c455d
commit
04f05fbc9a
587
src/cpu6502.d
587
src/cpu6502.d
@ -40,6 +40,17 @@ version(OpFunctions)
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{
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enum versionCheck = 2;
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enum opArray = true;
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// With free functions, strict and cumulative need to be set by
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// version.
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version(Strict)
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enum vStrict = true;
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else
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enum vStrict = false;
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version(Cumulative)
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enum vCumulative = true;
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else
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enum vCumulative = false;
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}
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// OpSwitch: each opcode is inlined in a 256-case switch.
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@ -105,7 +116,10 @@ final class Cpu(string chip, bool strict, bool cumulative)
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ubyte N, Z;
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bool V, D, I, C;
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static if (opArray) mixin(OpArrayDef());
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static if (opArray)
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{
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mixin(OpArrayDef());
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}
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// TODO: other methods for stopping cpu
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bool keepRunning;
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@ -122,7 +136,7 @@ final class Cpu(string chip, bool strict, bool cumulative)
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D = ((p & 0x08) != 0);
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I = ((p & 0x04) != 0);
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Z = ((p & 0x02) ? 0 : 1);
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C = ((val & 0x01) != 0);
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C = ((p & 0x01) != 0);
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}
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final ubyte statusToByte()
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@ -141,23 +155,33 @@ final class Cpu(string chip, bool strict, bool cumulative)
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keepRunning = continuous;
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// TODO debugging info?
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ubyte opcode;
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static if (!opArray)
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{
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static if (cumulative) int cycles;
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}
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do {
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// XXX check signals
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// XXX figure out cumulative/final cycle stuff
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static if (cumulative) {}
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else
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static if (cumulative && !opArray)
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cycles = 1;
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// XXX figure out final cycle stuff
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static if (!cumulative)
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clock.tick();
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// XXX check signals, NMI/IRQ delays, etc.
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opcode = memory.read(PC++);
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mixin(OpExecute(_chip));
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mixin(OpExecute(_chip, strict, cumulative));
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} while (keepRunning);
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}
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version(OpDelegates) mixin (OpBodies(_chip));
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version(OpDelegates) mixin (OpBodies(_chip, strict, cumulative));
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}
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version(OpFunctions) mixin(OpBodies("6502"));
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version(OpFunctions) mixin(OpBodies("65C02"));
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enum ushort IRQ_VECTOR = 0xFFFE;
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private:
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version(OpFunctions) mixin(OpBodies("6502", vStrict, vCumulative));
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version(OpFunctions) mixin(OpBodies("65C02", vStrict, vCumulative));
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string OpArrayDef()
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@ -189,7 +213,7 @@ string OpArrayInit()
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}
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}
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string OpBodies(string chip)
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string OpBodies(string chip, bool strict, bool cumulative)
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{
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static if (!opArray) return "";
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else
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@ -199,37 +223,40 @@ string OpBodies(string chip)
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{
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version(OpDelegates)
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ret ~= "final void opcode_" ~ Hex2(op) ~ "()\n{\n" ~
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OpBody(op, chip) ~ "}\n";
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If!(cumulative)("int cycles = 1;\n") ~
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OpBody(op, chip, strict, cumulative) ~ "}\n";
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version(OpFunctions)
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ret ~= "void opcode_" ~ Hex2(op) ~
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"(T)(T cpu) if (is" ~ chip ~ "!T)\n{\n" ~
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OpBody(op, chip) ~ "}\n";
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If!(cumulative)("int cycles = 1;\n") ~
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OpBody(op, chip, strict, cumulative) ~ "}\n";
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}
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return ret;
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}
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}
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string OpExecute(string chip)
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string OpExecute(string chip, bool strict, bool cumulative)
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{
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version(OpDelegates)
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return q{opcodes[opcode]();};
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version(OpFunctions)
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return q{opcodes[opcode](this);};
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version(OpSwitch)
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return Switch256(chip);
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return Switch256(chip, strict, cumulative);
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version(OpNestedSwitch)
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return Switch16x16(chip);
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return Switch16x16(chip, strict, cumulative);
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}
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string Switch256(string chip)
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string Switch256(string chip, bool strict, bool cumulative)
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{
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string ret = "final switch (opcode)\n{\n";
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foreach (op; 0..256)
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ret ~= "case 0x" ~ Hex2(op) ~ ":\n" ~ OpBody(op, chip) ~ "break;\n\n";
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ret ~= "case 0x" ~ Hex2(op) ~ ":\n" ~
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OpBody(op, chip, strict, cumulative) ~ "break;\n";
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return ret ~ "}\n";
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}
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string Switch16x16(string chip)
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string Switch16x16(string chip, bool strict, bool cumulative)
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{
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string ret = "final switch (opcode & 0xF0)\n{\n";
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foreach (opHi; 0..16)
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@ -239,8 +266,9 @@ string Switch16x16(string chip)
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foreach (opLo; 0..16)
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{
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int op = opLo | (opHi << 4);
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ret ~= "case 0x0" ~ Hex1(opLo) ~ ":\n" ~ OpBody(op, chip) ~
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"break;\n\n";
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ret ~= "case 0x0" ~ Hex1(opLo) ~ ":\n" ~
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OpBody(op, chip, strict, cumulative) ~
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"break;\n";
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}
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ret ~= "}\nbreak;\n";
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}
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@ -248,12 +276,509 @@ string Switch16x16(string chip)
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}
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string OpBody(int op, string chip)
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string OpBody(int op, string chip, bool strict, bool cumulative)
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{
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return "";
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final switch (opName(op, chip))
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{
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case "BRK":
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return Break(strict, cumulative);
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case "RTI":
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return "";
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case "JSR":
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return "";
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case "RTS":
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return "";
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case "JMP":
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return ""; // address modes
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case "KIL":
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return "";
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case "BPL":
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return "";
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case "BMI":
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return "";
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case "BVC":
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return "";
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case "BVS":
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return "";
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case "BRA":
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return "";
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case "BCC":
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return "";
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case "BCS":
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return "";
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case "BNE":
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return "";
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case "BEQ":
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return "";
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case "CLC":
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return "";
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case "SEC":
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return "";
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case "CLI":
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return "";
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case "SEI":
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return "";
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case "CLV":
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return "";
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case "CLD":
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return "";
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case "SED":
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return "";
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case "NOP":
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return ""; // address modes
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case "TAX":
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return "";
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case "TXA":
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return "";
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case "TAY":
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return "";
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case "TYA":
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return "";
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case "TSX":
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return "";
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case "TXS":
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return "";
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case "DEX":
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return "";
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case "DEY":
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return "";
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case "INX":
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return "";
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case "INY":
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return "";
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case "PLP":
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return "";
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case "PLA":
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return "";
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case "PLX":
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return "";
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case "PLY":
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return "";
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case "PHP":
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return "";
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case "PHA":
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return "";
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case "PHX":
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return "";
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case "PHY":
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return "";
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case "LDA":
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return "";
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case "LDX":
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return "";
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case "LDY":
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return "";
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case "STA":
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return "";
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case "STX":
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return "";
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case "STY":
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return "";
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case "STZ":
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return "";
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case "BIT":
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return ""; // address modes
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case "CMP":
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return "";
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case "CPX":
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return "";
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case "CPY":
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return "";
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case "ORA":
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return "";
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case "AND":
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return "";
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case "EOR":
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return "";
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case "ADC":
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return ""; // n/c (op, cyc)
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case "SBC":
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return ""; // n/c (op, cyc)
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case "ASL":
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return ""; // n/c (op, cyc)
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case "ROL":
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return ""; // n/c (op, cyc)
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case "LSR":
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return ""; // n/c (op, cyc)
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case "ROR":
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return ""; // n/c (op, cyc)
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case "INC":
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return ""; // n/c (op, +ina)
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case "DEC":
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return ""; // n/c (op, +dea)
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case "TRB":
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return "";
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case "TSB":
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return "";
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case "LAS":
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return "";
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case "LAX":
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return ""; // address modes
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case "SAX":
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return "";
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case "ANC":
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return "";
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case "ALR":
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return "";
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case "ARR":
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return "";
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case "AXS":
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return "";
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case "AHX":
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return "";
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case "SHY":
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return "";
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case "SHX":
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return "";
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case "TAS":
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return "";
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case "XAA":
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return "";
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case "SLO":
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return "";
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case "RLA":
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return "";
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case "SRE":
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return "";
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case "RRA":
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return "";
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case "DCP":
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return "";
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case "ISC":
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return "";
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}
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}
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string Break(bool s, bool c)
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{
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return Peek(Attr("PC"), s, c) ~
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IncPC() ~
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PushPC(s, c) ~
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Push(Attr("statusToByte()"), s, c) ~
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Set(Attr("I")) ~
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ReadWord(Attr("PC"), "IRQ_VECTOR", c) ~
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Done(c);
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}
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string PreAccess(bool cumulative)
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{
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return If!(cumulative)("++cycles;\n", Attr("clock") ~ ".tick();\n");
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}
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string Peek(string addr, bool strict, bool cumulative)
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{
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return PreAccess(cumulative) ~
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If!(strict)(Attr("memory") ~ ".read(" ~ addr ~");\n");
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}
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string Read(string var, string addr, bool c)
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{
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return PreAccess(c) ~
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var ~ " = " ~ Attr("memory") ~ ".read(" ~ addr ~");\n";
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}
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string Write(string addr, string val, bool cumulative)
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{
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return If!(cumulative)("++cycles;\n", Attr("clock") ~ ".tick();\n") ~
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Attr("memory") ~ ".write(" ~ addr ~ ", " ~ val ~ ");\n";
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}
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string ReadWord(string var, string addr, bool c)
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{
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return PreAccess(c) ~
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var ~ " = " ~ Attr("memory") ~ ".read(" ~ addr ~");\n" ~
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PreAccess(c) ~
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var ~ " |= (" ~ Attr("memory") ~
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".read(cast(ushort)((" ~ addr ~ ") + 1)) << 8);\n";
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}
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string IncPC()
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{
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return "++" ~ Attr("PC") ~ ";\n";
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}
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string IncSP()
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{
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return "++" ~ Attr("S") ~ ";\n";
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}
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string DecSP()
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{
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return "--" ~ Attr("S") ~ ";\n";
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}
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string Push(string val, bool s, bool c)
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{
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return Write("0x0100 + " ~ Attr("S"), val, c) ~
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DecSP();
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}
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string PushPC(bool s, bool c)
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{
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return Push(HiByte(Attr("PC")), s, c) ~
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Push(LoByte(Attr("PC")), s, c);
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}
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string Set(string flag)
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{
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return flag ~ " = true;\n";
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}
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string Done(bool cumulative)
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{
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return If!(cumulative)(Attr("clock") ~ ".tick(cycles);\n");
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}
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string Attr(string var)
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{
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version(OpFunctions)
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return "cpu." ~ var;
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else
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return var;
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}
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string HiByte(string var)
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{
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return var ~ " >> 8";
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}
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string LoByte(string var)
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{
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return var ~ " & 0xff";
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}
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string If(alias cond)(string yes, string no = "")
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{
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if (cond)
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return yes;
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else
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return no;
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}
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string opName(int op, string chip)
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{
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if (chip == "6502")
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return OP_NAMES_6502[op];
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else
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return OP_NAMES_65C02[op];
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}
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int opMode(int op, string chip)
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{
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if (chip == "6502")
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return ADDR_MODES_6502[op];
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else
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return ADDR_MODES_65C02[op];
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}
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int opExCyc(int op, string chip)
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{
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if (chip == "6502")
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return EXTRA_CYCLES_6502[op];
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else
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return EXTRA_CYCLES_65C02[op];
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}
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// Opcode names.
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immutable OP_NAMES_6502 = [
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"BRK", "ORA", "KIL", "SLO", "NOP", "ORA", "ASL", "SLO",
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"PHP", "ORA", "ASL", "ANC", "NOP", "ORA", "ASL", "SLO",
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"BPL", "ORA", "KIL", "SLO", "NOP", "ORA", "ASL", "SLO",
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"CLC", "ORA", "NOP", "SLO", "NOP", "ORA", "ASL", "SLO",
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"JSR", "AND", "KIL", "RLA", "BIT", "AND", "ROL", "RLA",
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"PLP", "AND", "ROL", "ANC", "BIT", "AND", "ROL", "RLA",
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"BMI", "AND", "KIL", "RLA", "NOP", "AND", "ROL", "RLA",
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"SEC", "AND", "NOP", "RLA", "NOP", "AND", "ROL", "RLA",
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"RTI", "EOR", "KIL", "SRE", "NOP", "EOR", "LSR", "SRE",
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"PHA", "EOR", "LSR", "ALR", "JMP", "EOR", "LSR", "SRE",
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"BVC", "EOR", "KIL", "SRE", "NOP", "EOR", "LSR", "SRE",
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"CLI", "EOR", "NOP", "SRE", "NOP", "EOR", "LSR", "SRE",
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"RTS", "ADC", "KIL", "RRA", "NOP", "ADC", "ROR", "RRA",
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"PLA", "ADC", "ROR", "ARR", "JMP", "ADC", "ROR", "RRA",
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"BVS", "ADC", "KIL", "RRA", "NOP", "ADC", "ROR", "RRA",
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"SEI", "ADC", "NOP", "RRA", "NOP", "ADC", "ROR", "RRA",
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"NOP", "STA", "NOP", "SAX", "STY", "STA", "STX", "SAX",
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"DEY", "NOP", "TXA", "XAA", "STY", "STA", "STX", "SAX",
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"BCC", "STA", "KIL", "AHX", "STY", "STA", "STX", "SAX",
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"TYA", "STA", "TXS", "TAS", "SHY", "STA", "SHX", "AHX",
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"LDY", "LDA", "LDX", "LAX", "LDY", "LDA", "LDX", "LAX",
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"TAY", "LDA", "TAX", "LAX", "LDY", "LDA", "LDX", "LAX",
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"BCS", "LDA", "KIL", "LAX", "LDY", "LDA", "LDX", "LAX",
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"CLV", "LDA", "TSX", "LAS", "LDY", "LDA", "LDX", "LAX",
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"CPY", "CMP", "NOP", "DCP", "CPY", "CMP", "DEC", "DCP",
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"INY", "CMP", "DEX", "AXS", "CPY", "CMP", "DEC", "DCP",
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"BNE", "CMP", "KIL", "DCP", "NOP", "CMP", "DEC", "DCP",
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"CLD", "CMP", "NOP", "DCP", "NOP", "CMP", "DEC", "DCP",
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"CPX", "SBC", "NOP", "ISC", "CPX", "SBC", "INC", "ISC",
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"INX", "SBC", "NOP", "SBC", "CPX", "SBC", "INC", "ISC",
|
||||
"BEQ", "SBC", "KIL", "ISC", "NOP", "SBC", "INC", "ISC",
|
||||
"SED", "SBC", "NOP", "ISC", "NOP", "SBC", "INC", "ISC"
|
||||
];
|
||||
|
||||
immutable OP_NAMES_65C02 = [
|
||||
"BRK", "ORA", "NOP", "NOP", "TSB", "ORA", "ASL", "NOP",
|
||||
"PHP", "ORA", "ASL", "NOP", "TSB", "ORA", "ASL", "NOP",
|
||||
"BPL", "ORA", "ORA", "NOP", "TRB", "ORA", "ASL", "NOP",
|
||||
"CLC", "ORA", "INC", "NOP", "TRB", "ORA", "ASL", "NOP",
|
||||
"JSR", "AND", "NOP", "NOP", "BIT", "AND", "ROL", "NOP",
|
||||
"PLP", "AND", "ROL", "NOP", "BIT", "AND", "ROL", "NOP",
|
||||
"BMI", "AND", "AND", "NOP", "BIT", "AND", "ROL", "NOP",
|
||||
"SEC", "AND", "DEC", "NOP", "BIT", "AND", "ROL", "NOP",
|
||||
"RTI", "EOR", "NOP", "NOP", "NOP", "EOR", "LSR", "NOP",
|
||||
"PHA", "EOR", "LSR", "NOP", "JMP", "EOR", "LSR", "NOP",
|
||||
"BVC", "EOR", "EOR", "NOP", "NOP", "EOR", "LSR", "NOP",
|
||||
"CLI", "EOR", "PHY", "NOP", "NOP", "EOR", "LSR", "NOP",
|
||||
"RTS", "ADC", "NOP", "NOP", "STZ", "ADC", "ROR", "NOP",
|
||||
"PLA", "ADC", "ROR", "NOP", "JMP", "ADC", "ROR", "NOP",
|
||||
"BVS", "ADC", "ADC", "NOP", "STZ", "ADC", "ROR", "NOP",
|
||||
"SEI", "ADC", "PLY", "NOP", "JMP", "ADC", "ROR", "NOP",
|
||||
"BRA", "STA", "NOP", "NOP", "STY", "STA", "STX", "NOP",
|
||||
"DEY", "BIT", "TXA", "NOP", "STY", "STA", "STX", "NOP",
|
||||
"BCC", "STA", "STA", "NOP", "STY", "STA", "STX", "NOP",
|
||||
"TYA", "STA", "TXS", "NOP", "STZ", "STA", "STZ", "NOP",
|
||||
"LDY", "LDA", "LDX", "NOP", "LDY", "LDA", "LDX", "NOP",
|
||||
"TAY", "LDA", "TAX", "NOP", "LDY", "LDA", "LDX", "NOP",
|
||||
"BCS", "LDA", "LDA", "NOP", "LDY", "LDA", "LDX", "NOP",
|
||||
"CLV", "LDA", "TSX", "NOP", "LDY", "LDA", "LDX", "NOP",
|
||||
"CPY", "CMP", "NOP", "NOP", "CPY", "CMP", "DEC", "NOP",
|
||||
"INY", "CMP", "DEX", "NOP", "CPY", "CMP", "DEC", "NOP",
|
||||
"BNE", "CMP", "CMP", "NOP", "NOP", "CMP", "DEC", "NOP",
|
||||
"CLD", "CMP", "PHX", "NOP", "NOP", "CMP", "DEC", "NOP",
|
||||
"CPX", "SBC", "NOP", "NOP", "CPX", "SBC", "INC", "NOP",
|
||||
"INX", "SBC", "NOP", "NOP", "CPX", "SBC", "INC", "NOP",
|
||||
"BEQ", "SBC", "SBC", "NOP", "NOP", "SBC", "INC", "NOP",
|
||||
"SED", "SBC", "PLX", "NOP", "NOP", "SBC", "INC", "NOP"
|
||||
];
|
||||
|
||||
|
||||
// Addressing modes.
|
||||
|
||||
enum { IMP, IMM, ZP, ZPX, ZPY, IZX, IZY, ABS, ABX, ABY, IND, REL,
|
||||
ZPI, ABI, NP1, NP8, KIL }
|
||||
|
||||
immutable ADDR_MODES_6502 = [
|
||||
IMP, IZX, KIL, IZX, ZP, ZP, ZP, ZP,
|
||||
IMP, IMM, IMP, IMM, ABS, ABS, ABS, ABS,
|
||||
REL, IZY, KIL, IZY, ZPX, ZPX, ZPX, ZPX,
|
||||
IMP, ABY, IMP, ABY, ABX, ABX, ABX, ABX,
|
||||
ABS, IZX, KIL, IZX, ZP, ZP, ZP, ZP,
|
||||
IMP, IMM, IMP, IMM, ABS, ABS, ABS, ABS,
|
||||
REL, IZY, KIL, IZY, ZPX, ZPX, ZPX, ZPX,
|
||||
IMP, ABY, IMP, ABY, ABX, ABX, ABX, ABX,
|
||||
IMP, IZX, KIL, IZX, ZP, ZP, ZP, ZP,
|
||||
IMP, IMM, IMP, IMM, ABS, ABS, ABS, ABS,
|
||||
REL, IZY, KIL, IZY, ZPX, ZPX, ZPX, ZPX,
|
||||
IMP, ABY, IMP, ABY, ABX, ABX, ABX, ABX,
|
||||
IMP, IZX, KIL, IZX, ZP, ZP, ZP, ZP,
|
||||
IMP, IMM, IMP, IMM, IND, ABS, ABS, ABS,
|
||||
REL, IZY, KIL, IZY, ZPX, ZPX, ZPX, ZPX,
|
||||
IMP, ABY, IMP, ABY, ABX, ABX, ABX, ABX,
|
||||
IMM, IZX, IMM, IZX, ZP, ZP, ZP, ZP,
|
||||
IMP, IMM, IMP, IMM, ABS, ABS, ABS, ABS,
|
||||
REL, IZY, KIL, IZY, ZPX, ZPX, ZPY, ZPY,
|
||||
IMP, ABY, IMP, ABY, ABX, ABX, ABY, ABY,
|
||||
IMM, IZX, IMM, IZX, ZP, ZP, ZP, ZP,
|
||||
IMP, IMM, IMP, IMM, ABS, ABS, ABS, ABS,
|
||||
REL, IZY, KIL, IZY, ZPX, ZPX, ZPY, ZPY,
|
||||
IMP, ABY, IMP, ABY, ABX, ABX, ABY, ABY,
|
||||
IMM, IZX, IMM, IZX, ZP, ZP, ZP, ZP,
|
||||
IMP, IMM, IMP, IMM, ABS, ABS, ABS, ABS,
|
||||
REL, IZY, KIL, IZY, ZPX, ZPX, ZPX, ZPX,
|
||||
IMP, ABY, IMP, ABY, ABX, ABX, ABX, ABX,
|
||||
IMM, IZX, IMM, IZX, ZP, ZP, ZP, ZP,
|
||||
IMP, IMM, IMP, IMM, ABS, ABS, ABS, ABS,
|
||||
REL, IZY, KIL, IZY, ZPX, ZPX, ZPX, ZPX,
|
||||
IMP, ABY, IMP, ABY, ABX, ABX, ABX, ABX
|
||||
];
|
||||
|
||||
immutable ADDR_MODES_65C02 = [
|
||||
IMP, IZX, IMM, NP1, ZP, ZP, ZP, NP1,
|
||||
IMP, IMM, IMP, NP1, ABS, ABS, ABS, NP1,
|
||||
REL, IZY, ZPI, NP1, ZP, ZPX, ZPX, NP1,
|
||||
IMP, ABY, IMP, NP1, ABS, ABX, ABX, NP1,
|
||||
ABS, IZX, IMM, NP1, ZP, ZP, ZP, NP1,
|
||||
IMP, IMM, IMP, NP1, ABS, ABS, ABS, NP1,
|
||||
REL, IZY, ZPI, NP1, ZPX, ZPX, ZPX, NP1,
|
||||
IMP, ABY, IMP, NP1, ABX, ABX, ABX, NP1,
|
||||
IMP, IZX, IMM, NP1, ZP, ZP, ZP, NP1,
|
||||
IMP, IMM, IMP, NP1, ABS, ABS, ABS, NP1,
|
||||
REL, IZY, ZPI, NP1, ZPX, ZPX, ZPX, NP1,
|
||||
IMP, ABY, IMP, NP1, NP8, ABX, ABX, NP1,
|
||||
IMP, IZX, IMM, NP1, ZP, ZP, ZP, NP1,
|
||||
IMP, IMM, IMP, NP1, IND, ABS, ABS, NP1,
|
||||
REL, IZY, ZPI, NP1, ZPX, ZPX, ZPX, NP1,
|
||||
IMP, ABY, IMP, NP1, ABI, ABX, ABX, NP1,
|
||||
REL, IZX, IMM, NP1, ZP, ZP, ZP, NP1,
|
||||
IMP, IMM, IMP, NP1, ABS, ABS, ABS, NP1,
|
||||
REL, IZY, ZPI, NP1, ZPX, ZPX, ZPY, NP1,
|
||||
IMP, ABY, IMP, NP1, ABX, ABX, ABX, NP1,
|
||||
IMM, IZX, IMM, NP1, ZP, ZP, ZP, NP1,
|
||||
IMP, IMM, IMP, NP1, ABS, ABS, ABS, NP1,
|
||||
REL, IZY, ZPI, NP1, ZPX, ZPX, ZPY, NP1,
|
||||
IMP, ABY, IMP, NP1, ABX, ABX, ABY, NP1,
|
||||
IMM, IZX, IMM, NP1, ZP, ZP, ZP, NP1,
|
||||
IMP, IMM, IMP, NP1, ABS, ABS, ABS, NP1,
|
||||
REL, IZY, ZPI, NP1, ZPX, ZPX, ZPX, NP1,
|
||||
IMP, ABY, IMP, NP1, ABX, ABX, ABX, NP1,
|
||||
IMM, IZX, IMM, NP1, ZP, ZP, ZP, NP1,
|
||||
IMP, IMM, IMP, NP1, ABS, ABS, ABS, NP1,
|
||||
REL, IZY, ZPI, NP1, ZPX, ZPX, ZPX, NP1,
|
||||
IMP, ABY, IMP, NP1, ABX, ABX, ABX, NP1
|
||||
];
|
||||
|
||||
|
||||
// Page-crossing extra cycles.
|
||||
|
||||
immutable EXTRA_CYCLES_6502 = [
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1,
|
||||
];
|
||||
|
||||
immutable EXTRA_CYCLES_65C02 = [
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
|
||||
];
|
||||
|
||||
|
||||
// Custom hex printing.
|
||||
// (to!string(x, 16) uses uppercase, which makes "8" and "B" hard to
|
||||
// tell apart, and format("%0.2x", x) can't be used in CTFE.)
|
||||
@ -273,19 +798,3 @@ string Hex2(int dec)
|
||||
return HEX_DIGITS[highNybble..highNybble+1] ~
|
||||
HEX_DIGITS[lowNybble..lowNybble+1];
|
||||
}
|
||||
|
||||
|
||||
alias Cpu!("6502", false, false) T1;
|
||||
alias Cpu!("6502", false, true) T2;
|
||||
alias Cpu!("6502", true, false) T3;
|
||||
alias Cpu!("6502", true, true) T4;
|
||||
alias Cpu!("65C02", false, false) T5;
|
||||
alias Cpu!("65C02", false, true) T6;
|
||||
alias Cpu!("65C02", true, false) T7;
|
||||
alias Cpu!("65C02", true, true) T8;
|
||||
|
||||
void main()
|
||||
{
|
||||
import std.stdio;
|
||||
writeln(Switch16x16("6502"));
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user