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timing tests
This commit is contained in:
edmccard
parent
04662745b0
commit
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784
test/test_bus.d
Normal file
784
test/test_bus.d
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@ -0,0 +1,784 @@
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module test_bus;
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import std.algorithm, std.array, std.conv, std.exception, std.string;
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import test.base;
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T[] If(alias cond, T)(T[] actions)
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{
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if (cond)
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return actions;
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else
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return [];
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}
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template timesetup_t(T)
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{
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alias Bus[] function(T, ref TestMemory, out int) timesetup_t;
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}
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/// Bus access pattern for register opcodes.
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auto accesses_reg(T)(T cpu, ref TestMemory mem, out int cycles)
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if (isCpu!T)
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{
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auto pc = getPC(cpu);
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auto opcode = mem[pc];
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assert(REG_OPS!T.canFind(opcode));
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cycles = 2;
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return [Bus(Action.READ, pc)] ~
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If!(isStrict!T)(
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[Bus(Action.READ, pc+1)]);
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}
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/// Bus access pattern for push opcodes.
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auto accesses_push(T)(T cpu, ref TestMemory mem, out int cycles)
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if (isCpu!T)
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{
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auto pc = getPC(cpu);
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auto opcode = mem[pc];
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assert(PUSH_OPS!T.canFind(opcode));
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auto sp = getSP(cpu);
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cycles = 3;
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return [Bus(Action.READ, pc)] ~
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If!(isStrict!T)(
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[Bus(Action.READ, pc+1)]) ~
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[Bus(Action.WRITE, sp)];
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}
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/// Bus access pattern for pull opcodes.
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auto accesses_pull(T)(T cpu, ref TestMemory mem, out int cycles)
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if (isCpu!T)
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{
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auto pc = getPC(cpu);
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auto opcode = mem[pc];
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assert(PULL_OPS!T.canFind(opcode));
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auto sp = getSP(cpu);
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auto sp1 = pageWrapAdd(sp, 1);
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cycles = 4;
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return [Bus(Action.READ, pc)] ~
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If!(isStrict!T)(
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[Bus(Action.READ, pc+1),
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Bus(Action.READ, sp)]) ~
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[Bus(Action.READ, sp1)];
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}
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/// Bus access pattern for immediate mode opcodes.
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auto accesses_imm(T)(T cpu, ref TestMemory mem, out int cycles)
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if (isCpu!T)
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{
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auto pc = getPC(cpu);
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auto opcode = mem[pc];
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assert(IMM_OPS!T.canFind(opcode));
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bool decimal = isCMOS!T && isStrict!T && getFlag(cpu, Flag.D) &&
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BCD_OPS!T.canFind(opcode);
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cycles = 2 + decimal;
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return [Bus(Action.READ, pc),
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Bus(Action.READ, pc+1)] ~
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If!decimal(
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[Bus(Action.READ, pc+2)]);
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}
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/// Bus access pattern for branch opcodes.
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auto accesses_rel(T)(T cpu, ref TestMemory mem, out int cycles)
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if (isCpu!T)
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{
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auto pc = getPC(cpu);
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auto opcode = mem[pc], op1 = mem[pc+1];
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assert(BRANCH_OPS!T.canFind(opcode));
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auto base = cast(ushort)(pc + 2);
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bool branch = wouldBranch(cpu, opcode);
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ushort wrongPage = pageWrapAdd(base, cast(byte)op1);
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bool px = wrongPage != pageCrossAdd(base, cast(byte)op1);
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ushort wrongAddr = isNMOS!T ? wrongPage : base;
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cycles = 2 + branch + px;
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return [Bus(Action.READ, pc),
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Bus(Action.READ, pc+1)] ~
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If!branch(If!(isStrict!T)(
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[Bus(Action.READ, pc+2)] ~
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If!px(
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[Bus(Action.READ, wrongAddr)])));
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}
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/// Bus access pattern for zeropage mode opcodes.
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auto accesses_zpg(T)(T cpu, ref TestMemory mem, out int cycles)
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if (isCpu!T)
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{
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auto pc = getPC(cpu);
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auto opcode = mem[pc], op1 = mem[pc+1];
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assert(ZPG_OPS!T.canFind(opcode));
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cycles = 2; // + accesses_end
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return [Bus(Action.READ, pc),
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Bus(Action.READ, pc+1)] ~
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accesses_end(cpu, opcode, 2, op1, cycles);
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}
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/// Bus access pattern for absolute mode opcodes.
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auto accesses_abs(T)(T cpu, ref TestMemory mem, out int cycles)
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if (isCpu!T)
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{
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auto pc = getPC(cpu);
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auto opcode = mem[pc], op1 = mem[pc+1], op2 = mem[pc+2];
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assert(ABS_OPS!T.canFind(opcode));
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auto addr = address(op1, op2);
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cycles = 3; // + accesses_end
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return [Bus(Action.READ, pc),
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Bus(Action.READ, pc+1),
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Bus(Action.READ, pc+2)] ~
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accesses_end(cpu, opcode, 3, addr, cycles);
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}
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/// Bus access pattern for zeropage,x/y mode opcodes.
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auto accesses_zpxy(T)(T cpu, ref TestMemory mem, out int cycles)
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if (isCpu!T)
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{
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auto pc = getPC(cpu);
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auto opcode = mem[pc], op1 = mem[pc+1];
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bool useX = ZPX_OPS!T.canFind(opcode);
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assert(useX || ZPY_OPS!T.canFind(opcode));
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auto idx = (useX ? getX(cpu) : getY(cpu));
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auto addr = pageWrapAdd(op1, idx);
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cycles = 3; // + accesses_end
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return [Bus(Action.READ, pc),
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Bus(Action.READ, pc+1)] ~
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If!(isStrict!T)(
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If!(isNMOS!T)(
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[Bus(Action.READ, op1)]) ~
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If!(isCMOS!T)(
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[Bus(Action.READ, pc+2)])) ~ // XXX
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accesses_end(cpu, opcode, 2, addr, cycles);
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/*
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* According to "Understanding the Apple IIe", the extra read on
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* the 65C02 (marked XXX above) is the address of the last operand
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* byte (pc + 1).
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*/
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}
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/// Bus access pattern for absolute,x/y mode opcodes.
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auto accesses_abxy(T)(T cpu, ref TestMemory mem, out int cycles)
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if (isCpu!T)
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{
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auto pc = getPC(cpu);
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auto opcode = mem[pc];
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auto op1 = mem[pc+1], op2 = mem[pc+2];
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bool useX = ABX_OPS!T.canFind(opcode);
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assert(useX || ABY_OPS!T.canFind(opcode));
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auto idx = useX ? getX(cpu) : getY(cpu);
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auto base = address(op1, op2);
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auto guess = pageWrapAdd(base, idx);
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auto addr = pageCrossAdd(base, idx);
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cycles = 3; // + accesses_px + accesses_end
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return [Bus(Action.READ, pc),
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Bus(Action.READ, pc+1),
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Bus(Action.READ, pc+2)] ~
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accesses_px(cpu, opcode, 3, guess, addr, cycles) ~
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accesses_end(cpu, opcode, 3, addr, cycles);
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}
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/// Bus access pattern for indirect zeropage,x mode opcodes.
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auto accesses_izx(T)(T cpu, ref TestMemory mem, out int cycles)
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if (isCpu!T)
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{
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auto pc = getPC(cpu);
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auto opcode = mem[pc], op1 = mem[pc+1];
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assert(IZX_OPS!T.canFind(opcode));
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auto idx = getX(cpu);
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auto ial = pageWrapAdd(op1, idx);
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auto iah = pageWrapAdd(ial, 1);
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auto addr = address(mem[ial], mem[iah]);
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cycles = 5; // + accesses_end
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return [Bus(Action.READ, pc),
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Bus(Action.READ, pc+1)] ~
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If!(isStrict!T)(
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If!(isNMOS!T)(
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[Bus(Action.READ, op1)]) ~
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If!(isCMOS!T)(
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[Bus(Action.READ, pc+2)])) ~ // XXX
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[Bus(Action.READ, ial),
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Bus(Action.READ, iah)] ~
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accesses_end(cpu, opcode, 2, addr, cycles);
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/*
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* According to "Understanding the Apple IIe", the extra read on
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* the 65C02 (marked XXX above) is the address of the last operand
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* byte (pc + 1).
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*/
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}
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/// Bus access pattern for indirect zeropage,y mode opcodes.
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auto accesses_izy(T)(T cpu, ref TestMemory mem, out int cycles)
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if (isCpu!T)
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{
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auto pc = getPC(cpu);
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auto opcode = mem[pc], op1 = mem[pc+1];
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assert(IZY_OPS!T.canFind(opcode));
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auto idx = getY(cpu);
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auto ial = op1;
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auto iah = pageWrapAdd(ial, 1);
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auto base = address(mem[ial], mem[iah]);
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auto guess = pageWrapAdd(base, idx);
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auto addr = pageCrossAdd(base, idx);
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cycles = 4; // + accesses_px + accesses_end
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return [Bus(Action.READ, pc),
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Bus(Action.READ, pc+1),
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Bus(Action.READ, ial),
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Bus(Action.READ, iah)] ~
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accesses_px(cpu, opcode, 2, guess, addr, cycles) ~
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accesses_end(cpu, opcode, 2, addr, cycles);
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}
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/// Bus access pattern for indirect zeropage mode opcodes.
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auto accesses_zpi(T)(T cpu, ref TestMemory mem, out int cycles)
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if (isCpu!T && isCMOS!T)
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{
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auto pc = getPC(cpu);
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auto opcode = mem[pc], op1 = mem[pc+1];
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assert(ZPI_OPS!T.canFind(opcode));
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auto ial = op1;
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auto iah = pageWrapAdd(ial, 1);
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auto addr = address(mem[ial], mem[iah]);
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cycles = 4; // + accesses_end
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return [Bus(Action.READ, pc),
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Bus(Action.READ, pc+1),
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Bus(Action.READ, ial),
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Bus(Action.READ, iah)] ~
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accesses_end(cpu, opcode, 2, addr, cycles);
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}
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/// Bus access pattern for NMOS HLT opcodes.
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auto accesses_hlt(T)(T cpu, ref TestMemory mem, out int cycles)
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if (isCpu!T && isNMOS!T)
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{
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auto pc = getPC(cpu);
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auto opcode = mem[pc];
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assert(HLT_OPS!T.canFind(opcode));
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return [Bus(Action.READ, pc)];
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}
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/// Bus access pattern for 1-cycle NOPs.
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auto accesses_nop1(T)(T cpu, ref TestMemory mem, out int cycles)
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if (isCpu!T && isCMOS!T)
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{
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auto pc = getPC(cpu);
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auto opcode = mem[pc];
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assert(NOP1_OPS!T.canFind(opcode));
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cycles = 1;
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return [Bus(Action.READ, pc)];
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}
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auto accesses_px(T)(T cpu, ubyte opcode, int opLen, ushort guess, ushort right,
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ref int cycles)
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if (isCpu!T)
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{
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auto pc = getPC(cpu);
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bool noShortcut = WRITE_OPS!T.canFind(opcode) ||
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(isNMOS!T ? (RMW_OPS!T.canFind(opcode))
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: (opcode == 0xDE || opcode == 0xFE));
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if (guess != right)
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{
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cycles += 1;
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return If!(isStrict!T)(
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If!(isNMOS!T)([Bus(Action.READ, guess)]) ~
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If!(isCMOS!T)([Bus(Action.READ, pc + opLen)])); // XXX
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}
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else if (noShortcut)
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{
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cycles += 1;
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return If!(isStrict!T)([Bus(Action.READ, guess)]);
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}
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else
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{
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return cast(Bus[])[];
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}
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/*
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* According to "Understanding the Apple IIe", the extra read on
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* the 65C02 (marked XXX above) is the address of the last operand
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* byte (pc + opLen - 1) for abx/aby, or the address of the high
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* byte of the indirect address (op1 + 1) for izy.
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*/
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}
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auto accesses_end(T)(T cpu, ubyte opcode, int opLen, ushort addr,
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ref int cycles)
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if (isCpu!T)
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{
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auto pc = getPC(cpu);
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bool rmw = RMW_OPS!T.canFind(opcode);
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bool write = !rmw && WRITE_OPS!T.canFind(opcode);
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bool read = !rmw && !write;
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bool decimal = isCMOS!T && isStrict!T && getFlag(cpu, Flag.D) &&
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BCD_OPS!T.canFind(opcode);
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cycles += (rmw ? 3 : (write ? 1 : (1 + decimal)));
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return If!read(
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[Bus(Action.READ, addr)] ~
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If!decimal(
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[Bus(Action.READ, pc + opLen)])) ~
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If!write(
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[Bus(Action.WRITE, addr)]) ~
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If!rmw(
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[Bus(Action.READ, addr)] ~
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If!(isStrict!T)(
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If!(isNMOS!T)(
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[Bus(Action.WRITE, addr)]) ~
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If!(isCMOS!T)(
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[Bus(Action.READ, addr)])) ~
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[Bus(Action.WRITE, addr)]);
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}
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/// Bus access pattern for RTS.
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auto accesses_op_RTS(T)(T cpu, ref TestMemory mem, out int cycles)
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if (isCpu!T)
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{
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auto pc = getPC(cpu);
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auto opcode = mem[pc];
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assert(opcode == 0x60);
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auto sp = getSP(cpu);
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auto sp1 = pageWrapAdd(sp, 1);
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auto sp2 = pageWrapAdd(sp, 2);
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auto ret = address(mem[sp1], mem[sp2]);
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cycles = 6;
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return [Bus(Action.READ, pc)] ~
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If!(isStrict!T)(
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[Bus(Action.READ, pc+1),
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Bus(Action.READ, sp)]) ~
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[Bus(Action.READ, sp1),
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Bus(Action.READ, sp2)] ~
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If!(isStrict!T)(
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[Bus(Action.READ, ret)]);
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}
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/// Bus access pattern for RTI.
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auto accesses_op_RTI(T)(T cpu, ref TestMemory mem, out int cycles)
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if (isCpu!T)
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{
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auto pc = getPC(cpu);
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auto opcode = mem[pc];
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assert(opcode == 0x40);
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auto sp = getSP(cpu);
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auto sp1 = pageWrapAdd(sp, 1);
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auto sp2 = pageWrapAdd(sp, 2);
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auto sp3 = pageWrapAdd(sp, 3);
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cycles = 6;
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return [Bus(Action.READ, pc)] ~
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If!(isStrict!T)(
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[Bus(Action.READ, pc+1),
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Bus(Action.READ, sp)]) ~
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[Bus(Action.READ, sp1),
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Bus(Action.READ, sp2),
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Bus(Action.READ, sp3)];
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}
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/// Bus access pattern for BRK.
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auto accesses_op_BRK(T)(T cpu, ref TestMemory mem, out int cycles)
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if (isCpu!T)
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{
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auto pc = getPC(cpu);
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auto opcode = mem[pc];
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assert(opcode == 0x00);
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auto sp = getSP(cpu);
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auto sp1 = pageWrapAdd(sp, -1);
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auto sp2 = pageWrapAdd(sp, -2);
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cycles = 7;
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return [Bus(Action.READ, pc)] ~
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If!(isStrict!T)(
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[Bus(Action.READ, pc+1)]) ~
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[Bus(Action.WRITE, sp),
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Bus(Action.WRITE, sp1),
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Bus(Action.WRITE, sp2),
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Bus(Action.READ, 0xFFFE),
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Bus(Action.READ, 0xFFFF)];
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}
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/// Bus access pattern for JSR
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auto accesses_op_JSR(T)(T cpu, ref TestMemory mem, out int cycles)
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if (isCpu!T)
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{
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auto pc = getPC(cpu);
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auto opcode = mem[pc];
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assert(opcode == 0x20);
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auto sp = getSP(cpu);
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auto sp1 = pageWrapAdd(sp, -1);
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cycles = 6;
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return [Bus(Action.READ, pc),
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Bus(Action.READ, pc+1)] ~
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If!(isStrict!T)(
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[Bus(Action.READ, sp)]) ~
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[Bus(Action.WRITE, sp),
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Bus(Action.WRITE, sp1),
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Bus(Action.READ, pc+2)];
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}
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/// Bus access pattern for JMP absolute
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auto accesses_op_JMP_abs(T)(T cpu, ref TestMemory mem, out int cycles)
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if (isCpu!T)
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{
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auto pc = getPC(cpu);
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auto opcode = mem[pc];
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assert(opcode == 0x4C);
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cycles = 3;
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return [Bus(Action.READ, pc),
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Bus(Action.READ, pc+1),
|
||||
Bus(Action.READ, pc+2)];
|
||||
}
|
||||
|
||||
|
||||
/// Bus access pattern for JMP indirect
|
||||
auto accesses_op_JMP_ind(T)(T cpu, ref TestMemory mem, out int cycles)
|
||||
if (isCpu!T)
|
||||
{
|
||||
auto pc = getPC(cpu);
|
||||
auto opcode = mem[pc], op1 = mem[pc+1], op2 = mem[pc+2];
|
||||
assert(opcode == 0x6C);
|
||||
|
||||
auto ial = address(op1, op2);
|
||||
auto iah = (isNMOS!T ? pageWrapAdd(ial, 1)
|
||||
: pageCrossAdd(ial, 1));
|
||||
|
||||
cycles = 5 + isCMOS!T;
|
||||
return [Bus(Action.READ, pc),
|
||||
Bus(Action.READ, pc+1),
|
||||
Bus(Action.READ, pc+2)] ~
|
||||
If!(isStrict!T)(If!(isCMOS!T)(
|
||||
[Bus(Action.READ, pc+3)])) ~ // XXX
|
||||
[Bus(Action.READ, ial),
|
||||
Bus(Action.READ, iah)];
|
||||
|
||||
/*
|
||||
* According to "Understanding the Apple IIe", the extra read on
|
||||
* the 65C02 (marked XXX above) is the address of the last operand
|
||||
* byte (pc + 2).
|
||||
*/
|
||||
}
|
||||
|
||||
|
||||
/// Bus access pattern for JMP indirect,x
|
||||
auto accesses_op_JMP_inx(T)(T cpu, ref TestMemory mem, out int cycles)
|
||||
if (isCpu!T && isCMOS!T)
|
||||
{
|
||||
auto pc = getPC(cpu);
|
||||
auto opcode = mem[pc];
|
||||
assert(opcode == 0x7C);
|
||||
|
||||
auto idx = getX(cpu);
|
||||
auto base = address(mem[pc+1], mem[pc+2]);
|
||||
auto ial = pageCrossAdd(base, idx);
|
||||
auto iah = pageCrossAdd(ial, 1);
|
||||
|
||||
cycles = 6;
|
||||
return [Bus(Action.READ, pc),
|
||||
Bus(Action.READ, pc+1),
|
||||
Bus(Action.READ, pc+2)] ~
|
||||
If!(isStrict!T)(
|
||||
[Bus(Action.READ, pc+3)]) ~ // XXX
|
||||
[Bus(Action.READ, ial),
|
||||
Bus(Action.READ, iah)];
|
||||
|
||||
/*
|
||||
* According to "Understanding the Apple IIe", the extra read on
|
||||
* the 65C02 (marked XXX above) is the address of the last operand
|
||||
* byte (pc + 2).
|
||||
*/
|
||||
}
|
||||
|
||||
|
||||
/// Bus access pattern for CMOS opcode 5C
|
||||
auto accesses_op_5C(T)(T cpu, ref TestMemory mem, out int cycles)
|
||||
if (isCpu!T && isCMOS!T)
|
||||
{
|
||||
auto pc = getPC(cpu);
|
||||
auto opcode = mem[pc];
|
||||
assert(opcode == 0x5C);
|
||||
|
||||
auto weird = address(mem[pc+1], 0xFF);
|
||||
|
||||
cycles = 8;
|
||||
return [Bus(Action.READ, pc),
|
||||
Bus(Action.READ, pc+1)] ~
|
||||
If!(isStrict!T)(
|
||||
[Bus(Action.READ, pc+2),
|
||||
Bus(Action.READ, weird),
|
||||
Bus(Action.READ, 0xFFFF),
|
||||
Bus(Action.READ, 0xFFFF),
|
||||
Bus(Action.READ, 0xFFFF),
|
||||
Bus(Action.READ, 0xFFFF)]);
|
||||
}
|
||||
|
||||
|
||||
enum Action : ushort { NONE, READ, WRITE }
|
||||
|
||||
struct Bus
|
||||
{
|
||||
Action action;
|
||||
ushort addr;
|
||||
|
||||
this(Action action, int addr)
|
||||
{
|
||||
this.action = action; this.addr = cast(ushort)addr;
|
||||
}
|
||||
|
||||
string toString() const
|
||||
{
|
||||
return format("Bus(%s, %0.4X)", to!string(action), addr);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
*
|
||||
*/
|
||||
const(Bus[]) recordBus(T)(T cpu, int actions = 8)
|
||||
if (isCpu!T)
|
||||
{
|
||||
auto record = new Bus[actions];
|
||||
int c;
|
||||
|
||||
enforce(cpu.memoryRead !is null && cpu.memoryWrite !is null);
|
||||
auto wrappedRead = cpu.memoryRead;
|
||||
auto wrappedWrite = cpu.memoryWrite;
|
||||
|
||||
ubyte read(ushort addr)
|
||||
{
|
||||
if (c == actions)
|
||||
throw new TestException(
|
||||
format("cannot record more than %d actions", actions));
|
||||
record[c++] = Bus(Action.READ, addr);
|
||||
return wrappedRead(addr);
|
||||
}
|
||||
|
||||
void write(ushort addr, ubyte val)
|
||||
{
|
||||
if (c == actions)
|
||||
throw new TestException(
|
||||
format("cannot record more than %d actions", actions));
|
||||
record[c++] = Bus(Action.WRITE, addr);
|
||||
wrappedWrite(addr, val);
|
||||
}
|
||||
|
||||
cpu.memoryRead = &read;
|
||||
cpu.memoryWrite = &write;
|
||||
|
||||
return record;
|
||||
}
|
||||
|
||||
auto recordCycles(T)(T cpu)
|
||||
if (isCpu!T)
|
||||
{
|
||||
auto cycles = new int;
|
||||
auto wrappedTick = cpu.tick;
|
||||
|
||||
static if (isCumulative!T)
|
||||
{
|
||||
void tick(int cyc)
|
||||
{
|
||||
(*cycles) += cyc;
|
||||
wrappedTick(cyc);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
void tick()
|
||||
{
|
||||
(*cycles)++;
|
||||
wrappedTick();
|
||||
}
|
||||
}
|
||||
cpu.tick = &tick;
|
||||
|
||||
return constRef(cycles);
|
||||
}
|
||||
|
||||
|
||||
string getExpected(T)()
|
||||
{
|
||||
string[] tmp = new string[256];
|
||||
|
||||
void add_op(const(ubyte[]) list, string fname)
|
||||
{
|
||||
foreach(op; list)
|
||||
{
|
||||
tmp[op] = " case 0x" ~ to!string(op, 16) ~ ": " ~
|
||||
"expected = &" ~ fname ~ "!T; break;";
|
||||
}
|
||||
}
|
||||
|
||||
add_op(REG_OPS!T, "accesses_reg");
|
||||
add_op(PUSH_OPS!T, "accesses_push");
|
||||
add_op(PULL_OPS!T, "accesses_pull");
|
||||
add_op(BRANCH_OPS!T, "accesses_rel");
|
||||
add_op(IMM_OPS!T, "accesses_imm");
|
||||
add_op(ZPG_OPS!T, "accesses_zpg");
|
||||
add_op(ZPX_OPS!T, "accesses_zpxy");
|
||||
add_op(ZPY_OPS!T, "accesses_zpxy");
|
||||
add_op(ABS_OPS!T, "accesses_abs");
|
||||
add_op(ABX_OPS!T, "accesses_abxy");
|
||||
add_op(ABY_OPS!T, "accesses_abxy");
|
||||
add_op(IZX_OPS!T, "accesses_izx");
|
||||
add_op(IZY_OPS!T, "accesses_izy");
|
||||
add_op([0x00], "accesses_op_BRK");
|
||||
add_op([0x20], "accesses_op_JSR");
|
||||
add_op([0x40], "accesses_op_RTI");
|
||||
add_op([0x4C], "accesses_op_JMP_abs");
|
||||
add_op([0x60], "accesses_op_RTS");
|
||||
add_op([0x6C], "accesses_op_JMP_ind");
|
||||
static if (isNMOS!T)
|
||||
add_op(HLT_OPS!T, "accesses_hlt");
|
||||
else
|
||||
{
|
||||
add_op(ZPI_OPS!T, "accesses_zpi");
|
||||
add_op(NOP1_OPS!T, "accesses_nop1");
|
||||
add_op([0x7C], "accesses_op_JMP_inx");
|
||||
add_op([0x5C], "accesses_op_5C");
|
||||
}
|
||||
|
||||
return "final switch (opcode)\n{\n" ~ join(tmp, "\n") ~ "\n}";
|
||||
}
|
||||
|
||||
import std.stdio;
|
||||
|
||||
void test_opcode_timing(T)(ubyte opcode)
|
||||
{
|
||||
addrsetup_t!T[] function(ubyte) setups1;
|
||||
datasetup_t!T[] function(ubyte) setups2;
|
||||
mixin(getMemSetup!T());
|
||||
|
||||
timesetup_t!T expected;
|
||||
mixin(getExpected!T());
|
||||
|
||||
auto funcs1 = setups1(opcode);
|
||||
string name1;
|
||||
foreach(func1; funcs1)
|
||||
{
|
||||
ushort addr;
|
||||
int cycles;
|
||||
auto cpu = new T();
|
||||
auto block1 = func1(cpu, addr, name1);
|
||||
auto mem = TestMemory(block1);
|
||||
connectCpu(cpu, mem);
|
||||
auto exp = expected(cpu, mem, cycles);
|
||||
exp = exp ~ new Bus[8 - exp.length];
|
||||
auto actual = recordBus(cpu);
|
||||
auto actualCycles = recordCycles(cpu);
|
||||
// XXX debug
|
||||
write(format("Testing %s (%0.2X) -- ", name1, opcode));
|
||||
try
|
||||
{
|
||||
runOneOpcode(cpu);
|
||||
}
|
||||
catch (TestException e) // possibly not related to timing
|
||||
{
|
||||
// XXX wrap
|
||||
throw e;
|
||||
}
|
||||
if (actual != exp)
|
||||
{
|
||||
// XXX make error message, throw
|
||||
}
|
||||
if (actualCycles != cycles)
|
||||
{
|
||||
// XXX make error message, throw
|
||||
}
|
||||
if (actual == exp && actualCycles == cycles)
|
||||
writeln("OK");
|
||||
else
|
||||
{
|
||||
writeln();
|
||||
writeln(actualCycles, " ", cycles);
|
||||
writeln(actual);
|
||||
writeln(exp);
|
||||
throw new TestException("timing");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
unittest
|
||||
{
|
||||
import std.stdio;
|
||||
|
||||
alias CPU!("65C02", false, false) T1;
|
||||
for (int op = 0x00; op < 0x100; op++)
|
||||
test_opcode_timing!T1(cast(ubyte)op);
|
||||
|
||||
alias CPU!("65C02", true, false) T2;
|
||||
for (int op = 0x00; op < 0x100; op++)
|
||||
test_opcode_timing!T2(cast(ubyte)op);
|
||||
|
||||
alias CPU!("6502", false, false) T3;
|
||||
for (int op = 0x00; op < 0x100; op++)
|
||||
test_opcode_timing!T3(cast(ubyte)op);
|
||||
|
||||
alias CPU!("6502", true, false) T4;
|
||||
for (int op = 0x00; op < 0x100; op++)
|
||||
test_opcode_timing!T4(cast(ubyte)op);
|
||||
|
||||
alias CPU!("65C02", false, true) T1;
|
||||
for (int op = 0x00; op < 0x100; op++)
|
||||
test_opcode_timing!T1(cast(ubyte)op);
|
||||
|
||||
alias CPU!("65C02", true, true) T2;
|
||||
for (int op = 0x00; op < 0x100; op++)
|
||||
test_opcode_timing!T2(cast(ubyte)op);
|
||||
|
||||
alias CPU!("6502", false, true) T3;
|
||||
for (int op = 0x00; op < 0x100; op++)
|
||||
test_opcode_timing!T3(cast(ubyte)op);
|
||||
|
||||
alias CPU!("6502", true, true) T4;
|
||||
for (int op = 0x00; op < 0x100; op++)
|
||||
test_opcode_timing!T4(cast(ubyte)op);
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user