memory detection all working and sets bank defaults
This commit is contained in:
Dagen Brock
parent
bbfc1a7a76
commit
c7c86025ab
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@ -860,3 +860,4 @@ BINBCDVARDUMP
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jsr RDKEY
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rts
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157
src/mmt.s
157
src/mmt.s
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@ -20,6 +20,12 @@ Init
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lda $C034 ; save border color
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sta BorderColor
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jsr DetectRam
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lda BankExpansionLowest
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sta StartBank
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lda BankExpansionHighest
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sta EndBank
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lda #MainMenuDefs
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ldx #>MainMenuDefs
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jsr Menu_InitMenu
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@ -28,6 +34,7 @@ Init
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Main
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:menuLoop jsr DrawMenuBackground
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jsr DrawRomMessage
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jsr DrawRamMessages
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:menuDrawOptionsLoop jsr MenuUpdateWordSize ;always update this before draw in case of change
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lda #MainMenuDefs
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ldy #>MainMenuDefs
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@ -49,8 +56,12 @@ Main
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beq :nextItem
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:unknownKey bra :menuNoDrawLoop
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:prevItem jsr Menu_PrevItem
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jsr Menu_UndrawSelectedAll ;hack for blinky cursor
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stz _ticker
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bra :menuNoDrawLoop
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:nextItem jsr Menu_NextItem
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jsr Menu_UndrawSelectedAll ;hack for blinky cursor
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stz _ticker
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bra :menuNoDrawLoop
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* Main loop end ^^^
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@ -132,11 +143,46 @@ DrawMenuBackground jsr HOME
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DrawRomMessage
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PRINTXY #55;#05;Mesg_Rom
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PRINTXY #55;#06;Mesg_Rom
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lda GSROM
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jsr PRBYTE
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rts
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DrawRamMessages
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lda GSROM
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cmp #3
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bne :rom0or1
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:rom3 PRINTXY #55;#07;Mesg_InternalRam1024
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bra :drawExpansionMessage
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:rom0or1 PRINTXY #55;#07;Mesg_InternalRam256
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:drawExpansionMessage PRINTXY #55;#08;Mesg_ExpansionRam
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lda BankExpansionRam ;number of banks
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clc
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xce
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rep #$30
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and #$00FF ;clear artifacts? can't remember state of B
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asl ;*2
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asl ;*4
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asl ;*8
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asl ;*16
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asl ;*32
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asl ;*64
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sta _stash
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sep #$30
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ldx _stash
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ldy _stash+1
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jsr BINtoBCD
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phx
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tya
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jsr PRBYTE
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pla
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jsr PRBYTE
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lda #"K"
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jsr COUT
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rts
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LOG MAC
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lda #]1
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ldy #>]1
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@ -238,7 +284,7 @@ BeginTestPass PRINTXY #38;#05;Mesg_TestPass
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clc ; WRITE START
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xce
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rep $10 ; long x, short a
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lda TestStartBank
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lda StartBank
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sta CurBank
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ldy #0 ; update interval counter
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:bankloop lda CurBank
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@ -278,7 +324,7 @@ BeginTestPass PRINTXY #38;#05;Mesg_TestPass
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clc ; READ START
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xce
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rep $10 ; long x, short a
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lda TestStartBank
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lda StartBank
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sta CurBank
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ldy #0 ; update interval counter
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:bankrloop lda CurBank
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@ -328,6 +374,11 @@ BeginTestPass PRINTXY #38;#05;Mesg_TestPass
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_testIteration ds 8
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_errorCounter ds 8
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UpdateScanInterval equ #$1000
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Mesg_InternalRam256 asc "Built-In RAM 256K",00
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Mesg_InternalRam1024 asc "Built-In RAM 1024K",00
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Mesg_ExpansionRam asc "Expansion RAM ",00
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Mesg_Rom asc "Apple IIgs ROM ",00
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Mesg_UserManual asc "USE ARROW KEYS TO MOVE - USE ENTER TO SELECT/EDIT",00
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Mesg_Starting asc $8D,"Starting Test",$8D,"Press P to pause, ESC to stop.",$8D,$8D,00
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@ -623,7 +674,7 @@ MenuStr_JSR da BeginTest ; MUST PRECEDE MENU S
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MenuStr_BeginTest asc " BEGIN TEST "
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MenuStr_BeginTestL equ #*-MenuStr_BeginTest
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MenuStr_BeginTestE db 00
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TestStartBank db #$06
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StartBank db #$06
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EndBank db #$1F
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CurBank db #0
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StartAddr dw #$0000
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@ -653,7 +704,7 @@ MainMenuDefs
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:StartBank hex 19,05 ; x,y
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db Menu_TypeHex ; 1=hex input
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db 01 ; memory size (bytes)
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da TestStartBank ; variable storage
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da StartBank ; variable storage
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:EndBank hex 22,05 ; x,y
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db Menu_TypeHex ; 1=hex input
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db 01 ; memory size (bytes)
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@ -800,6 +851,7 @@ CheckKey lda KEY
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rts
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WaitKey
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:kloop
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jsr ColorizeMenu
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@ -819,3 +871,98 @@ BorderColor db 0
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_stash ds 255
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ds \
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* Creates a 256 byte map of each bank, "BankRam"
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* The map shows whether it's Built-in RAM, ROM, Expansion RAM, etc.
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DetectRam
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lda #BankRAMFastBuiltIn ;these are universal to all IIgs
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sta BankMap+$00 ;bank 00
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sta BankMap+$01 ;bank 01
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lda #BankRAMSlowBuiltIn ;
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sta BankMap+$e0 ;bank e0
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sta BankMap+$e1 ;bank e1
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lda #BankROMUsed
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sta BankMap+$FE ;bank FE
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sta BankMap+$FF ;bank FF
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lda GSROM
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cmp #3 ;check for ROM3 IIgs
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bne :rom0or1
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:rom3 lda #BankRAMFastBuiltIn
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ldx #$02 ;bank 02
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:builtinram sta BankMap,x ;bank 02
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inx
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cpx #$10 ;stop after bank 0F
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bcc :builtinram
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lda #BankROMUsed ;ROM 3 is 256KB, so 4 banks (2 additional)
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sta BankMap+$FC ;
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sta BankMap+$FD ;
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ldx #$10 ;ROM3 starts scan at bank 10
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bra :detectloop
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:rom0or1 ;no additional mappings
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lda #$FE ;ROM1 end bank FE
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sta :endbankscan+1 ;but change our max scan bank
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ldx #$02 ;ROM0/1 starts scan at bank 02
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:detectloop txa ;we'll store the bank number
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sta :writer+3 ;overwrite bank address
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sta :reader+3
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sta :compare+1
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:writer stal $000000 ;should overwrite first byte
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:reader ldal $000000
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:compare cmp #$00
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bne :notused
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inc BankExpansionRam ;TotalMB++
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lda #BankRAMFastExpansion ;store mapping
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sta BankMap,x
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:continue inx
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cpx #$E0 ;skip banks $E0-$EF
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bcc :endbankscan ; <E0
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cpx #$F0
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bcs :endbankscan ; >= F0 (>EF)
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ldx #$F0 ;skip to bank F0
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bra :detectloop
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:endbankscan cpx #$FC ;ROM3 end bank (default)
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bcc :detectloop ;blt
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;let's find low/high to simplify things
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ldx #$ff
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:lowloop lda BankMap,x
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cmp #BankRAMFastExpansion
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beq :isRam
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dex
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cpx #$ff
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bne :lowloop
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bra :checkhigh
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:isRam stx BankExpansionLowest
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dex
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bra :lowloop
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:checkhigh ldx #$00
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:highloop lda BankMap,x
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cmp #BankRAMFastExpansion
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beq :isRam2
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inx
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bne :highloop
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bra :done
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:isRam2 stx BankExpansionHighest
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inx
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bra :highloop
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:done rts
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:notused lda #BankNoRAM
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sta BankMap,x
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bra :continue
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BankExpansionRam ds 1
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BankExpansionLowest ds 1
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BankExpansionHighest ds 1
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ds \
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BankMap ds 256 ;
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BankROMUsed = 1
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BankROMReserved = 2
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BankRAMSlowBuiltIn = 3
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BankRAMFastBuiltIn = 4
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BankRAMFastExpansion = 5
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BankNoRAM = 0
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