mirror of
https://github.com/byteworksinc/ORCA-C.git
synced 2024-09-27 18:58:34 +00:00
Optimize away some tax/tay instructions used only to set flags.
This commit is contained in:
parent
bf40e861aa
commit
76e4b1f038
1
CGI.pas
1
CGI.pas
@ -44,6 +44,7 @@ const
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isPrivate = 32; {is the label private?}
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isPrivate = 32; {is the label private?}
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constantOpnd = 64; {the absolute operand is a constant}
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constantOpnd = 64; {the absolute operand is a constant}
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localLab = 128; {the operand is a local lab}
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localLab = 128; {the operand is a local lab}
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forFlags = 256; {instruction used for effect on flags only}
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m_adc_abs = $6D; {op code #s for 65816 instructions}
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m_adc_abs = $6D; {op code #s for 65816 instructions}
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m_adc_dir = $65;
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m_adc_dir = $65;
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27
Gen.pas
27
Gen.pas
@ -1071,7 +1071,7 @@ if (op^.optype in [cgByte,cgUByte,cgWord,cgUWord]) and
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if rOpcode = pc_fjp then begin
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if rOpcode = pc_fjp then begin
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if op^.optype in [cgByte,cgWord] then begin
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if op^.optype in [cgByte,cgWord] then begin
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if NeedsCondition(op^.left^.opcode) then
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if NeedsCondition(op^.left^.opcode) then
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GenImplied(m_tax);
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GenImpliedForFlags(m_tax);
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if (num >= 0) and (num < 4) then begin
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if (num >= 0) and (num < 4) then begin
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if op^.opcode = pc_geq then begin
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if op^.opcode = pc_geq then begin
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if num <> 0 then begin
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if num <> 0 then begin
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@ -1139,7 +1139,7 @@ if (op^.optype in [cgByte,cgUByte,cgWord,cgUWord]) and
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else if rOpcode = pc_tjp then begin
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else if rOpcode = pc_tjp then begin
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if op^.optype in [cgByte,cgWord] then begin
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if op^.optype in [cgByte,cgWord] then begin
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if NeedsCondition(op^.left^.opcode) then
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if NeedsCondition(op^.left^.opcode) then
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GenImplied(m_tax);
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GenImpliedForFlags(m_tax);
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if (num >= 0) and (num < 4) then begin
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if (num >= 0) and (num < 4) then begin
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lab2 := GenLabel;
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lab2 := GenLabel;
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if op^.opcode = pc_geq then begin
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if op^.opcode = pc_geq then begin
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@ -1675,7 +1675,7 @@ GenTree(op^.left);
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if op^.q in [wordToLong,wordToUlong] then begin
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if op^.q in [wordToLong,wordToUlong] then begin
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lab1 := GenLabel;
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lab1 := GenLabel;
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GenNative(m_ldx_imm, immediate, 0, nil, 0);
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GenNative(m_ldx_imm, immediate, 0, nil, 0);
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GenImplied(m_tay);
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GenImpliedForFlags(m_tay);
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GenNative(m_bpl, relative, lab1, nil, 0);
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GenNative(m_bpl, relative, lab1, nil, 0);
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GenImplied(m_dex);
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GenImplied(m_dex);
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GenLab(lab1);
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GenLab(lab1);
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@ -1861,7 +1861,7 @@ else if op^.q in [byteToQuad,byteToUQuad] then begin
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else if op^.q in [wordToQuad,wordToUQuad] then begin
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else if op^.q in [wordToQuad,wordToUQuad] then begin
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lab1 := GenLabel;
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lab1 := GenLabel;
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GenNative(m_ldx_imm, immediate, 0, nil, 0);
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GenNative(m_ldx_imm, immediate, 0, nil, 0);
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GenImplied(m_tay);
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GenImpliedForFlags(m_tay);
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GenNative(m_bpl, relative, lab1, nil, 0);
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GenNative(m_bpl, relative, lab1, nil, 0);
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GenImplied(m_dex);
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GenImplied(m_dex);
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GenLab(lab1);
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GenLab(lab1);
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@ -2140,7 +2140,7 @@ if (op^.optype in [cgByte,cgUByte,cgWord,cgUWord]) and
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if num <> 0 then
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if num <> 0 then
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GenNative(m_cmp_imm, immediate, num, nil, 0)
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GenNative(m_cmp_imm, immediate, num, nil, 0)
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else if NeedsCondition(leftOp) then
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else if NeedsCondition(leftOp) then
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GenImplied(m_tay);
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GenImpliedForFlags(m_tay);
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if opcode = pc_fjp then
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if opcode = pc_fjp then
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GenNative(beq, relative, lab1, nil, 0)
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GenNative(beq, relative, lab1, nil, 0)
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else
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else
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@ -5476,7 +5476,7 @@ procedure GenTree {op: icptr};
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pc_not: begin
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pc_not: begin
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lab1 := GenLabel;
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lab1 := GenLabel;
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GenImplied(m_tax);
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GenImpliedForFlags(m_tax);
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GenNative(m_beq, relative, lab1, nil, 0);
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GenNative(m_beq, relative, lab1, nil, 0);
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GenNative(m_lda_imm, immediate, 1, nil, 0);
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GenNative(m_lda_imm, immediate, 1, nil, 0);
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GenLab(lab1);
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GenLab(lab1);
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@ -5811,14 +5811,15 @@ procedure GenTree {op: icptr};
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power := power + 1;
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power := power + 1;
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val := val >> 1;
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val := val >> 1;
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end; {while}
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end; {while}
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if power <> 1 then
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if power <> 1 then begin
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GenNative(m_ldy_imm, immediate, power, nil, 0);
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GenNative(m_ldy_imm, immediate, power, nil, 0);
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lab1 := GenLabel;
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lab1 := GenLabel;
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GenLab(lab1);
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end; {if}
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lab2 := GenLabel;
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lab2 := GenLabel;
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lab3 := GenLabel;
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lab3 := GenLabel;
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GenLab(lab1);
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GenImpliedForFlags(m_tax);
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GenImplied(m_clc);
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GenImplied(m_clc);
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GenImplied(m_tax);
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GenNative(m_bpl, relative, lab2, nil, 0);
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GenNative(m_bpl, relative, lab2, nil, 0);
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GenImplied(m_ina);
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GenImplied(m_ina);
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GenNative(m_beq, relative, lab3, nil, 0);
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GenNative(m_beq, relative, lab3, nil, 0);
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@ -5991,10 +5992,10 @@ procedure GenTree {op: icptr};
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GenTree(op^.left);
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GenTree(op^.left);
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opcode := op^.left^.opcode;
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opcode := op^.left^.opcode;
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if NeedsCondition(opcode) then
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if NeedsCondition(opcode) then
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GenImplied(m_tax)
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GenImpliedForFlags(m_tax)
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else if opcode = pc_ind then
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else if opcode = pc_ind then
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if op^.left^.optype in [cgByte,cgUByte] then
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if op^.left^.optype in [cgByte,cgUByte] then
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GenImplied(m_tax);
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GenImpliedForFlags(m_tax);
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if op^.opcode = pc_fjp then
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if op^.opcode = pc_fjp then
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GenNative(m_bne, relative, lab1, nil, 0)
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GenNative(m_bne, relative, lab1, nil, 0)
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else {if op^.opcode = pc_tjp then}
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else {if op^.opcode = pc_tjp then}
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@ -7320,7 +7321,7 @@ procedure GenTree {op: icptr};
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lab3 := GenLabel;
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lab3 := GenLabel;
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GenTree(op^.left);
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GenTree(op^.left);
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if NeedsCondition(op^.left^.opcode) then
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if NeedsCondition(op^.left^.opcode) then
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GenImplied(m_tax);
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GenImpliedForFlags(m_tax);
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GenNative(m_beq, relative, lab1, nil, 0);
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GenNative(m_beq, relative, lab1, nil, 0);
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GenNative(m_brl, longrelative, lab2, nil, 0);
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GenNative(m_brl, longrelative, lab2, nil, 0);
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GenLab(lab1);
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GenLab(lab1);
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147
Native.pas
147
Native.pas
@ -86,6 +86,14 @@ procedure GenImplied (p_opcode: integer);
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{ p_code - operation code }
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{ p_code - operation code }
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procedure GenImpliedForFlags (p_opcode: integer);
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{ Generate implied addressing instruction used for flags only. }
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{ }
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{ parameters: }
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{ p_code - operation code (m_tax or m_tay) }
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procedure GenCall (callNum: integer);
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procedure GenCall (callNum: integer);
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{ short form of jsl to library subroutine - reduces code size }
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{ short form of jsl to library subroutine - reduces code size }
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@ -180,11 +188,15 @@ type
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end;
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end;
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var
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var
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{native peephole optimization}
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{register optimization}
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{----------------------------}
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{---------------------}
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aRegister, {current register contents}
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aRegister, {current register contents}
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xRegister,
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xRegister,
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yRegister: registerType;
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yRegister: registerType;
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lastRegOpcode: integer; {opcode of last reg/flag-setting instr.}
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{native peephole optimization}
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{----------------------------}
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nleadOpcodes: set of 0..max_opcode; {instructions that can start an opt.}
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nleadOpcodes: set of 0..max_opcode; {instructions that can start an opt.}
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nstopOpcodes: set of 0..max_opcode; {instructions not involved in opt.}
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nstopOpcodes: set of 0..max_opcode; {instructions not involved in opt.}
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nnextspot: npeepRange; {next empty spot in npeep}
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nnextspot: npeepRange; {next empty spot in npeep}
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@ -765,7 +777,25 @@ procedure CheckRegisters(p_opcode: integer; p_mode: addressingMode;
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{ p_name - named operand }
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{ p_name - named operand }
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{ p_flags - operand modifier flags }
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{ p_flags - operand modifier flags }
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label 1,2;
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label 1,2,3;
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function NZMatchA: boolean;
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{ Are the N and Z flags known to match the value in A? }
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{ }
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{ Note: Assumes long registers }
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begin {NZMatchA}
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NZMatchA := lastRegOpcode in
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[m_adc_abs,m_adc_dir,m_adc_imm,m_adc_s,m_adc_indl,m_adc_indly,
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m_and_abs,m_and_dir,m_and_imm,m_and_s,m_and_indl,m_and_indly,m_asl_a,
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m_dea,m_eor_abs,m_eor_dir,m_eor_imm,m_eor_s,m_eor_indl,m_eor_indly,
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m_ina,m_lda_abs,m_lda_absx,m_lda_dir,m_lda_dirx,m_lda_imm,m_lda_indl,
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m_lda_indly,m_lda_long,m_lda_longx,m_lda_s,m_lsr_a,m_ora_abs,m_ora_dir,
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m_ora_dirX,m_ora_imm,m_ora_long,m_ora_longX,m_ora_s,m_ora_indl,
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m_ora_indly,m_pla,m_ror_a,m_sbc_abs,m_sbc_dir,m_sbc_imm,m_sbc_s,
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m_sbc_indl,m_sbc_indly,m_tax,m_tay,m_tcd,m_tdc,m_txa,m_tya];
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end; {NZMatchA}
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begin {CheckRegisters}
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begin {CheckRegisters}
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case p_opcode of
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case p_opcode of
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@ -784,10 +814,13 @@ case p_opcode of
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m_plx:
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m_plx:
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xRegister.condition := regUnknown;
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xRegister.condition := regUnknown;
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m_bcc,m_bcs,m_beq,m_bmi,m_bne,m_bpl,m_bra,m_brl,m_bvs,m_clc,m_cmp_abs,
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m_bcc,m_bcs,m_beq,m_bmi,m_bne,m_bpl,m_bvs,
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m_cmp_dir,m_cmp_imm,m_cmp_s,m_cmp_indl,m_cmp_indly,m_cpx_imm,m_jml,
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m_pha,m_phb,m_phd,m_php,m_phx,m_phy,m_pei_dir,m_tcs:
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m_pha,m_phb,m_phd,m_phx,m_phy,m_plb,m_rtl,m_rts,m_sec,m_tcs,d_add,d_pin,
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goto 3;
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m_pei_dir,m_cpx_abs,m_cpx_dir,m_cmp_dirx,m_php,m_plp,m_cop,d_wrd: ;
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m_bra,m_brl,m_clc,m_cmp_abs,m_cmp_dir,m_cmp_imm,m_cmp_s,m_cmp_indl,
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m_cmp_indly,m_cpx_imm,m_jml,m_plb,m_rtl,m_rts,m_sec,d_add,d_pin,
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m_cpx_abs,m_cpx_dir,m_cmp_dirx,m_plp,m_cop,d_wrd: ;
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m_pea: begin
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m_pea: begin
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if aRegister.condition = regImmediate then
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if aRegister.condition = regImmediate then
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@ -817,9 +850,20 @@ case p_opcode of
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goto 2;
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goto 2;
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end; {if}
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end; {if}
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end; {if}
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end; {if}
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goto 3;
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end;
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end;
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m_sta_s,m_pld,m_tcd: begin
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m_sta_s: begin
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if aRegister.condition = regLocal then
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aRegister.condition := regUnknown;
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if xRegister.condition = regLocal then
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xRegister.condition := regUnknown;
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if yRegister.condition = regLocal then
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yRegister.condition := regUnknown;
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goto 3;
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end;
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m_pld,m_tcd: begin
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if aRegister.condition = regLocal then
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if aRegister.condition = regLocal then
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aRegister.condition := regUnknown;
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aRegister.condition := regUnknown;
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if xRegister.condition = regLocal then
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if xRegister.condition = regLocal then
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@ -835,6 +879,7 @@ case p_opcode of
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xRegister.condition := regUnknown;
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xRegister.condition := regUnknown;
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if yRegister.condition <> regImmediate then
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if yRegister.condition <> regImmediate then
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yRegister.condition := regUnknown;
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yRegister.condition := regUnknown;
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goto 3;
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end;
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end;
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m_sta_absX,m_stz_absX,m_sta_longX: begin
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m_sta_absX,m_stz_absX,m_sta_longX: begin
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@ -847,10 +892,25 @@ case p_opcode of
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if yRegister.condition = regAbsolute then
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if yRegister.condition = regAbsolute then
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if yRegister.lab = p_name then
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if yRegister.lab = p_name then
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yRegister.condition := regUnknown;
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yRegister.condition := regUnknown;
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goto 3;
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end;
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end;
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m_dec_abs,m_inc_abs,m_sta_abs,m_stx_abs,m_sty_abs,m_sta_long,m_stz_abs,
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m_dec_abs,m_inc_abs,m_tsb_abs: begin
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m_tsb_abs: begin
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if aRegister.condition = regAbsolute then
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if aRegister.lab = p_name then
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if aRegister.value = p_operand then
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aRegister.condition := regUnknown;
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if xRegister.condition = regAbsolute then
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if xRegister.lab = p_name then
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if xRegister.value = p_operand then
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xRegister.condition := regUnknown;
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if yRegister.condition = regAbsolute then
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if yRegister.lab = p_name then
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if yRegister.value = p_operand then
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yRegister.condition := regUnknown;
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end;
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m_sta_abs,m_stx_abs,m_sty_abs,m_sta_long,m_stz_abs: begin
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if aRegister.condition = regAbsolute then
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if aRegister.condition = regAbsolute then
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if aRegister.lab = p_name then
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if aRegister.lab = p_name then
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if aRegister.value = p_operand then
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if aRegister.value = p_operand then
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@ -866,9 +926,22 @@ case p_opcode of
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if yRegister.value = p_operand then
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if yRegister.value = p_operand then
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if p_opcode <> m_sty_abs then
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if p_opcode <> m_sty_abs then
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yRegister.condition := regUnknown;
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yRegister.condition := regUnknown;
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goto 3;
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end;
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end;
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m_dec_dir,m_inc_dir,m_tsb_dir,m_sta_dir,m_stx_dir,m_sty_dir,m_stz_dir: begin
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m_dec_dir,m_inc_dir,m_tsb_dir: begin
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if aRegister.condition = regLocal then
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if aRegister.value = p_operand then
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aRegister.condition := regUnknown;
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if xRegister.condition = regLocal then
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if xRegister.value = p_operand then
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xRegister.condition := regUnknown;
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if yRegister.condition = regLocal then
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if yRegister.value = p_operand then
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yRegister.condition := regUnknown;
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end;
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m_sta_dir,m_stx_dir,m_sty_dir,m_stz_dir: begin
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if aRegister.condition = regLocal then
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if aRegister.condition = regLocal then
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if aRegister.value = p_operand then
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if aRegister.value = p_operand then
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if p_opcode <> m_sta_dir then
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if p_opcode <> m_sta_dir then
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@ -881,9 +954,10 @@ case p_opcode of
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if yRegister.value = p_operand then
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if yRegister.value = p_operand then
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if p_opcode <> m_sty_dir then
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if p_opcode <> m_sty_dir then
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yRegister.condition := regUnknown;
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yRegister.condition := regUnknown;
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goto 3;
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end;
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end;
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m_dec_dirX,m_inc_dirX,m_sta_dirX,m_sty_dirX,m_stz_dirX: begin
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m_dec_dirX,m_inc_dirX: begin
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if aRegister.condition = regLocal then
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if aRegister.condition = regLocal then
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if aRegister.value >= p_operand-1 then
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if aRegister.value >= p_operand-1 then
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aRegister.condition := regUnknown;
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aRegister.condition := regUnknown;
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@ -894,6 +968,19 @@ case p_opcode of
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if yRegister.value >= p_operand-1 then
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if yRegister.value >= p_operand-1 then
|
||||||
yRegister.condition := regUnknown;
|
yRegister.condition := regUnknown;
|
||||||
end;
|
end;
|
||||||
|
|
||||||
|
m_sta_dirX,m_sty_dirX,m_stz_dirX: begin
|
||||||
|
if aRegister.condition = regLocal then
|
||||||
|
if aRegister.value >= p_operand-1 then
|
||||||
|
aRegister.condition := regUnknown;
|
||||||
|
if xRegister.condition = regLocal then
|
||||||
|
if xRegister.value >= p_operand-1 then
|
||||||
|
xRegister.condition := regUnknown;
|
||||||
|
if yRegister.condition = regLocal then
|
||||||
|
if yRegister.value >= p_operand-1 then
|
||||||
|
yRegister.condition := regUnknown;
|
||||||
|
goto 3;
|
||||||
|
end;
|
||||||
|
|
||||||
m_dex:
|
m_dex:
|
||||||
if xRegister.condition = regImmediate then
|
if xRegister.condition = regImmediate then
|
||||||
@ -1230,7 +1317,13 @@ case p_opcode of
|
|||||||
end;
|
end;
|
||||||
|
|
||||||
m_tax: begin
|
m_tax: begin
|
||||||
if aRegister.condition <> regUnknown then
|
if (p_flags & forFlags) <> 0 then begin
|
||||||
|
if longA then
|
||||||
|
if longI then
|
||||||
|
if NZMatchA then
|
||||||
|
goto 1;
|
||||||
|
end {if}
|
||||||
|
else if aRegister.condition <> regUnknown then
|
||||||
if aRegister.condition = xRegister.condition then
|
if aRegister.condition = xRegister.condition then
|
||||||
if aRegister.value = xRegister.value then
|
if aRegister.value = xRegister.value then
|
||||||
if aRegister.flags = xRegister.flags then
|
if aRegister.flags = xRegister.flags then
|
||||||
@ -1242,7 +1335,13 @@ case p_opcode of
|
|||||||
end;
|
end;
|
||||||
|
|
||||||
m_tay: begin
|
m_tay: begin
|
||||||
if aRegister.condition <> regUnknown then
|
if (p_flags & forFlags) <> 0 then begin
|
||||||
|
if longA then
|
||||||
|
if longI then
|
||||||
|
if NZMatchA then
|
||||||
|
goto 1;
|
||||||
|
end {if}
|
||||||
|
else if aRegister.condition <> regUnknown then
|
||||||
if aRegister.condition = yRegister.condition then
|
if aRegister.condition = yRegister.condition then
|
||||||
if aRegister.value = yRegister.value then
|
if aRegister.value = yRegister.value then
|
||||||
if aRegister.flags = yRegister.flags then
|
if aRegister.flags = yRegister.flags then
|
||||||
@ -1301,9 +1400,12 @@ case p_opcode of
|
|||||||
xRegister := yRegister;
|
xRegister := yRegister;
|
||||||
end;
|
end;
|
||||||
end; {case}
|
end; {case}
|
||||||
2:
|
2: {emit the instruction normally}
|
||||||
|
lastRegOpcode := p_opcode;
|
||||||
|
3: {branch here for instructions that}
|
||||||
|
{do not modify A/X/Y or flags }
|
||||||
WriteNative(p_opcode, p_mode, p_operand, p_name, p_flags);
|
WriteNative(p_opcode, p_mode, p_operand, p_name, p_flags);
|
||||||
1:
|
1: {branch here to skip the instruction}
|
||||||
end; {CheckRegisters}
|
end; {CheckRegisters}
|
||||||
|
|
||||||
|
|
||||||
@ -1944,6 +2046,18 @@ GenNative(p_opcode, implied, 0, nil, 0);
|
|||||||
end; {GenImplied}
|
end; {GenImplied}
|
||||||
|
|
||||||
|
|
||||||
|
procedure GenImpliedForFlags {p_opcode: integer};
|
||||||
|
|
||||||
|
{ Generate implied addressing instruction used for flags only. }
|
||||||
|
{ }
|
||||||
|
{ parameters: }
|
||||||
|
{ p_code - operation code (m_tax or m_tay) }
|
||||||
|
|
||||||
|
begin {GenImplied}
|
||||||
|
GenNative(p_opcode, implied, 0, nil, forFlags);
|
||||||
|
end; {GenImplied}
|
||||||
|
|
||||||
|
|
||||||
procedure GenCall {callNum: integer};
|
procedure GenCall {callNum: integer};
|
||||||
|
|
||||||
{ short form of jsl to library subroutine - reduces code size }
|
{ short form of jsl to library subroutine - reduces code size }
|
||||||
@ -2354,6 +2468,7 @@ begin {InitNative}
|
|||||||
aRegister.condition := regUnknown; {set up the peephole optimizer}
|
aRegister.condition := regUnknown; {set up the peephole optimizer}
|
||||||
xRegister.condition := regUnknown;
|
xRegister.condition := regUnknown;
|
||||||
yRegister.condition := regUnknown;
|
yRegister.condition := regUnknown;
|
||||||
|
lastRegOpcode := 0; {BRK}
|
||||||
nnextspot := 1;
|
nnextspot := 1;
|
||||||
nleadOpcodes := [m_asl_a,m_bcs,m_beq,m_bmi,m_bne,m_bpl,m_brl,m_bvs,m_bcc,
|
nleadOpcodes := [m_asl_a,m_bcs,m_beq,m_bmi,m_bne,m_bpl,m_brl,m_bvs,m_bcc,
|
||||||
m_dec_abs,m_lda_abs,m_lda_dir,m_lda_imm,m_ldx_imm,m_sta_abs,m_sta_dir,
|
m_dec_abs,m_lda_abs,m_lda_dir,m_lda_imm,m_ldx_imm,m_sta_abs,m_sta_dir,
|
||||||
|
Loading…
Reference in New Issue
Block a user