From f19d21365a1ad3ce0d6c8238ac11eef226872838 Mon Sep 17 00:00:00 2001 From: Stephen Heumann Date: Tue, 2 Mar 2021 19:19:00 -0600 Subject: [PATCH] Recognize more indirect long instructions in the native code optimizer. These instructions can be generated for indirect accesses to quad values, and the optimization can sometimes make those code sequences more efficient (e.g. avoiding unnecessary reloads of Y). --- CGI.pas | 6 ++++++ Native.pas | 8 +++++--- 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/CGI.pas b/CGI.pas index 0046898..fcca32a 100644 --- a/CGI.pas +++ b/CGI.pas @@ -50,11 +50,13 @@ const m_adc_imm = $69; m_adc_s = $63; m_adc_indl = $67; + m_adc_indly = $77; m_and_abs = $2D; m_and_dir = $25; m_and_imm = $29; m_and_s = $23; m_and_indl = $27; + m_and_indly = $37; m_asl_a = $0A; m_bcc = $90; m_bcs = $B0; @@ -74,6 +76,7 @@ const m_cmp_long = $CF; m_cmp_s = $C3; m_cmp_indl = $C7; + m_cmp_indly = $D7; m_cop = $02; m_cpx_abs = 236; m_cpx_dir = 228; @@ -90,6 +93,7 @@ const m_eor_imm = 73; m_eor_s = 67; m_eor_indl = $47; + m_eor_indly = $57; m_ina = 26; m_inc_abs = 238; m_inc_absX = $FE; @@ -127,6 +131,7 @@ const m_ora_longX = 31; m_ora_s = 3; m_ora_indl = $07; + m_ora_indly = $17; m_pea = 244; m_pei_dir = 212; m_pha = 72; @@ -149,6 +154,7 @@ const m_sbc_imm = 233; m_sbc_s = 227; m_sbc_indl = $E7; + m_sbc_indly = $F7; m_sec = 56; m_sep = 226; m_sta_abs = 141; diff --git a/Native.pas b/Native.pas index 1aef324..627dcf8 100644 --- a/Native.pas +++ b/Native.pas @@ -774,7 +774,9 @@ case p_opcode of m_and_s,m_asl_a,m_dea,m_eor_abs,m_eor_dir,m_eor_imm,m_eor_s,m_lda_absx, m_lda_dirx,m_lda_indl,m_lda_indly,m_lda_longx,m_lda_s,m_lsr_a,m_ora_abs, m_ora_dir,m_ora_dirX,m_ora_imm,m_ora_long,m_ora_longX,m_ora_s,m_pla, - m_sbc_abs,m_sbc_dir,m_sbc_imm,m_sbc_s,m_tdc,m_tsc: + m_sbc_abs,m_sbc_dir,m_sbc_imm,m_sbc_s,m_tdc,m_tsc,m_adc_indl,m_adc_indly, + m_and_indl,m_and_indly,m_ora_indl,m_ora_indly,m_sbc_indl,m_sbc_indly, + m_eor_indl,m_eor_indly: aRegister.condition := regUnknown; m_ldy_absX,m_ldy_dirX,m_ply: @@ -784,8 +786,8 @@ case p_opcode of xRegister.condition := regUnknown; m_bcc,m_bcs,m_beq,m_bmi,m_bne,m_bpl,m_bra,m_brl,m_bvs,m_clc,m_cmp_abs, - m_cmp_dir,m_cmp_imm,m_cmp_s,m_cpx_imm,m_jml,m_pha,m_phb,m_phd, - m_phx,m_phy,m_plb,m_rtl,m_rts,m_sec,m_tcs,d_add,d_pin, + m_cmp_dir,m_cmp_imm,m_cmp_s,m_cmp_indl,m_cmp_indly,m_cpx_imm,m_jml, + m_pha,m_phb,m_phd,m_phx,m_phy,m_plb,m_rtl,m_rts,m_sec,m_tcs,d_add,d_pin, m_pei_dir,m_cpx_abs,m_cpx_dir,m_cmp_dirx,m_php,m_plp,m_cop,d_wrd: ; m_pea: begin