2023-06-11 02:05:11 +00:00
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; Init
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sound_control = $3c ;really at $e1c03c
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sound_data = $3d ;really at $e1c03d
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sound_address = $3e ;really at $e1c03e
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sound_interrupt_ptr = $e1002c
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irq_volume = $e100ca
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osc_interrupt = $e100cc
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mx %10
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access_doc_registers = *
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ldal irq_volume
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sta sound_control
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rts
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access_doc_ram = *
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ldal irq_volume
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ora #%0110_0000
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sta sound_control
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rts
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access_doc_ram_no_inc = *
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ldal irq_volume
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ora #%0100_0000
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sta sound_control
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rts
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mx %00
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APUStartUp
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sei
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phd
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pea $c000
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pld
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jsr copy_instruments_to_doc
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2023-06-11 17:00:52 +00:00
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jsr setup_doc_registers
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2023-06-11 02:05:11 +00:00
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jsr setup_interrupt
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pld
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cli
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rts
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APUShutDown = *
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sei
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phd
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lda #$c000
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tcd
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jsr stop_playing
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lda backup_interrupt_ptr ; restore old interrupt ptr
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stal sound_interrupt_ptr
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lda backup_interrupt_ptr+2
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stal sound_interrupt_ptr+2
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cli
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pld
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clc
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rts
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stop_playing = *
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ldy #7 ; Number of oscillators
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sep #$20
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mx %10
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jsr access_doc_registers
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lda #$a0 ; stop all oscillators in use
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sta sound_address
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lda #%11
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]loop sta sound_data
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inc sound_address
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dey
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bne ]loop
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lda #$a0+interrupt_oscillator ; stop interrupt oscillator
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sta sound_address
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lda #3
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sta sound_data
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rep #$20
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mx %00
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rts
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; Copy in 4 different square wave duty cycles and a triangle wave
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copy_instruments_to_doc
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jsr setup_docram
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lda #$0100
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jsr make_eigth_pulse
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lda #$0200
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jsr make_quarter_pulse
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lda #$0300
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jsr make_half_pulse
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lda #$0400
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jsr make_inv_quarter_pulse
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lda #$0500
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jsr copy_triangle
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rts
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;--------------------------
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setup_docram
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sep #$20
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mx %10
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jsr access_doc_ram
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stz sound_address
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lda #$80
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ldx #256 ;make sure that page 00 has nonzero data for interrupt
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:loop sta sound_data
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dex
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bne :loop
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rep #$20
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mx %00
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rts
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;--------------------------
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make_eigth_pulse
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ldy #32
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jmp make_pulse
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make_quarter_pulse
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ldy #64
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jmp make_pulse
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make_half_pulse
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ldy #128
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jmp make_pulse
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make_inv_quarter_pulse
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ldy #192
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jmp make_pulse
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make_pulse
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sep #$30
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mx %11
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stz sound_address
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xba
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sta sound_address+1
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ldx #0
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:loop1
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lda #$01
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sta sound_data
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inx
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dey
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bne :loop1
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:loop2
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lda #$FF
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sta sound_data
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inx
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bne :loop2
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rep #$30
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mx %00
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rts
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copy_triangle
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sep #$30
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mx %11
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stz sound_address
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xba
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sta sound_address+1
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ldx #0
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:loop
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lda triangle_wave,x
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sta sound_data
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inx
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bne :loop
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rep #$30
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mx %00
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rts
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;--------------------------
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triangle_wave
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hex 80828486888a8c8e90929496989a9c9e
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hex a0a2a4a6a8aaacaeb0b2b4b6b8babcbe
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hex c0c1c3c5c7c9cbcdcfd1d3d5d7d9dbdd
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hex dfe1e3e5e7e9ebedeff1f3f5f7f9fbfd
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hex fffdfbf9f7f5f3f1efedebe9e7e5e3e1
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hex dfdddbd9d7d5d3d1cfcdcbc9c7c5c3c1
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hex c0bebcbab8b6b4b2b0aeacaaa8a6a4a2
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hex a09e9c9a98969492908e8c8a88868482
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hex 807e7c7a78767472706e6c6a68666462
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hex 605e5c5a58565452504e4c4a48464442
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hex 413f3d3b39373533312f2d2b29272523
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hex 211f1d1b19171513110f0d0b09070503
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hex 01030507090b0d0f11131517191b1d1f
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hex 21232527292b2d2f31333537393b3d3f
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hex 41424446484a4c4e50525456585a5c5e
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hex 60626466686a6c6e70727476787a7c7e
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;--------------------------
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setup_doc_registers
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sep #$20
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mx %10
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jsr access_doc_registers
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2023-06-11 17:00:52 +00:00
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ldx #pulse1_sound_settings
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jsr copy_register_config
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ldx #pulse2_sound_settings
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jsr copy_register_config
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ldx #triangle_sound_settings
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jsr copy_register_config
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2023-06-11 02:05:11 +00:00
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rep #$20
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mx %00
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rts
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2023-06-11 17:00:52 +00:00
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copy_register_config
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ldy #0
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:loop lda: 0,x ; Set DOC registers for the NES channels
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sta sound_address
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inx
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lda: 0,x
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sta sound_data
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inx
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iny
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cpy #6 ; 6 pairs to describe this oscillator
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bne :loop
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rts
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2023-06-11 02:05:11 +00:00
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;--------------------------
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setup_interrupt = *
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ldal sound_interrupt_ptr
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sta backup_interrupt_ptr
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ldal sound_interrupt_ptr+2
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sta backup_interrupt_ptr+2
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lda #$5c
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stal sound_interrupt_ptr
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phk
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phk
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pla
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stal sound_interrupt_ptr+2
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lda #interrupt_handler
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stal sound_interrupt_ptr+1
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sep #$20
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mx %10
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jsr access_doc_registers
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ldy #0
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2023-06-11 17:00:52 +00:00
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:loop lda timer_sound_settings,y ; Set DOC registers for the interrupt oscillator
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2023-06-11 02:05:11 +00:00
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sta sound_address
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iny
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lda timer_sound_settings,y
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sta sound_data
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iny
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cpy #7*2
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2023-06-11 17:00:52 +00:00
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bne :loop
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2023-06-11 02:05:11 +00:00
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rep #$20
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mx %00
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rts
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interrupt_oscillator = 31
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reference_freq = 1195 ; interrupt frequence (240Hz)
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timer_sound_settings = * ; set up oscillator 30 for interrupts
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dfb $00+interrupt_oscillator,reference_freq ; frequency low register
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dfb $20+interrupt_oscillator,reference_freq/256 ; frequency high register
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dfb $40+interrupt_oscillator,0 ; volume register, volume = 0
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dfb $80+interrupt_oscillator,0 ; wavetable pointer register, point to 0
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dfb $c0+interrupt_oscillator,0 ; wavetable size register, 256 byte length
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dfb $e1,$3e ; oscillator enable register
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dfb $a0+interrupt_oscillator,$08 ; mode register, set to free run
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pulse1_oscillator = 0
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pulse2_oscillator = 2
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triangle_oscillator = 4
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2023-06-11 17:00:52 +00:00
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default_freq = 5000
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2023-06-11 02:05:11 +00:00
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pulse1_sound_settings = *
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dfb $00+pulse1_oscillator,default_freq ; frequency low register
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dfb $20+pulse1_oscillator,default_freq/256 ; frequency high register
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2023-06-11 17:00:52 +00:00
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dfb $40+pulse1_oscillator,128 ; volume register, volume = 0
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2023-06-11 02:05:11 +00:00
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dfb $80+pulse1_oscillator,3 ; wavetable pointer register, point to $0300 by default (50% duty cycle)
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dfb $c0+pulse1_oscillator,0 ; wavetable size register, 256 byte length
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dfb $a0+pulse1_oscillator,0 ; mode register, set to free run
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pulse2_sound_settings = *
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dfb $00+pulse2_oscillator,default_freq ; frequency low register
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dfb $20+pulse2_oscillator,default_freq/256 ; frequency high register
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2023-06-11 17:00:52 +00:00
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dfb $40+pulse2_oscillator,120 ; volume register, volume = 0
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2023-06-11 02:05:11 +00:00
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dfb $80+pulse2_oscillator,3 ; wavetable pointer register, point to $0300 by default (50% duty cycle)
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dfb $c0+pulse2_oscillator,0 ; wavetable size register, 256 byte length
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dfb $a0+pulse2_oscillator,0 ; mode register, set to free run
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triangle_sound_settings = *
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dfb $00+triangle_oscillator,default_freq ; frequency low register
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dfb $20+triangle_oscillator,default_freq/256 ; frequency high register
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dfb $40+triangle_oscillator,0 ; volume register, volume = 0
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dfb $80+triangle_oscillator,5 ; wavetable pointer register, point to $0500
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dfb $c0+triangle_oscillator,0 ; wavetable size register, 256 byte length
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dfb $a0+triangle_oscillator,0 ; mode register, set to free run
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backup_interrupt_ptr ds 4
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;-----------------------------------------------------------------------------------------
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; interupt handler
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;-----------------------------------------------------------------------------------------
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interrupt_handler = *
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phb
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phd
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phk
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plb
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clc
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xce
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rep #$30
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mx %00
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lda #$c000
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tcd
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2023-06-11 17:00:52 +00:00
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sep #$30
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mx %11
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2023-06-11 02:05:11 +00:00
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jsr access_doc_registers
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ldal osc_interrupt ; which oscillator generated the interrupt?
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and #%00111110
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lsr
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cmp #interrupt_oscillator
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2023-06-11 17:00:52 +00:00
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beq *+5
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brl :not_timer ; Only service timer interrupts
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2023-06-11 02:05:11 +00:00
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; Set the parameters for the first square wave channel
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2023-06-11 17:00:52 +00:00
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lda #$80+pulse1_oscillator
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sta sound_address
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2023-06-11 02:05:11 +00:00
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lda APU_PULSE1_REG1 ; Get the cycle duty bits
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2023-06-11 17:00:52 +00:00
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jsr set_pulse_duty_cycle
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lda #$40+pulse1_oscillator
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sta sound_address
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lda APU_PULSE1_REG1
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jsr set_pulse_volume
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rep #$30
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lda APU_PULSE1_REG3
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jsr get_pulse_freq ; return freq in 16-bic accumulator
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sep #$30
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ldx #$00+pulse1_oscillator
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stx sound_address
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sta sound_data
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ldx #$20+pulse1_oscillator
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stx sound_address
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xba
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sta sound_data
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; Now do the second square wave
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lda #$80+pulse2_oscillator
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sta sound_address
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lda APU_PULSE2_REG1 ; Get the cycle duty bits
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jsr set_pulse_duty_cycle
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lda #$40+pulse2_oscillator
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sta sound_address
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lda APU_PULSE2_REG1
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jsr set_pulse_volume
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rep #$30
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lda APU_PULSE2_REG3
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jsr get_pulse_freq ; return freq in 16-bic accumulator
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sep #$30
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ldx #$00+pulse2_oscillator
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stx sound_address
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sta sound_data
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ldx #$20+pulse2_oscillator
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stx sound_address
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xba
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sta sound_data
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; lda border_color
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; inc
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; and #$03
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; sta border_color
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; jsr setborder
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:not_timer
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sep #$30
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pld
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plb
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clc
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rtl
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set_pulse_duty_cycle
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mx %11
|
2023-06-11 02:05:11 +00:00
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rol
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rol
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rol
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and #$03
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tax
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lda duty_cycle_page,x
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sta sound_data
|
2023-06-11 17:00:52 +00:00
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rts
|
2023-06-11 02:05:11 +00:00
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2023-06-11 17:00:52 +00:00
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set_pulse_volume
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2023-06-11 02:05:11 +00:00
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and #$0F
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asl
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asl
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asl
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asl
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sta sound_data
|
2023-06-11 17:00:52 +00:00
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rts
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2023-06-11 02:05:11 +00:00
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2023-06-11 17:00:52 +00:00
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get_pulse_freq
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mx %00
|
2023-06-11 02:05:11 +00:00
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and #$07FF ; Load the timer value (11-bits); freq = 1.79MHz / (16 * (t - 1)) = 111860Hz / (t-1)
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dec
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lsr ; Divide top and bottom by 2 -- 55930 / ((t - 1)/2)
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sta divisor
|
2023-06-11 17:00:52 +00:00
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lda #55930 ; $DA7A
|
2023-06-11 02:05:11 +00:00
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sta dividend
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lda #0
|
2023-06-11 17:00:52 +00:00
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ldx #16 ; 16 bits of division
|
2023-06-11 02:05:11 +00:00
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asl dividend
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:dl1 rol
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cmp divisor
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bcc :dl2
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sbc divisor
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:dl2 rol dividend
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dex
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bne :dl1
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lda dividend
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sta dividend
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asl
|
2023-06-11 17:00:52 +00:00
|
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; asl
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asl
|
2023-06-11 02:05:11 +00:00
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asl
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adc dividend ; multiple by 5 to get the approx DOC value (0.2Hz per)
|
2023-06-11 17:00:52 +00:00
|
|
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; sta dividend
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rts
|
2023-06-11 02:05:11 +00:00
|
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|
2023-06-11 17:00:52 +00:00
|
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|
turn_off_interrupts
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php
|
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sep #$20
|
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lda #$a0+interrupt_oscillator
|
2023-06-11 02:05:11 +00:00
|
|
|
sta sound_address
|
2023-06-11 17:00:52 +00:00
|
|
|
lda #0
|
2023-06-11 02:05:11 +00:00
|
|
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sta sound_data
|
2023-06-11 17:00:52 +00:00
|
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plp
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rts
|
2023-06-11 02:05:11 +00:00
|
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|
duty_cycle_page dfb $01,$02,$03,$04 ; Page of DOC RAM that holds the different duty cycle wavforms
|
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|
border_color dw 0
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dividend dw 0
|
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divisor dw 0
|
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; 8-bit mode
|
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; A = register number
|
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|
; X = register value
|
|
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|
mx %00
|
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|
SetDOCReg
|
|
|
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|
stal $E0C03E
|
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|
txa
|
|
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|
stal $E0C03D
|
|
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|
|
rts
|
|
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|
|
_SetDOCReg mac
|
|
|
|
|
lda ]1 ; Select the oscillator enable registers
|
|
|
|
|
ldx ]2
|
|
|
|
|
jsr SetDOCReg
|
|
|
|
|
<<<
|
|
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|
|
|
|
|
|
; Pulse Channel 1
|
|
|
|
|
APU_PULSE1
|
|
|
|
|
APU_PULSE1_REG1 ds 1 ; DDLC NNNN - Duty, loop envelope/disable length counter, constant volume, envelope period/volume
|
|
|
|
|
APU_PULSE1_REG2 ds 1 ; EPPP NSSS - Sweep unit: enabled, period, negative, shift count
|
|
|
|
|
APU_PULSE1_REG3 ds 1 ; LLLL LLLL - Timer Low
|
|
|
|
|
APU_PULSE1_REG4 ds 1 ; llll lHHH - Length counter load, timer high (also resets duty and starts envelope)
|
|
|
|
|
|
|
|
|
|
APU_PULSE2
|
|
|
|
|
APU_PULSE2_REG1 ds 1 ; DDLC NNNN - Duty, loop envelope/disable length counter, constant volume, envelope period/volume
|
|
|
|
|
APU_PULSE2_REG2 ds 1 ; EPPP NSSS - Sweep unit: enabled, period, negative, shift count
|
|
|
|
|
APU_PULSE2_REG3 ds 1 ; LLLL LLLL - Timer Low
|
|
|
|
|
APU_PULSE2_REG4 ds 1 ; llll lHHH - Length counter load, timer high (also resets duty and starts envelope)
|
|
|
|
|
|
|
|
|
|
APU_TRIANGLE
|
|
|
|
|
APU_TRIANGLE_REG1 ds 1 ; DDLC NNNN - Duty, loop envelope/disable length counter, constant volume, envelope period/volume
|
|
|
|
|
APU_TRIANGLE_REG2 ds 1 ; EPPP NSSS - Sweep unit: enabled, period, negative, shift count
|
|
|
|
|
APU_TRIANGLE_REG3 ds 1 ; LLLL LLLL - Timer Low
|
|
|
|
|
APU_TRIANGLE_REG4 ds 1 ; llll lHHH - Length counter load, timer high (also resets duty and starts envelope)
|
|
|
|
|
|
|
|
|
|
APU_STATUS ds 1
|
|
|
|
|
|
|
|
|
|
mx %11
|
|
|
|
|
APU_PULSE1_REG1_WRITE ENT
|
|
|
|
|
stal APU_PULSE1_REG1
|
|
|
|
|
rtl
|
|
|
|
|
|
|
|
|
|
APU_PULSE1_REG2_WRITE ENT
|
|
|
|
|
stal APU_PULSE1_REG2
|
|
|
|
|
rtl
|
|
|
|
|
|
|
|
|
|
APU_PULSE1_REG3_WRITE ENT
|
|
|
|
|
stal APU_PULSE1_REG3
|
|
|
|
|
rtl
|
|
|
|
|
|
|
|
|
|
APU_PULSE1_REG4_WRITE ENT
|
|
|
|
|
stal APU_PULSE1_REG4
|
|
|
|
|
rtl
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
APU_PULSE2_REG1_WRITE ENT
|
|
|
|
|
stal APU_PULSE2_REG1
|
|
|
|
|
rtl
|
|
|
|
|
|
|
|
|
|
APU_PULSE2_REG2_WRITE ENT
|
|
|
|
|
stal APU_PULSE2_REG2
|
|
|
|
|
rtl
|
|
|
|
|
|
|
|
|
|
APU_PULSE2_REG3_WRITE ENT
|
|
|
|
|
stal APU_PULSE2_REG3
|
|
|
|
|
rtl
|
|
|
|
|
|
|
|
|
|
APU_PULSE2_REG4_WRITE ENT
|
|
|
|
|
stal APU_PULSE2_REG4
|
|
|
|
|
rtl
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
APU_TRIANGLE_REG1_WRITE ENT
|
|
|
|
|
stal APU_TRIANGLE_REG1
|
|
|
|
|
rtl
|
|
|
|
|
|
|
|
|
|
APU_TRIANGLE_REG2_WRITE ENT
|
|
|
|
|
stal APU_TRIANGLE_REG2
|
|
|
|
|
rtl
|
|
|
|
|
|
|
|
|
|
APU_TRIANGLE_REG3_WRITE ENT
|
|
|
|
|
stal APU_TRIANGLE_REG3
|
|
|
|
|
rtl
|
|
|
|
|
|
|
|
|
|
APU_TRIANGLE_REG4_WRITE ENT
|
|
|
|
|
stal APU_TRIANGLE_REG4
|
|
|
|
|
rtl
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
APU_STATUS_WRITE ENT
|
|
|
|
|
stal APU_STATUS
|
|
|
|
|
pha
|
|
|
|
|
|
|
|
|
|
; Pulse 1 is OSC 0
|
|
|
|
|
bit #$01
|
|
|
|
|
beq :pulse1_off
|
|
|
|
|
_SetDOCReg #$40+pulse1_oscillator;#128
|
|
|
|
|
bra :pulse1_end
|
|
|
|
|
:pulse1_off
|
|
|
|
|
_SetDOCReg #$40+pulse1_oscillator;#0
|
|
|
|
|
:pulse1_end
|
|
|
|
|
|
|
|
|
|
; Pulse 2 is OSC 2
|
|
|
|
|
bit #$02
|
|
|
|
|
beq :pulse2_off
|
|
|
|
|
_SetDOCReg #$40+pulse2_oscillator;#128
|
|
|
|
|
bra :pulse2_end
|
|
|
|
|
:pulse2_off
|
|
|
|
|
_SetDOCReg #$40+pulse2_oscillator;#0
|
|
|
|
|
:pulse2_end
|
|
|
|
|
|
|
|
|
|
; Triangle is OSC 4
|
2023-06-11 17:00:52 +00:00
|
|
|
; bit #$03
|
|
|
|
|
; beq :triangle_off
|
|
|
|
|
; _SetDOCReg #$40+triangle_oscillator;#128
|
|
|
|
|
; bra :triangle_end
|
|
|
|
|
;:triangle_off
|
|
|
|
|
; _SetDOCReg #$40+triangle_oscillator;#0
|
|
|
|
|
;:triangle_end
|
2023-06-11 02:05:11 +00:00
|
|
|
|
|
|
|
|
pla
|
|
|
|
|
rtl
|
