2022-04-25 21:34:54 +00:00
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; Basic tile functions
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2022-05-18 05:34:25 +00:00
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; Copy tileset data from a pointer in memory to the tiledata back
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; X = high word
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; A = low word
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_LoadTileSet
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sta tmp0
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2022-05-19 03:49:14 +00:00
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stx tmp1
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2022-05-18 05:34:25 +00:00
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ldy #0
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tyx
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:loop lda [tmp0],y
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stal tiledata,x
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dex
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dex
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dey
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dey
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bne :loop
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rts
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2022-04-25 21:34:54 +00:00
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; Low-level function to take a tile descriptor and return the address in the tiledata
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; bank. This is not too useful in the fast-path because the fast-path does more
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; incremental calculations, but it is handy for other utility functions
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;
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; A = tile descriptor
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;
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; The address is the TileID * 128 + (HFLIP * 64)
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_GetTileAddr
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asl ; Multiply by 2
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2022-05-18 05:34:25 +00:00
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bit #2*TILE_HFLIP_BIT ; Check if the horizontal flip bit is set
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beq :no_flip
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2022-04-25 21:34:54 +00:00
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inc ; Set the LSB
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:no_flip asl ; x4
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asl ; x8
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asl ; x16
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asl ; x32
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asl ; x64
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asl ; x128
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rts
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; Ignore the horizontal flip bit
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_GetBaseTileAddr
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asl ; Multiply by 2
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asl ; x4
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asl ; x8
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asl ; x16
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asl ; x32
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asl ; x64
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asl ; x128
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rts
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2022-04-29 17:38:04 +00:00
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; Helper function to get the address offset into the tile cachce / tile backing store
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; X = tile column [0, 40] (41 columns)
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; Y = tile row [0, 25] (26 rows)
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_GetTileStoreOffset
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phx ; preserve the registers
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phy
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jsr _GetTileStoreOffset0
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ply
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plx
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rts
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_GetTileStoreOffset0
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tya
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asl
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tay
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txa
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asl
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clc
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adc TileStoreYTable,y
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rts
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2022-04-25 21:34:54 +00:00
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; Initialize the tile storage data structures. This takes care of populating the tile records with the
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; appropriate constant values.
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InitTiles
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:col equ tmp0
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:row equ tmp1
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:vbuff equ tmp2
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2022-06-01 18:55:04 +00:00
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; Initialize the Tile Store
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2022-04-25 21:34:54 +00:00
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ldx #TILE_STORE_SIZE-2
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lda #25
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sta :row
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lda #40
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sta :col
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lda #$8000
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sta :vbuff
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:loop
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2022-06-01 18:55:04 +00:00
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; The first set of values in the Tile Store that are changed during each frame based on the actions
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2022-04-25 21:34:54 +00:00
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; that are happening
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lda #0
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2022-05-20 04:40:45 +00:00
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sta TileStore+TS_TILE_ID,x ; clear the tile store with the special zero tile
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sta TileStore+TS_TILE_ADDR,x
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sta TileStore+TS_SPRITE_FLAG,x ; no sprites are set at the beginning
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sta TileStore+TS_DIRTY,x ; none of the tiles are dirty
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2022-04-25 21:34:54 +00:00
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2022-06-01 18:55:04 +00:00
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; Set the default tile rendering functions
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lda EngineMode
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bit #ENGINE_MODE_DYN_TILES+ENGINE_MODE_TWO_LAYER
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beq :fast
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; ldal TileProcs
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; sta TileStore+TS_BASE_TILE_DISP,x
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bra :out
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:fast
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ldal FastTileProcs
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sta TileStore+TS_BASE_TILE_DISP,x
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:out
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2022-04-25 21:34:54 +00:00
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; lda DirtyTileProcs ; Fill in with the first dispatch address
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; stal TileStore+TS_DIRTY_TILE_DISP,x
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;
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; lda TileProcs ; Same for non-dirty, non-sprite base case
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; stal TileStore+TS_BASE_TILE_DISP,x
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2022-06-01 18:55:04 +00:00
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2022-04-25 21:34:54 +00:00
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; The next set of values are constants that are simply used as cached parameters to avoid needing to
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; calculate any of these values during tile rendering
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lda :row ; Set the long address of where this tile
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asl ; exists in the code fields
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tay
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2022-05-19 02:00:06 +00:00
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lda #>TileStore ; get middle 16 bits: "00 -->BBHH<-- LL"
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and #$FF00 ; merge with code field bank
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ora BRowTableHigh,y
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2022-05-20 04:40:45 +00:00
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sta TileStore+TS_CODE_ADDR_HIGH,x ; High word of the tile address (just the bank)
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2022-05-19 02:00:06 +00:00
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2022-04-25 21:34:54 +00:00
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lda BRowTableLow,y
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2022-05-20 04:40:45 +00:00
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sta TileStore+TS_BASE_ADDR,x ; May not be needed later if we can figure out the right constant...
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2022-04-25 21:34:54 +00:00
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lda :col ; Set the offset values based on the column
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asl ; of this tile
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asl
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2022-05-20 04:40:45 +00:00
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sta TileStore+TS_WORD_OFFSET,x ; This is the offset from 0 to 82, used in LDA (dp),y instruction
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2022-04-25 21:34:54 +00:00
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tay
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lda Col2CodeOffset+2,y
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clc
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2022-05-20 04:40:45 +00:00
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adc TileStore+TS_BASE_ADDR,x
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sta TileStore+TS_CODE_ADDR_LOW,x ; Low word of the tile address in the code field
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2022-04-25 21:34:54 +00:00
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dec :col
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bpl :hop
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dec :row
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lda #40
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sta :col
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:hop
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dex
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dex
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bpl :loop
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rts
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2022-04-29 17:38:04 +00:00
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; Set a tile value in the tile backing store. Mark dirty if the value changes
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;
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; A = tile id
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; X = tile column [0, 40] (41 columns)
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; Y = tile row [0, 25] (26 rows)
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;
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; Registers are not preserved
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_SetTile
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pha
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jsr _GetTileStoreOffset0 ; Get the address of the X,Y tile position
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2022-05-19 02:39:39 +00:00
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tay
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2022-04-29 17:38:04 +00:00
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pla
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2022-05-19 02:39:39 +00:00
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cmp TileStore+TS_TILE_ID,y ; Only set to dirty if the value changed
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2022-04-29 17:38:04 +00:00
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beq :nochange
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2022-05-19 02:39:39 +00:00
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sta TileStore+TS_TILE_ID,y ; Value is different, store it.
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2022-04-29 17:38:04 +00:00
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jsr _GetTileAddr
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2022-05-19 02:39:39 +00:00
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sta TileStore+TS_TILE_ADDR,y ; Committed to drawing this tile, so get the address of the tile in the tiledata bank for later
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2022-04-29 17:38:04 +00:00
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; Set the standard renderer procs for this tile.
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;
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; 1. The dirty render proc is always set the same.
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; 2. If BG1 and DYN_TILES are disabled, then the TS_BASE_TILE_DISP is selected from the Fast Renderers, otherwise
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; it is selected from the full tile rendering functions.
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; 3. The copy process is selected based on the flip bits
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;
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; When a tile overlaps the sprite, it is the responsibility of the Render function to compose the appropriate
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; functionality. Sometimes it is simple, but in cases of the sprites overlapping Dynamic Tiles and other cases
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; it can be more involved.
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2022-05-19 02:39:39 +00:00
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lda TileStore+TS_TILE_ID,y
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2022-04-29 17:38:04 +00:00
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and #TILE_VFLIP_BIT+TILE_HFLIP_BIT ; get the lookup value
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xba
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2022-05-19 02:39:39 +00:00
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tax
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; ldal DirtyTileProcs,x
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; sta TileStore+TS_DIRTY_TILE_DISP,y
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2022-04-29 17:38:04 +00:00
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2022-05-19 02:39:39 +00:00
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; ldal CopyTileProcs,x
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; sta TileStore+TS_DIRTY_TILE_COPY,y
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2022-04-29 17:38:04 +00:00
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lda EngineMode
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bit #ENGINE_MODE_DYN_TILES+ENGINE_MODE_TWO_LAYER
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beq :fast
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2022-05-19 02:39:39 +00:00
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lda TileStore+TS_TILE_ID,y ; Get the non-sprite dispatch address
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2022-04-29 17:38:04 +00:00
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and #TILE_CTRL_MASK
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xba
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2022-05-19 02:39:39 +00:00
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tax
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; ldal TileProcs,x
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; sta TileStore+TS_BASE_TILE_DISP,y
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2022-04-29 17:38:04 +00:00
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bra :out
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:fast
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2022-05-19 02:39:39 +00:00
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ldal FastTileProcs,x
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sta TileStore+TS_BASE_TILE_DISP,y
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2022-04-29 17:38:04 +00:00
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:out
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2022-05-19 02:39:39 +00:00
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jmp _PushDirtyTileY ; on the next call to _ApplyTiles
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2022-04-29 17:38:04 +00:00
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:nochange rts
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; SetBG0XPos
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;
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; Set the virtual horizontal position of the primary background layer. In addition to
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; updating the direct page state locations, this routine needs to preserve the original
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; value as well. This is a bit subtle, because if this routine is called multiple times
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; with different values, we need to make sure the *original* value is preserved and not
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; continuously overwrite it.
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;
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; We assume that there is a clean code field in this routine
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_SetBG0XPos
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cmp StartX
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beq :out ; Easy, if nothing changed, then nothing changes
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ldx StartX ; Load the old value (but don't save it yet)
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sta StartX ; Save the new position
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lda #DIRTY_BIT_BG0_X
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tsb DirtyBits ; Check if the value is already dirty, if so exit
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bne :out ; without overwriting the original value
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stx OldStartX ; First change, so preserve the value
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:out rts
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; SetBG0YPos
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;
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; Set the virtual position of the primary background layer.
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_SetBG0YPos
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cmp StartY
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beq :out ; Easy, if nothing changed, then nothing changes
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ldx StartY ; Load the old value (but don't save it yet)
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sta StartY ; Save the new position
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lda #DIRTY_BIT_BG0_Y
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tsb DirtyBits ; Check if the value is already dirty, if so exit
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bne :out ; without overwriting the original value
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stx OldStartY ; First change, so preserve the value
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:out rts
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2022-05-31 13:43:26 +00:00
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; Macro helper for the bit test tree
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; dobit bit_position,dest;next;exit
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dobit mac
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lsr
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bcc next_bit
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beq last_bit
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tax
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2022-06-02 17:28:49 +00:00
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lda (SPRITE_VBUFF_PTR+{]1*2}),y
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2022-05-31 13:43:26 +00:00
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sta sprite_ptr0+{]2*4}
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txa
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jmp ]3
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2022-06-02 17:28:49 +00:00
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last_bit lda (SPRITE_VBUFF_PTR+{]1*2}),y
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2022-05-31 13:43:26 +00:00
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sta sprite_ptr0+{]2*4}
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jmp ]4
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next_bit
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<<<
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; Specialization for the first sprite which can just return the vbuff address
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; in a register if there is only one sprite intersecting the tile
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2022-06-02 17:28:49 +00:00
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; dobit bit_position,dest;next;exit
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2022-05-31 13:43:26 +00:00
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dobit1 mac
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lsr
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bcc next_bit
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beq last_bit
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tax
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2022-06-02 17:28:49 +00:00
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lda (SPRITE_VBUFF_PTR+{]1*2}),y
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2022-05-31 13:43:26 +00:00
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sta sprite_ptr0+{]2*4}
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txa
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jmp ]3
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2022-06-02 17:28:49 +00:00
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last_bit lda (SPRITE_VBUFF_PTR+{]1*2}),y
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2022-05-31 13:43:26 +00:00
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jmp ]4
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next_bit
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<<<
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; Optimization discussion. In the Sprite2.s file, we calculate the VBUFF address for each tile overlapped
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; by a sprite:
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;
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; 4 lda VBuffOrigin
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; 3 adc ]2
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; 7 sta [tmp0],y
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;
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; and then in this macro it is loaded again and copied to the direct page. If a sprite is never drawn, this is
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; wasted work (which is not too ofter since >4 sprites would need to be overlapping), but still.
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;
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; 6 ldy: {]1*TILE_STORE_SIZE},x
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; 4 sty sprite_ptr0+{]2*4}
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;
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; Since we know *exactly* which sprite is being accessed, the _Sprites+TS_VBUFF_BASE,y value can be loaded without
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; an index
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;
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; 5 lda _Sprites+TS_VBUFF_BASE+{]1*2}
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; 6 adc {]1*TILE_STORE_SIZE},x
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; 4 sta sprite_ptr0+{]2*4}
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; 2 tya
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;
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; = a savings of at least (24 - 17) = 7 cycles per tile and more if the sprite is skipped.
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;
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; The problem is that this still required storing a value for the sprite in the tile store. What is ideal is
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; if there is a way to know implicitly which relative tile offset we are on for a given sprite and use
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; that to calculate the offset...
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;
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; What do we know
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; X = current tile
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; Sprite+TS_LOOKUP_INDEX
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;
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; txa
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; sbc _Sprites+TS_LOOKUP_INDEX+{]1*2}
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; tay
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; lda _Sprites+TS_VBUFF_BASE+{]1*2}
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; adc DisplacementTable,y
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; sta sprite_ptr0+{]2*4}
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;
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; Have the sprite select a table base which holds the offset values, pre-adjusted for the TS_LOOKUP_INDEX. The table
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; values are fixed. Yes!! This is the solution!! It will only need 288 bytes of total space
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;
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; Best implementation will pass the Tile Store index in Y instead of X
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;
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; 5 lda _Sprites+VBUFF_TABLE+{]1*2}
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; 6 sta self_mod
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; 6 lda $0000,x
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; 4 sta sprite_ptr0+{]2*4}
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; 2 tya
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;
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; or
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;
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; 5 lda _Sprites+VBUFF_TABLE+{]1*2}
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; 4 sta tmp0
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; 7 lda (tmp0),y
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; 4 sta sprite_ptr0+{]2*4}
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; 2 txa
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;
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; Even better, if the VBUFF_TABLE (only 32 bytes) was already stored in the second direct page
|
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;
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; 7 lda (VBUFF_TABLE+{]1*2}),y
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; 5 adc _Sprites+VBUFF_TABLE+{]1*2}
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; 4 sta sprite_ptr0+{]2*4}
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; 2 txa
|
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;
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; Final saving compared to current implementation is (24 - 18) = 6 cycles per tile and we eliminate
|
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|
|
; the need to pre-calculate
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;
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; If we find a last bit (4th in this case) and will exit
|
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|
stpbit mac
|
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lsr
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bcc next_bit
|
2022-06-02 17:28:49 +00:00
|
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|
lda (SPRITE_VBUFF_PTR+{]1*2}),y
|
2022-05-31 13:43:26 +00:00
|
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sta sprite_ptr0+{]2*4}
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|
|
jmp ]3
|
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|
next_bit
|
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|
<<<
|
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; Last bit test which *must* be set
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endbit mac
|
2022-06-02 17:28:49 +00:00
|
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|
lda (SPRITE_VBUFF_PTR+{]1*2}),y
|
2022-05-31 13:43:26 +00:00
|
|
|
sta sprite_ptr0+{]2*4}
|
|
|
|
jmp ]3
|
|
|
|
<<<
|
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|
|
|
|
|
|
; OPTIMIZATION:
|
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|
;
|
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|
; bit #$00FF ; Optimization to skip the first 8 bits if they are all zeros
|
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|
|
; bne norm_entry
|
|
|
|
; xba
|
|
|
|
; jmp skip_entry
|
|
|
|
;
|
|
|
|
; Placed at the entry point
|
|
|
|
|
|
|
|
; This is a complex, but fast subroutine that is called from the core tile rendering code. It
|
|
|
|
; Takes a bitmap of sprites in the Accumulator and then extracts the VBuff addresses for the
|
|
|
|
; target TileStore entry and places them in specific direct page locations.
|
|
|
|
;
|
|
|
|
; Inputs:
|
|
|
|
; A = sprite bitmap (assumed to be non-zero)
|
|
|
|
; Y = tile store index
|
|
|
|
; D = second work page
|
|
|
|
; B = vbuff array bank
|
|
|
|
; Output:
|
|
|
|
; X =
|
|
|
|
;
|
|
|
|
; ]1 address of single sprite process
|
|
|
|
; ]2 address of two sprite process
|
|
|
|
; ]3 address of three sprite process
|
|
|
|
; ]4 address of four sprite process
|
|
|
|
|
|
|
|
SpriteBitsToVBuffAddrs mac
|
|
|
|
dobit1 0;0;b_1_1;]1
|
|
|
|
dobit1 1;0;b_2_1;]1
|
|
|
|
dobit1 2;0;b_3_1;]1
|
|
|
|
dobit1 3;0;b_4_1;]1
|
|
|
|
dobit1 4;0;b_5_1;]1
|
|
|
|
dobit1 5;0;b_6_1;]1
|
|
|
|
dobit1 6;0;b_7_1;]1
|
|
|
|
dobit1 7;0;b_8_1;]1
|
|
|
|
dobit1 8;0;b_9_1;]1
|
|
|
|
dobit1 9;0;b_10_1;]1
|
|
|
|
dobit1 10;0;b_11_1;]1
|
|
|
|
dobit1 11;0;b_12_1;]1
|
|
|
|
dobit1 12;0;b_13_1;]1
|
|
|
|
dobit1 13;0;b_14_1;]1
|
|
|
|
dobit1 14;0;b_15_1;]1
|
2022-06-02 17:28:49 +00:00
|
|
|
endbit 15;0;]1
|
2022-05-31 13:43:26 +00:00
|
|
|
|
|
|
|
b_1_1 dobit 1;1;b_2_2;]2
|
|
|
|
b_2_1 dobit 2;1;b_3_2;]2
|
|
|
|
b_3_1 dobit 3;1;b_4_2;]2
|
|
|
|
b_4_1 dobit 4;1;b_5_2;]2
|
|
|
|
b_5_1 dobit 5;1;b_6_2;]2
|
|
|
|
b_6_1 dobit 6;1;b_7_2;]2
|
|
|
|
b_7_1 dobit 7;1;b_8_2;]2
|
|
|
|
b_8_1 dobit 8;1;b_9_2;]2
|
|
|
|
b_9_1 dobit 9;1;b_10_2;]2
|
|
|
|
b_10_1 dobit 10;1;b_11_2;]2
|
|
|
|
b_11_1 dobit 11;1;b_12_2;]2
|
|
|
|
b_12_1 dobit 12;1;b_13_2;]2
|
|
|
|
b_13_1 dobit 13;1;b_14_2;]2
|
|
|
|
b_14_1 dobit 14;1;b_15_2;]2
|
|
|
|
b_15_1 endbit 15;1;]2
|
|
|
|
|
|
|
|
b_2_2 dobit 2;2;b_3_3;]3
|
|
|
|
b_3_2 dobit 3;2;b_4_3;]3
|
|
|
|
b_4_2 dobit 4;2;b_5_3;]3
|
|
|
|
b_5_2 dobit 5;2;b_6_3;]3
|
|
|
|
b_6_2 dobit 6;2;b_7_3;]3
|
|
|
|
b_7_2 dobit 7;2;b_8_3;]3
|
|
|
|
b_8_2 dobit 8;2;b_9_3;]3
|
|
|
|
b_9_2 dobit 9;2;b_10_3;]3
|
|
|
|
b_10_2 dobit 10;2;b_11_3;]3
|
|
|
|
b_11_2 dobit 11;2;b_12_3;]3
|
|
|
|
b_12_2 dobit 12;2;b_13_3;]3
|
|
|
|
b_13_2 dobit 13;2;b_14_3;]3
|
|
|
|
b_14_2 dobit 14;2;b_15_3;]3
|
|
|
|
b_15_2 endbit 15;2;]3
|
|
|
|
|
|
|
|
b_3_3 stpbit 3;3;]4
|
|
|
|
b_4_3 stpbit 4;3;]4
|
|
|
|
b_5_3 stpbit 5;3;]4
|
|
|
|
b_6_3 stpbit 6;3;]4
|
|
|
|
b_7_3 stpbit 7;3;]4
|
|
|
|
b_8_3 stpbit 8;3;]4
|
|
|
|
b_9_3 stpbit 9;3;]4
|
|
|
|
b_10_3 stpbit 10;3;]4
|
|
|
|
b_11_3 stpbit 11;3;]4
|
|
|
|
b_12_3 stpbit 12;3;]4
|
|
|
|
b_13_3 stpbit 13;3;]4
|
|
|
|
b_14_3 stpbit 14;3;]4
|
|
|
|
b_15_3 endbit 15;3;]4
|
|
|
|
<<<
|