mirror of
https://github.com/lscharen/iigs-game-engine.git
synced 2024-06-07 11:29:33 +00:00
940 lines
32 KiB
ArmAsm
940 lines
32 KiB
ArmAsm
; Init
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sound_control = $3c ;really at $e1c03c
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sound_data = $3d ;really at $e1c03d
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sound_address = $3e ;really at $e1c03e
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sound_interrupt_ptr = $e1002c
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irq_volume = $e100ca
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osc_interrupt = $e100cc
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mx %10
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access_doc_registers = *
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ldal irq_volume
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sta sound_control
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rts
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access_doc_ram = *
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ldal irq_volume
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ora #%0110_0000
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sta sound_control
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rts
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access_doc_ram_no_inc = *
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ldal irq_volume
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ora #%0100_0000
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sta sound_control
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rts
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mx %00
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APUStartUp
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sei
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phd
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pea $c000
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pld
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jsr copy_instruments_to_doc
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jsr setup_doc_registers
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jsr setup_interrupt
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pld
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cli
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rts
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APUShutDown = *
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sei
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phd
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lda #$c000
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tcd
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jsr stop_playing
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lda backup_interrupt_ptr ; restore old interrupt ptr
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stal sound_interrupt_ptr
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lda backup_interrupt_ptr+2
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stal sound_interrupt_ptr+2
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cli
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pld
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clc
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rts
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stop_playing = *
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ldy #7 ; Number of oscillators
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sep #$20
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mx %10
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jsr access_doc_registers
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lda #$a0 ; stop all oscillators in use
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sta sound_address
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lda #%11
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]loop sta sound_data
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inc sound_address
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dey
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bne ]loop
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lda #$a0+interrupt_oscillator ; stop interrupt oscillator
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sta sound_address
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lda #3
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sta sound_data
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rep #$20
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mx %00
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rts
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; Copy in 4 different square wave duty cycles and a triangle wave
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copy_instruments_to_doc
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jsr setup_docram
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lda #$0100
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jsr make_eigth_pulse
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lda #$0200
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jsr make_quarter_pulse
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lda #$0300
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jsr make_half_pulse
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lda #$0400
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jsr make_inv_quarter_pulse
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lda #$0500
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jsr copy_triangle
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rts
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;--------------------------
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setup_docram
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sep #$20
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mx %10
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jsr access_doc_ram
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stz sound_address
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lda #$80
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ldx #256 ;make sure that page 00 has nonzero data for interrupt
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:loop sta sound_data
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dex
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bne :loop
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rep #$20
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mx %00
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rts
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;--------------------------
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make_eigth_pulse
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ldy #32
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jmp make_pulse
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make_quarter_pulse
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ldy #64
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jmp make_pulse
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make_half_pulse
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ldy #128
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jmp make_pulse
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make_inv_quarter_pulse
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ldy #192
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jmp make_pulse
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make_pulse
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sep #$30
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mx %11
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stz sound_address
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xba
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sta sound_address+1
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ldx #0
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:loop1
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lda #$01
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sta sound_data
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inx
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dey
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bne :loop1
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:loop2
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lda #$FF
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sta sound_data
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inx
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bne :loop2
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rep #$30
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mx %00
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rts
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copy_triangle
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sep #$30
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mx %11
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stz sound_address
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xba
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sta sound_address+1
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ldx #0
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:loop
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lda triangle_wave,x
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sta sound_data
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inx
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bne :loop
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rep #$30
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mx %00
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rts
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;--------------------------
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triangle_wave
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hex 80828486888a8c8e90929496989a9c9e
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hex a0a2a4a6a8aaacaeb0b2b4b6b8babcbe
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hex c0c1c3c5c7c9cbcdcfd1d3d5d7d9dbdd
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hex dfe1e3e5e7e9ebedeff1f3f5f7f9fbfd
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hex fffdfbf9f7f5f3f1efedebe9e7e5e3e1
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hex dfdddbd9d7d5d3d1cfcdcbc9c7c5c3c1
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hex c0bebcbab8b6b4b2b0aeacaaa8a6a4a2
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hex a09e9c9a98969492908e8c8a88868482
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hex 807e7c7a78767472706e6c6a68666462
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hex 605e5c5a58565452504e4c4a48464442
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hex 413f3d3b39373533312f2d2b29272523
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hex 211f1d1b19171513110f0d0b09070503
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hex 01030507090b0d0f11131517191b1d1f
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hex 21232527292b2d2f31333537393b3d3f
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hex 41424446484a4c4e50525456585a5c5e
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hex 60626466686a6c6e70727476787a7c7e
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;--------------------------
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setup_doc_registers
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sep #$20
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mx %10
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jsr access_doc_registers
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ldx #pulse1_sound_settings
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jsr copy_register_config
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ldx #pulse2_sound_settings
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jsr copy_register_config
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ldx #triangle_sound_settings
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jsr copy_register_config
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rep #$20
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mx %00
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rts
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copy_register_config
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ldy #0
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:loop lda: 0,x ; Set DOC registers for the NES channels
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sta sound_address
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inx
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lda: 0,x
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sta sound_data
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inx
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iny
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cpy #6 ; 6 pairs to describe this oscillator
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bne :loop
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rts
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;--------------------------
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setup_interrupt = *
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ldal sound_interrupt_ptr
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sta backup_interrupt_ptr
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ldal sound_interrupt_ptr+2
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sta backup_interrupt_ptr+2
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lda #$5c
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stal sound_interrupt_ptr
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phk
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phk
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pla
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stal sound_interrupt_ptr+2
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lda #interrupt_handler
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stal sound_interrupt_ptr+1
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sep #$20
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mx %10
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jsr access_doc_registers
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ldy #0
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:loop lda timer_sound_settings,y ; Set DOC registers for the interrupt oscillator
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sta sound_address
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iny
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lda timer_sound_settings,y
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sta sound_data
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iny
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cpy #7*2
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bne :loop
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rep #$20
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mx %00
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rts
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interrupt_oscillator = 31
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reference_freq = 1195 ; interrupt frequence (240Hz)
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timer_sound_settings = * ; set up oscillator 30 for interrupts
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dfb $00+interrupt_oscillator,reference_freq ; frequency low register
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dfb $20+interrupt_oscillator,reference_freq/256 ; frequency high register
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dfb $40+interrupt_oscillator,0 ; volume register, volume = 0
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dfb $80+interrupt_oscillator,0 ; wavetable pointer register, point to 0
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dfb $c0+interrupt_oscillator,0 ; wavetable size register, 256 byte length
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dfb $e1,$3e ; oscillator enable register
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dfb $a0+interrupt_oscillator,$08 ; mode register, set to free run
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pulse1_oscillator = 0
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pulse2_oscillator = 2
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triangle_oscillator = 4
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default_freq = 5000
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pulse1_sound_settings = *
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dfb $00+pulse1_oscillator,default_freq ; frequency low register
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dfb $20+pulse1_oscillator,default_freq/256 ; frequency high register
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dfb $40+pulse1_oscillator,0 ; volume register, volume = 0
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dfb $80+pulse1_oscillator,3 ; wavetable pointer register, point to $0300 by default (50% duty cycle)
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dfb $c0+pulse1_oscillator,0 ; wavetable size register, 256 byte length
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dfb $a0+pulse1_oscillator,0 ; mode register, set to free run
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pulse2_sound_settings = *
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dfb $00+pulse2_oscillator,default_freq ; frequency low register
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dfb $20+pulse2_oscillator,default_freq/256 ; frequency high register
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dfb $40+pulse2_oscillator,0 ; volume register, volume = 0
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dfb $80+pulse2_oscillator,3 ; wavetable pointer register, point to $0300 by default (50% duty cycle)
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dfb $c0+pulse2_oscillator,0 ; wavetable size register, 256 byte length
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dfb $a0+pulse2_oscillator,0 ; mode register, set to free run
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triangle_sound_settings = *
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dfb $00+triangle_oscillator,default_freq ; frequency low register
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dfb $20+triangle_oscillator,default_freq/256 ; frequency high register
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dfb $40+triangle_oscillator,0 ; volume register, volume = 0
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dfb $80+triangle_oscillator,5 ; wavetable pointer register, point to $0500
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dfb $c0+triangle_oscillator,0 ; wavetable size register, 256 byte length
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dfb $a0+triangle_oscillator,0 ; mode register, set to free run
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backup_interrupt_ptr ds 4
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;-----------------------------------------------------------------------------------------
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; APU internals
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;-----------------------------------------------------------------------------------------
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mx %11
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clock_length mac
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lda ]1+{APU_PULSE1_REG1-APU_PULSE1}
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bit #PULSE_HALT_FLAG
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bne no_count
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lda ]1+{APU_PULSE1_LENGTH_COUNTER-APU_PULSE1}
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beq no_count
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dec
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sta ]1+{APU_PULSE1_LENGTH_COUNTER-APU_PULSE1}
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no_count <<<
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clock_sweep mac
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lda ]1+{APU_PULSE1_SWEEP_DIVIDER-APU_PULSE1}
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dec
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sta ]1+{APU_PULSE1_SWEEP_DIVIDER-APU_PULSE1}
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bpl no_sweep
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lda #1
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sta ]1+{APU_PULSE1_RELOAD_FLAG-APU_PULSE1}
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lda ]1+{APU_PULSE1_REG2-APU_PULSE1} ; get the barrel shift argument from the register
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bpl no_sweep ; if sweep is not enabled, do nothing
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and #$07
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beq no_sweep ; shift must be != 0
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asl
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tax
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lda ]1+{APU_PULSE1_REG2-APU_PULSE1} ; put the negate flag in the y register
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and #$08
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tay
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rep #$20
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lda ]1+{APU_PULSE1_CURRENT_PERIOD-APU_PULSE1}
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cmp #8
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bcc no_sweep0 ; current period must be >= 8
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lda ]1+{APU_PULSE1_REG3-APU_PULSE1} ; raw period stored in the register
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and #$7FF
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jmp (bitshift,x) ; shift it by the shifter amount
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bitshift da bitshift_0,bitshift_1,bitshift_2,bitshift_3,bitshift_4,bitshift_5,bitshift_6,bitshift_7
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bitshift_7 lsr
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bitshift_6 lsr
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bitshift_5 lsr
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bitshift_4 lsr
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bitshift_3 lsr
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bitshift_2 lsr
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bitshift_1 lsr
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bitshift_0
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cpy #0 ; check if the negate flag was set
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beq no_negate
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eor #$FFFF ; pulse 1 uses 1's complement
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DO ]2
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inc
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FIN
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no_negate clc
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adc ]1+{APU_PULSE1_CURRENT_PERIOD-APU_PULSE1}
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sta ]1+{APU_PULSE1_TARGET_PERIOD-APU_PULSE1}
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stz ]1+{APU_PULSE1_MUTE-APU_PULSE1}
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ldy #1
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cmp #$800
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bcc *+5
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sty ]1+{APU_PULSE1_MUTE-APU_PULSE1} ; mute the output is the period is too large
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bcs *+5
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sta ]1+{APU_PULSE1_CURRENT_PERIOD-APU_PULSE1} ; set the current period if the target is within a valid range
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lda ]1+{APU_PULSE1_CURRENT_PERIOD-APU_PULSE1}
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cmp #8
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bcs *+5
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sty ]1+{APU_PULSE1_MUTE-APU_PULSE1} ; mute the output if the period is too small
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no_sweep0
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sep #$20
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no_sweep
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lda ]1+{APU_PULSE1_RELOAD_FLAG-APU_PULSE1} ; check if we need to reload the sweep delay
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beq no_reload
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stz ]1+{APU_PULSE1_RELOAD_FLAG-APU_PULSE1}
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lda ]1+{APU_PULSE1_REG2-APU_PULSE1}
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lsr
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lsr
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lsr
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lsr
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and #7
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sta ]1+{APU_PULSE1_SWEEP_DIVIDER-APU_PULSE1}
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no_reload <<<
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clock_envelope mac
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lda ]1+{APU_PULSE1_START_FLAG-APU_PULSE1}
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beq no_start
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stz ]1+{APU_PULSE1_START_FLAG-APU_PULSE1} ; clear the start flag
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lda #15
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sta ]1+{APU_PULSE1_ENVELOPE-APU_PULSE1} ; reset the envelope saw wave decay value
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lda ]1+{APU_PULSE1_REG1-APU_PULSE1}
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and #$0F
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sta ]1+{APU_PULSE1_ENVELOPE_DIVIDER-APU_PULSE1} ; reset the divider value
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bra envelope_out ; nothing else to do
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no_start
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lda ]1+{APU_PULSE1_ENVELOPE_DIVIDER-APU_PULSE1} ; clock the divider
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dec
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sta ]1+{APU_PULSE1_ENVELOPE_DIVIDER-APU_PULSE1}
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bpl envelope_out ; as long as divider is >=0, nothing to do
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lda ]1+{APU_PULSE1_REG1-APU_PULSE1} ; reset the divider to the volume/envelope value
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and #$0F
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sta ]1+{APU_PULSE1_ENVELOPE_DIVIDER-APU_PULSE1}
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lda ]1+{APU_PULSE1_ENVELOPE-APU_PULSE1}
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bne tick_envelope
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lda ]1+{APU_PULSE1_REG1-APU_PULSE1} ; if decay level counter is 0, check the loop bit and set counter to 15 if loop bit is set
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bit #PULSE_HALT_FLAG
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beq envelope_out
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lda #16 ; Set to 15
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tick_envelope
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dec
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sta ]1+{APU_PULSE1_ENVELOPE-APU_PULSE1}
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envelope_out <<<
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;-----------------------------------------------------------------------------------------
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; interupt handler
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;-----------------------------------------------------------------------------------------
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apu_frame_steps equ 5
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PULSE_HALT_FLAG equ $20
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PULSE_CONST_VOL_FLAG equ $10
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interrupt_handler = *
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phb
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phd
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phk
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plb
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clc
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xce
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rep #$30
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mx %00
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lda #$c000
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tcd
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sep #$30
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mx %11
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; Update the frame counter. We double-count so that frame counter can be used directly to dispatch to the
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; appropriate tick handler
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ldx apu_frame_counter
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inx
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inx
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cpx #2*apu_frame_steps ; TODO: This is set by MSB in $4017 (4 or 5). 4 = PAL, 5 = NTSC.
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bcc *+4
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ldx #0
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stx apu_frame_counter
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jmp (:frame_counter_proc,x)
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:frame_counter_proc da :quarter_frame,:half_frame,:quarter_frame,:no_frame,:half_frame
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:half_frame
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; clock the length counters
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clock_length APU_PULSE1
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clock_length APU_PULSE2
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; clock the sweep units
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clock_sweep APU_PULSE1;0
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clock_sweep APU_PULSE2;1
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; quarter frame updates run every APU frame (for 4-cycle)
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:quarter_frame
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; clock the envelopes and triangle linear counter
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clock_envelope APU_PULSE1
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clock_envelope APU_PULSE2
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:no_frame
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jsr access_doc_registers
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ldal osc_interrupt ; which oscillator generated the interrupt?
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and #%00111110
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lsr
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cmp #interrupt_oscillator
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beq *+5
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brl :not_timer ; Only service timer interrupts
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; Set the parameters for the first square wave channel
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lda #$80+pulse1_oscillator
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sta sound_address
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lda APU_PULSE1_REG1 ; Get the cycle duty bits
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jsr set_pulse_duty_cycle
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lda #$40+pulse1_oscillator
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sta sound_address
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lda APU_PULSE1_MUTE ; If the sweep muted the channel, no output
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beq :no_mute_pulse1
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lda #0
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bra :set_volume_pulse1
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:no_mute_pulse1
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lda APU_PULSE1_LENGTH_COUNTER ; If the length counter is zero, no output
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beq :set_volume_pulse1
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lda APU_PULSE1_REG1
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bit #PULSE_CONST_VOL_FLAG ; Check the constant volume bit
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bne :set_volume_pulse1
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lda APU_PULSE1_ENVELOPE
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:set_volume_pulse1
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jsr set_pulse_volume
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|
|
|
rep #$30
|
|
lda APU_PULSE1_CURRENT_PERIOD
|
|
jsr get_pulse_freq ; return freq in 16-bit accumulator
|
|
sep #$30
|
|
ldx #$00+pulse1_oscillator
|
|
stx sound_address
|
|
sta sound_data
|
|
ldx #$20+pulse1_oscillator
|
|
stx sound_address
|
|
xba
|
|
sta sound_data
|
|
|
|
; Now do the second square wave
|
|
|
|
lda #$80+pulse2_oscillator
|
|
sta sound_address
|
|
lda APU_PULSE2_REG1 ; Get the cycle duty bits
|
|
jsr set_pulse_duty_cycle
|
|
|
|
lda #$40+pulse2_oscillator
|
|
sta sound_address
|
|
|
|
lda APU_PULSE2_MUTE ; If the sweep muted the channel, no output
|
|
beq :no_mute_pulse2
|
|
lda #0
|
|
bra :set_volume_pulse2
|
|
:no_mute_pulse2
|
|
lda APU_PULSE2_LENGTH_COUNTER ; If the length counter is zero, no output
|
|
beq :set_volume_pulse2
|
|
lda APU_PULSE2_REG1
|
|
bit #PULSE_CONST_VOL_FLAG ; Check the constant volume bit
|
|
bne :set_volume_pulse2
|
|
lda APU_PULSE2_ENVELOPE
|
|
:set_volume_pulse2
|
|
jsr set_pulse_volume
|
|
|
|
rep #$30
|
|
lda APU_PULSE2_CURRENT_PERIOD
|
|
jsr get_pulse_freq ; return freq in 16-bic accumulator
|
|
sep #$30
|
|
ldx #$00+pulse2_oscillator
|
|
stx sound_address
|
|
sta sound_data
|
|
ldx #$20+pulse2_oscillator
|
|
stx sound_address
|
|
xba
|
|
sta sound_data
|
|
|
|
; Now the triangle wave. This wave needs linear counter support to be silenced
|
|
; brl :not_timer
|
|
|
|
rep #$30
|
|
lda APU_TRIANGLE_REG3
|
|
jsr get_pulse_freq ; return freq in 16-bic accumulator
|
|
lsr
|
|
sep #$30
|
|
|
|
ldx #$00+triangle_oscillator
|
|
stx sound_address
|
|
sta sound_data
|
|
ldx #$20+triangle_oscillator
|
|
stx sound_address
|
|
xba
|
|
sta sound_data
|
|
|
|
; lda border_color
|
|
; inc
|
|
; and #$03
|
|
; sta border_color
|
|
; jsr setborder
|
|
|
|
:not_timer
|
|
sep #$30
|
|
pld
|
|
plb
|
|
clc
|
|
rtl
|
|
|
|
set_pulse_duty_cycle
|
|
mx %11
|
|
rol
|
|
rol
|
|
rol
|
|
and #$03
|
|
tax
|
|
|
|
lda duty_cycle_page,x
|
|
sta sound_data
|
|
rts
|
|
|
|
set_pulse_volume
|
|
and #$0F
|
|
asl
|
|
asl
|
|
asl
|
|
asl
|
|
sta sound_data
|
|
rts
|
|
|
|
; NES freq = f_CPU / (16 * (t + 1))
|
|
; = 1.789773 MHz / (16 * (t + 1))
|
|
; = 111860.812 Hz / (t + 1)
|
|
;
|
|
; IIgs freq = 0.200807 * F_HL (for 32 oscillators with DOC RES = 0)
|
|
;
|
|
; Solving for F_HL = (1 / 0.200807) * 111860.812 / (t + 1)
|
|
; = 557056.338 / (t + 1)
|
|
;
|
|
; if t < 8 this value is out of range and the oscillator should be silenced
|
|
;
|
|
; otherwise, break apart the ratio
|
|
;
|
|
; f_HL = 10 * (55706 / (t + 1))
|
|
;
|
|
get_pulse_freq
|
|
mx %00
|
|
and #$7FF ; prevent overflow...
|
|
inc
|
|
sta divisor
|
|
lda #55706
|
|
sta dividend
|
|
|
|
lda #0
|
|
ldx #16 ; 16 bits of division
|
|
asl dividend
|
|
:dl1 rol
|
|
cmp divisor
|
|
bcc :dl2
|
|
sbc divisor
|
|
:dl2 rol dividend
|
|
dex
|
|
bne :dl1
|
|
|
|
lda dividend
|
|
sta dividend
|
|
asl
|
|
asl
|
|
clc
|
|
adc dividend ; multiple by 10 to get the DOC value
|
|
asl
|
|
rts
|
|
|
|
turn_off_interrupts
|
|
php
|
|
sep #$20
|
|
lda #$a0+interrupt_oscillator
|
|
sta sound_address
|
|
lda #0
|
|
sta sound_data
|
|
plp
|
|
rts
|
|
|
|
; Internal APU registers.
|
|
;
|
|
; These variables track the internal flags, counters and other status bits that make up
|
|
; the core functionality of the different channel hardware
|
|
|
|
apu_frame_counter dw 0 ; frame counter, clocked at 240Hz from the interrupt handler
|
|
|
|
; Internal APU register offsets
|
|
;length_counter_halt equ 0
|
|
;length_counter equ 1
|
|
;constant_volume_flag equ 2
|
|
;volume equ 3
|
|
;current_period equ 4
|
|
;target_period equ 6
|
|
|
|
; Internal APU registers for channel 1
|
|
;apu_pulse1 ds 8
|
|
;apu_pulse2 ds 8
|
|
|
|
;apu_pulse1_length_counter dfb 0
|
|
;apu_pulse1_decay_level dfb 0
|
|
;apu_pulse1_current_period dw 0
|
|
|
|
;apu_pulse2_length_counter dfb 0
|
|
;apu_pulse2_decay_level dfb 0
|
|
;apu_pulse2_current_period dw 0
|
|
|
|
duty_cycle_page dfb $01,$02,$03,$04 ; Page of DOC RAM that holds the different duty cycle wavforms
|
|
border_color dw 0
|
|
dividend dw 0
|
|
divisor dw 0
|
|
|
|
last_phase1_duty_cycle dfb $ff
|
|
last_phase2_duty_cycle dfb $ff
|
|
; 8-bit mode
|
|
; A = register number
|
|
; X = register value
|
|
mx %00
|
|
SetDOCReg
|
|
stal $E0C03E
|
|
txa
|
|
stal $E0C03D
|
|
rts
|
|
|
|
_SetDOCReg mac
|
|
lda ]1 ; Select the oscillator enable registers
|
|
ldx ]2
|
|
jsr SetDOCReg
|
|
<<<
|
|
|
|
; Pulse Channel 1
|
|
APU_PULSE1
|
|
APU_PULSE1_REG1 ds 1 ; DDLC NNNN - Duty, length counter halt, constant volume/evelope, envelope period/volume
|
|
APU_PULSE1_REG2 ds 1 ; EPPP NSSS - Sweep unit: enabled, period, negative, shift count
|
|
APU_PULSE1_REG3 ds 1 ; LLLL LLLL - Timer Low
|
|
APU_PULSE1_REG4 ds 1 ; llll lHHH - Length counter load, timer high (also resets duty and starts envelope)
|
|
|
|
APU_PULSE1_LENGTH_COUNTER dfb 0 ; internal register for the length counter
|
|
APU_PULSE1_RELOAD_FLAG dfb 0 ; internal register to reload the sweep divider value
|
|
APU_PULSE1_SWEEP_DIVIDER dfb 0 ; internal register to track the sweep divider value
|
|
APU_PULSE1_TARGET_PERIOD dw 0 ; internal register to hold the sweep unit target period
|
|
APU_PULSE1_CURRENT_PERIOD dw 0 ; internal register to hold the current period driving the oscillator
|
|
APU_PULSE1_MUTE dfb 0
|
|
APU_PULSE1_START_FLAG dfb 0
|
|
APU_PULSE1_ENVELOPE_DIVIDER dfb 0
|
|
APU_PULSE1_ENVELOPE dfb 0
|
|
|
|
_apu_pulse1_last_period dw 0 ; optimization
|
|
|
|
|
|
APU_PULSE2
|
|
APU_PULSE2_REG1 ds 1 ; DDLC NNNN - Duty, length counter halt, constant volume/evelope, envelope period/volume
|
|
APU_PULSE2_REG2 ds 1 ; EPPP NSSS - Sweep unit: enabled, period, negative, shift count
|
|
APU_PULSE2_REG3 ds 1 ; LLLL LLLL - Timer Low
|
|
APU_PULSE2_REG4 ds 1 ; llll lHHH - Length counter load, timer high (also resets duty and starts envelope)
|
|
|
|
APU_PULSE2_LENGTH_COUNTER dfb 0 ; internal register for the length counter
|
|
APU_PULSE2_RELOAD_FLAG dfb 0 ; internal register to reload the sweep divider value
|
|
APU_PULSE2_SWEEP_DIVIDER dfb 0 ; internal register to track the sweep divider value
|
|
APU_PULSE2_TARGET_PERIOD dw 0 ; internal register to hold the sweep unit target period
|
|
APU_PULSE2_CURRENT_PERIOD dw 0 ; internal register to hold the current period driving the oscillator
|
|
APU_PULSE2_MUTE dfb 0
|
|
APU_PULSE2_START_FLAG dfb 0
|
|
APU_PULSE2_ENVELOPE_DIVIDER dfb 0
|
|
APU_PULSE2_ENVELOPE dfb 0
|
|
|
|
_apu_pulse2_last_period dw 0 ; optimization
|
|
|
|
|
|
APU_TRIANGLE
|
|
APU_TRIANGLE_REG1 ds 1 ; DDLC NNNN - Duty, loop envelope/disable length counter, constant volume, envelope period/volume
|
|
APU_TRIANGLE_REG2 ds 1 ; EPPP NSSS - Sweep unit: enabled, period, negative, shift count
|
|
APU_TRIANGLE_REG3 ds 1 ; LLLL LLLL - Timer Low
|
|
APU_TRIANGLE_REG4 ds 1 ; llll lHHH - Length counter load, timer high (also resets duty and starts envelope)
|
|
|
|
APU_STATUS ds 1
|
|
|
|
mx %11
|
|
APU_PULSE1_REG1_WRITE ENT
|
|
stal APU_PULSE1_REG1
|
|
rtl
|
|
|
|
APU_PULSE1_REG2_WRITE ENT
|
|
php
|
|
pha
|
|
stal APU_PULSE1_REG2
|
|
lda #1
|
|
stal APU_PULSE1_RELOAD_FLAG ; mark that this register was written to
|
|
pla
|
|
plp
|
|
rtl
|
|
|
|
APU_PULSE1_REG3_WRITE ENT
|
|
stal APU_PULSE1_CURRENT_PERIOD
|
|
stal APU_PULSE1_REG3
|
|
rtl
|
|
|
|
APU_PULSE1_REG4_WRITE ENT
|
|
php
|
|
phx
|
|
pha
|
|
|
|
stal APU_PULSE1_REG4
|
|
and #$07
|
|
stal APU_PULSE1_CURRENT_PERIOD+1
|
|
|
|
; If the APU_STATUS bit is enabled, then load the length counter
|
|
ldal APU_STATUS
|
|
bit #$01
|
|
beq :no_reload
|
|
|
|
ldal APU_PULSE1_REG4
|
|
and #$F8
|
|
lsr
|
|
lsr
|
|
lsr
|
|
tax
|
|
ldal LengthTable,x
|
|
stal APU_PULSE1_LENGTH_COUNTER ; Immediately start the counter
|
|
lda #1
|
|
stal APU_PULSE1_START_FLAG
|
|
|
|
:no_reload
|
|
pla
|
|
plx
|
|
plp
|
|
rtl
|
|
|
|
; From https://www.nesdev.org/wiki/APU_Length_Counter
|
|
LengthTable
|
|
db 10,254, 20, 2, 40, 4, 80, 6, 160, 8, 60, 10, 14, 12, 26, 14
|
|
db 12, 16, 24, 18, 48, 20, 96, 22, 192, 24, 72, 26, 16, 28, 32, 30
|
|
|
|
APU_PULSE2_REG1_WRITE ENT
|
|
stal APU_PULSE2_REG1
|
|
rtl
|
|
|
|
APU_PULSE2_REG2_WRITE ENT
|
|
php
|
|
pha
|
|
stal APU_PULSE2_REG2
|
|
lda #1
|
|
stal APU_PULSE2_RELOAD_FLAG
|
|
pla
|
|
plp
|
|
rtl
|
|
|
|
APU_PULSE2_REG3_WRITE ENT
|
|
stal APU_PULSE2_CURRENT_PERIOD
|
|
stal APU_PULSE2_REG3
|
|
rtl
|
|
|
|
APU_PULSE2_REG4_WRITE ENT
|
|
php
|
|
phx
|
|
pha
|
|
|
|
stal APU_PULSE2_REG4
|
|
and #$07
|
|
stal APU_PULSE2_CURRENT_PERIOD+1
|
|
|
|
ldal APU_STATUS
|
|
bit #$01
|
|
beq :no_reload
|
|
|
|
ldal APU_PULSE2_REG4
|
|
and #$F8
|
|
lsr
|
|
lsr
|
|
lsr
|
|
tax
|
|
ldal LengthTable,x
|
|
stal APU_PULSE2_LENGTH_COUNTER ; Immediately start the counter
|
|
lda #1
|
|
stal APU_PULSE2_START_FLAG
|
|
|
|
:no_reload
|
|
pla
|
|
plx
|
|
plp
|
|
rtl
|
|
|
|
|
|
APU_TRIANGLE_REG1_WRITE ENT
|
|
stal APU_TRIANGLE_REG1
|
|
rtl
|
|
|
|
APU_TRIANGLE_REG2_WRITE ENT
|
|
stal APU_TRIANGLE_REG2
|
|
rtl
|
|
|
|
APU_TRIANGLE_REG3_WRITE ENT
|
|
stal APU_TRIANGLE_REG3
|
|
rtl
|
|
|
|
APU_TRIANGLE_REG4_WRITE ENT
|
|
stal APU_TRIANGLE_REG4
|
|
rtl
|
|
|
|
|
|
APU_STATUS_WRITE ENT
|
|
stal APU_STATUS
|
|
pha
|
|
|
|
; From NESDev Wiki: When the enabled bit is cleared (via $4015), the length counter is forced to 0
|
|
; and cannot be changed until enabled is set again (the length counter's previous value is lost).
|
|
; There is no immediate effect when enabled is set.
|
|
|
|
; Pulse 1
|
|
bit #$01
|
|
bne :pulse1_on
|
|
stz APU_PULSE1_LENGTH_COUNTER
|
|
:pulse1_on
|
|
|
|
; Pulse 2
|
|
bit #$02
|
|
bne :pulse2_on
|
|
stz APU_PULSE2_LENGTH_COUNTER
|
|
:pulse2_on
|
|
|
|
; Triangle is OSC 4
|
|
; bit #$03
|
|
; beq :triangle_off
|
|
; _SetDOCReg #$40+triangle_oscillator;#128
|
|
; bra :triangle_end
|
|
;:triangle_off
|
|
; _SetDOCReg #$40+triangle_oscillator;#0
|
|
;:triangle_end
|
|
|
|
pla
|
|
rtl
|