1325 lines
45 KiB
ArmAsm
1325 lines
45 KiB
ArmAsm
; Init
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sound_control = $3c ;really at $e1c03c
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sound_data = $3d ;really at $e1c03d
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sound_address = $3e ;really at $e1c03e
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sound_interrupt_ptr = $e1002c
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irq_volume = $e100ca
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osc_interrupt = $e100cc
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mx %10
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access_doc_registers = *
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ldal irq_volume
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sta sound_control
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rts
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access_doc_ram = *
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ldal irq_volume
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ora #%0110_0000
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sta sound_control
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rts
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access_doc_ram_no_inc = *
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ldal irq_volume
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ora #%0100_0000
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sta sound_control
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rts
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mx %00
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APUStartUp
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stal apu_mode
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sei
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phd
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pea $c000
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pld
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jsr copy_instruments_to_doc
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jsr setup_doc_registers
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jsr setup_interrupt
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pld
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cli
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rts
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APUShutDown = *
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sei
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phd
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lda #$c000
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tcd
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jsr stop_playing
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ldal apu_mode
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cmp #2
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beq :no_doc_interrupts
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lda backup_interrupt_ptr ; restore old interrupt ptr
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stal sound_interrupt_ptr
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lda backup_interrupt_ptr+2
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stal sound_interrupt_ptr+2
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:no_doc_interrupts
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cli
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pld
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clc
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rts
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stop_playing = *
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ldy #7 ; Number of oscillators
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sep #$20
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mx %10
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jsr access_doc_registers
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lda #$a0 ; stop all oscillators in use
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sta sound_address
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lda #%11
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]loop sta sound_data
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inc sound_address
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dey
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bne ]loop
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lda #$a0+interrupt_oscillator ; stop interrupt oscillator
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sta sound_address
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lda #3
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sta sound_data
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rep #$20
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mx %00
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rts
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; Copy in 4 different square wave duty cycles and a triangle wave
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copy_instruments_to_doc
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jsr setup_docram
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lda #$0100
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jsr make_eigth_pulse
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lda #$0200
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jsr make_quarter_pulse
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lda #$0300
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jsr make_half_pulse
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lda #$0400
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jsr make_inv_quarter_pulse
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lda #$0500
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jsr copy_triangle
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lda #$0600
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jsr copy_noise
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; lda #$8000
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; jsr gen_noise
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rts
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;--------------------------
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setup_docram
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sep #$20
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mx %10
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jsr access_doc_ram
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stz sound_address
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lda #$80
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ldx #256 ;make sure that page 00 has nonzero data for interrupt
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:loop sta sound_data
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dex
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bne :loop
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rep #$20
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mx %00
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rts
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;--------------------------
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make_eigth_pulse
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ldy #32
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jmp make_pulse
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make_quarter_pulse
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ldy #64
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jmp make_pulse
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make_half_pulse
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ldy #128
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jmp make_pulse
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make_inv_quarter_pulse
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ldy #192
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jmp make_pulse
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make_pulse
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sep #$30
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mx %11
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stz sound_address
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xba
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sta sound_address+1
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ldx #0
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:loop1
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lda #$01
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sta sound_data
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inx
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dey
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bne :loop1
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:loop2
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lda #$FF
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sta sound_data
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inx
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bne :loop2
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rep #$30
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mx %00
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rts
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copy_triangle
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sep #$30
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mx %11
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stz sound_address
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xba
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sta sound_address+1
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ldx #0
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:loop
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lda triangle_wave,x
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sta sound_data
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inx
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bne :loop
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rep #$30
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mx %00
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rts
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; Generate random data from the NES APU LFSR. Make it long enough to sound good.
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gen_noise
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copy_noise
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sep #$30
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mx %11
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stz sound_address
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xba
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sta sound_address+1
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ldx #0
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:loop
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lda noise_wave,x
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sta sound_data
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inx
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bne :loop
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rep #$30
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mx %00
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rts
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;--------------------------
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triangle_wave
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hex 80828486888a8c8e90929496989a9c9e
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hex a0a2a4a6a8aaacaeb0b2b4b6b8babcbe
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hex c0c1c3c5c7c9cbcdcfd1d3d5d7d9dbdd
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hex dfe1e3e5e7e9ebedeff1f3f5f7f9fbfd
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hex fffdfbf9f7f5f3f1efedebe9e7e5e3e1
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hex dfdddbd9d7d5d3d1cfcdcbc9c7c5c3c1
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hex c0bebcbab8b6b4b2b0aeacaaa8a6a4a2
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hex a09e9c9a98969492908e8c8a88868482
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hex 807e7c7a78767472706e6c6a68666462
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hex 605e5c5a58565452504e4c4a48464442
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hex 413f3d3b39373533312f2d2b29272523
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hex 211f1d1b19171513110f0d0b09070503
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hex 01030507090b0d0f11131517191b1d1f
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hex 21232527292b2d2f31333537393b3d3f
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hex 41424446484a4c4e50525456585a5c5e
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hex 60626466686a6c6e70727476787a7c7e
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noise_wave
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hex 8f968f763e6fd49ab1e564e295a9bcc9
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hex 717b6629e6970b865dc0e0d840d32a96
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hex 3bd4c5d407b78923d8c9766bea128e8a
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hex c9ee5ddbed3119ff14b4d9a44bfbb7c4
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hex 7a56e26e8aac9ebf1653c0260446231b
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hex 73431495fc585e943edacf8f5bb970e6
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hex 118dc361bee99c98f32d25f06a33715a
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hex 585344f7f3e2f3c36c37cfd78e40147f
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hex a4b20624ac633b42b3aac5407fac4ba9
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hex a4d71a1d020a7757ea244b103f0b7a76
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hex 9b533a60cda31e0fa2ce3491b55c4f26
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hex ea47a61f661deec128129372c3471a9b
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hex f85c3c077168d413184a139440460950
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hex dee3f9bdb65e162b08ed9231a72fb943
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hex 1ba599be80dc2812afa63cc2317cdb1a
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hex 8d99d56327bc50dc975bee94754f561b
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; hex 01ffffff0101ffffff01ffff01ff0101
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; hex ffffffffffff0101ff0101ff01ffff01
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; hex 01ff0101ffff01ffff0101ff01ff01ff
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; hex ffffffff0101010101ffff0101ff0101
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; hex ffffff0101ff01ff010101ff01010101
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; hex 0101ffffff01ffff01ff01ffff01ffff
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; hex ff01ffff0101ffff01ffffffffff01ff
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; hex ffffffffffff010101ffff01ff01ffff
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; hex 01ffffffff0101ffffffff0101ffff01
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; hex ff01ff01ff01ffff0101ff01ffffffff
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; hex ffff010101ffffffff01010101ff0101
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; hex ffffffffffffff01ff0101ffffff0101
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; hex 01ff010101ff01ffffffffff01ffffff
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; hex 01ffffffff010101ff01ffff01ff01ff
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; hex ffffffff0101ff010101ff01ffffff01
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; hex 0101010101ffff01ffff01010101ffff
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;--------------------------
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setup_doc_registers
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sep #$20
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mx %10
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jsr access_doc_registers
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ldx #pulse1_sound_settings
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jsr copy_register_config
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ldx #pulse2_sound_settings
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jsr copy_register_config
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ldx #triangle_sound_settings
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jsr copy_register_config
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ldx #noise_sound_settings
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jsr copy_register_config
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rep #$20
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mx %00
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rts
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copy_register_config
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ldy #0
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:loop lda: 0,x ; Set DOC registers for the NES channels
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sta sound_address
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inx
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lda: 0,x
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sta sound_data
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inx
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iny
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cpy #6 ; 6 pairs to describe this oscillator
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bne :loop
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rts
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;--------------------------
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setup_interrupt = *
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ldal apu_mode
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cmp #2 ; mode 2 = external driver at 60Hz
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beq :no_doc_interrupts
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ldal sound_interrupt_ptr
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sta backup_interrupt_ptr
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ldal sound_interrupt_ptr+2
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sta backup_interrupt_ptr+2
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lda #$5c
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stal sound_interrupt_ptr
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phk
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phk
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pla
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stal sound_interrupt_ptr+2
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lda #interrupt_handler
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stal sound_interrupt_ptr+1
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sep #$20
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mx %10
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ldal apu_mode
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beq :do_240hz
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lda #598
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ldy #598/256
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bra :set_timer_freq
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:do_240hz lda #1195
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ldy #1195/256
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:set_timer_freq
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stal timer_sound_settings+1 ; low byte of timer frequency
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tya
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stal timer_sound_settings+3 ; high byte of timer frequency
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jsr access_doc_registers
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ldy #0
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:loop lda timer_sound_settings,y ; Set DOC registers for the interrupt oscillator
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sta sound_address
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iny
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lda timer_sound_settings,y
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sta sound_data
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iny
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cpy #7*2
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bne :loop
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rep #$20
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mx %00
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:no_doc_interrupts
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rts
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interrupt_oscillator = 31
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;reference_freq = 299 ; interrupt frequence (60Hz)
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;reference_freq = 598 ; interrupt frequence (120Hz)
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reference_freq = 1195 ; interrupt frequence (240Hz)
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timer_sound_settings = * ; set up oscillator 30 for interrupts
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dfb $00+interrupt_oscillator,reference_freq ; frequency low register
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dfb $20+interrupt_oscillator,reference_freq/256 ; frequency high register
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dfb $40+interrupt_oscillator,0 ; volume register, volume = 0
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dfb $80+interrupt_oscillator,0 ; wavetable pointer register, point to 0
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dfb $c0+interrupt_oscillator,0 ; wavetable size register, 256 byte length
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dfb $e1,$3e ; oscillator enable register
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dfb $a0+interrupt_oscillator,$08 ; mode register, set to free run
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pulse1_oscillator = 0
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pulse2_oscillator = 2
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triangle_oscillator = 4
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noise_oscillator = 6
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default_freq = 800
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pulse1_sound_settings = *
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dfb $00+pulse1_oscillator,default_freq ; frequency low register
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dfb $20+pulse1_oscillator,default_freq/256 ; frequency high register
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dfb $40+pulse1_oscillator,0 ; volume register, volume = 0
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dfb $80+pulse1_oscillator,3 ; wavetable pointer register, point to $0300 by default (50% duty cycle)
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dfb $c0+pulse1_oscillator,0 ; wavetable size register, 256 byte length
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dfb $a0+pulse1_oscillator,0 ; mode register, set to free run
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pulse2_sound_settings = *
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dfb $00+pulse2_oscillator,default_freq ; frequency low register
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dfb $20+pulse2_oscillator,default_freq/256 ; frequency high register
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dfb $40+pulse2_oscillator,0 ; volume register, volume = 0
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dfb $80+pulse2_oscillator,3 ; wavetable pointer register, point to $0300 by default (50% duty cycle)
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dfb $c0+pulse2_oscillator,0 ; wavetable size register, 256 byte length
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dfb $a0+pulse2_oscillator,0 ; mode register, set to free run
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triangle_sound_settings = *
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dfb $00+triangle_oscillator,default_freq ; frequency low register
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dfb $20+triangle_oscillator,default_freq/256 ; frequency high register
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dfb $40+triangle_oscillator,0 ; volume register, volume = 0
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dfb $80+triangle_oscillator,5 ; wavetable pointer register, point to $0500
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dfb $c0+triangle_oscillator,0 ; wavetable size register, 256 byte length
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dfb $a0+triangle_oscillator,0 ; mode register, set to free run
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noise_sound_settings = *
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dfb $00+noise_oscillator,default_freq ; frequency low register
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dfb $20+noise_oscillator,default_freq/256 ; frequency high register
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dfb $40+noise_oscillator,128 ; volume register, volume = 0
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dfb $80+noise_oscillator,6 ; wavetable pointer register, point to $0600
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dfb $c0+noise_oscillator,0 ; wavetable size register, 256 byte length
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dfb $a0+noise_oscillator,0 ; mode register, set to free run
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backup_interrupt_ptr ds 4
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apu_mode ds 2
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;-----------------------------------------------------------------------------------------
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; APU internals
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;-----------------------------------------------------------------------------------------
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mx %11
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clock_length_counter mac
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lda ]1+{APU_PULSE1_REG1-APU_PULSE1}
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bit ]2
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bne no_count
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lda ]1+{APU_PULSE1_LENGTH_COUNTER-APU_PULSE1}
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beq no_count
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dec
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sta ]1+{APU_PULSE1_LENGTH_COUNTER-APU_PULSE1}
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no_count <<<
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|
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clock_linear_counter mac
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lda ]1+{APU_TRIANGLE_START_FLAG-APU_TRIANGLE}
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beq do_clock
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lda ]1+{APU_TRIANGLE_REG1-APU_TRIANGLE}
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|
and #$7F
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sta ]1+{APU_TRIANGLE_LINEAR_COUNTER-APU_TRIANGLE}
|
|
bra check_reset
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|
|
|
do_clock lda ]1+{APU_TRIANGLE_LINEAR_COUNTER-APU_TRIANGLE}
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beq check_reset
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|
dec
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sta ]1+{APU_TRIANGLE_LINEAR_COUNTER-APU_TRIANGLE}
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|
|
|
check_reset
|
|
lda ]1+{APU_TRIANGLE_REG1-APU_TRIANGLE}
|
|
bmi no_reset
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|
stz ]1+{APU_TRIANGLE_START_FLAG-APU_TRIANGLE}
|
|
no_reset <<<
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|
|
|
clock_sweep mac
|
|
lda ]1+{APU_PULSE1_SWEEP_DIVIDER-APU_PULSE1}
|
|
dec
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|
sta ]1+{APU_PULSE1_SWEEP_DIVIDER-APU_PULSE1}
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bpl no_sweep
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|
|
|
lda #1
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sta ]1+{APU_PULSE1_RELOAD_FLAG-APU_PULSE1}
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|
|
|
lda ]1+{APU_PULSE1_REG2-APU_PULSE1} ; get the barrel shift argument from the register
|
|
bpl no_sweep ; if sweep is not enabled, do nothing
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and #$07
|
|
beq no_sweep ; shift must be != 0
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|
asl
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|
tax
|
|
|
|
lda ]1+{APU_PULSE1_REG2-APU_PULSE1} ; put the negate flag in the y register
|
|
and #$08
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|
tay
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|
|
|
rep #$20
|
|
lda ]1+{APU_PULSE1_CURRENT_PERIOD-APU_PULSE1}
|
|
cmp #8
|
|
bcc no_sweep0 ; current period must be >= 8
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|
jmp (bitshift,x) ; shift it by the shifter amount
|
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bitshift da bitshift_0,bitshift_1,bitshift_2,bitshift_3,bitshift_4,bitshift_5,bitshift_6,bitshift_7
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|
bitshift_7 lsr
|
|
bitshift_6 lsr
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|
bitshift_5 lsr
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|
bitshift_4 lsr
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|
bitshift_3 lsr
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|
bitshift_2 lsr
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|
bitshift_1 lsr
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|
bitshift_0
|
|
cpy #0 ; check if the negate flag was set
|
|
beq no_negate
|
|
eor #$FFFF ; pulse 1 uses 1's complement
|
|
DO ]2
|
|
inc
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|
FIN
|
|
no_negate clc
|
|
adc ]1+{APU_PULSE1_CURRENT_PERIOD-APU_PULSE1}
|
|
cmp #$800
|
|
bcs no_sweep0
|
|
sta ]1+{APU_PULSE1_CURRENT_PERIOD-APU_PULSE1}
|
|
no_sweep0
|
|
sep #$20
|
|
no_sweep
|
|
lda ]1+{APU_PULSE1_RELOAD_FLAG-APU_PULSE1} ; check if we need to reload the sweep delay
|
|
beq no_reload
|
|
stz ]1+{APU_PULSE1_RELOAD_FLAG-APU_PULSE1}
|
|
lda ]1+{APU_PULSE1_REG2-APU_PULSE1}
|
|
lsr
|
|
lsr
|
|
lsr
|
|
lsr
|
|
and #7
|
|
sta ]1+{APU_PULSE1_SWEEP_DIVIDER-APU_PULSE1}
|
|
no_reload <<<
|
|
|
|
clock_envelope mac
|
|
lda ]1+{APU_PULSE1_START_FLAG-APU_PULSE1}
|
|
beq no_start
|
|
stz ]1+{APU_PULSE1_START_FLAG-APU_PULSE1} ; clear the start flag
|
|
lda #15
|
|
sta ]1+{APU_PULSE1_ENVELOPE-APU_PULSE1} ; reset the envelope saw wave decay value
|
|
lda ]1+{APU_PULSE1_REG1-APU_PULSE1}
|
|
and #$0F
|
|
sta ]1+{APU_PULSE1_ENVELOPE_DIVIDER-APU_PULSE1} ; reset the divider value
|
|
bra envelope_out ; nothing else to do
|
|
|
|
no_start
|
|
lda ]1+{APU_PULSE1_ENVELOPE_DIVIDER-APU_PULSE1} ; clock the divider
|
|
dec
|
|
sta ]1+{APU_PULSE1_ENVELOPE_DIVIDER-APU_PULSE1}
|
|
bpl envelope_out ; as long as divider is >=0, nothing to do
|
|
|
|
lda ]1+{APU_PULSE1_REG1-APU_PULSE1} ; reset the divider to the volume/envelope value
|
|
and #$0F
|
|
sta ]1+{APU_PULSE1_ENVELOPE_DIVIDER-APU_PULSE1}
|
|
|
|
lda ]1+{APU_PULSE1_ENVELOPE-APU_PULSE1}
|
|
bne tick_envelope
|
|
|
|
lda ]1+{APU_PULSE1_REG1-APU_PULSE1} ; if decay level counter is 0, check the loop bit and set counter to 15 if loop bit is set
|
|
bit #PULSE_HALT_FLAG
|
|
beq envelope_out
|
|
lda #16 ; Set to 15
|
|
tick_envelope
|
|
dec
|
|
sta ]1+{APU_PULSE1_ENVELOPE-APU_PULSE1}
|
|
envelope_out <<<
|
|
|
|
half_frame_clock
|
|
; clock the length counters
|
|
clock_length_counter APU_PULSE1;#PULSE_HALT_FLAG
|
|
clock_length_counter APU_PULSE2;#PULSE_HALT_FLAG
|
|
clock_length_counter APU_TRIANGLE;#TRIANGLE_HALT_FLAG
|
|
clock_length_counter APU_NOISE;#NOISE_HALT_FLAG
|
|
|
|
; clock the sweep units
|
|
clock_sweep APU_PULSE1;0
|
|
clock_sweep APU_PULSE2;1
|
|
rts
|
|
|
|
quarter_frame_clock
|
|
; clock the envelopes and triangle linear counter
|
|
clock_linear_counter APU_TRIANGLE
|
|
|
|
clock_envelope APU_PULSE1
|
|
clock_envelope APU_PULSE2
|
|
clock_envelope APU_NOISE
|
|
rts
|
|
|
|
;-----------------------------------------------------------------------------------------
|
|
; interupt handler
|
|
;-----------------------------------------------------------------------------------------
|
|
|
|
apu_frame_steps equ 5
|
|
PULSE_HALT_FLAG equ $20
|
|
NOISE_HALT_FLAG equ $20 ; noise and pulse channels have halt flagin same bit position in REG1
|
|
PULSE_CONST_VOL_FLAG equ $10
|
|
NOISE_CONST_VOL_FLAG equ $10
|
|
TRIANGLE_HALT_FLAG equ $80
|
|
|
|
mx %11
|
|
quarter_speed_driver = *
|
|
|
|
phb
|
|
phd
|
|
|
|
phk
|
|
plb
|
|
|
|
pea $c000
|
|
pld
|
|
|
|
ldx apu_frame_counter
|
|
inx
|
|
inx
|
|
cpx #2*apu_frame_steps ; TODO: This is set by MSB in $4017 (4 or 5). 4 = PAL, 5 = NTSC.
|
|
bcc *+4
|
|
ldx #0
|
|
stx apu_frame_counter
|
|
jmp (:frame_counter_proc,x)
|
|
:frame_counter_proc da :quarter_frame,:half_frame,:quarter_frame,:no_frame_60,:half_frame
|
|
|
|
; Quarter-speed interrupts (60Hz) -- clock four times in each handler
|
|
:half_frame
|
|
:quarter_frame
|
|
jsr half_frame_clock
|
|
jsr quarter_frame_clock
|
|
jsr quarter_frame_clock
|
|
jsr half_frame_clock
|
|
jsr quarter_frame_clock
|
|
jsr quarter_frame_clock
|
|
|
|
brl update_doc_registers
|
|
:no_frame_60
|
|
pld
|
|
plb
|
|
clc
|
|
rtl
|
|
|
|
mx %11
|
|
interrupt_handler = *
|
|
|
|
ldal show_border
|
|
beq :no_show
|
|
ldal $E0C034 ; save the border color
|
|
stal border_color
|
|
lda #1
|
|
jsr setborder
|
|
:no_show
|
|
|
|
phb
|
|
phd
|
|
|
|
phk
|
|
plb
|
|
|
|
clc
|
|
xce
|
|
|
|
pea $c000
|
|
pld
|
|
|
|
; Make sure it's the oscillator we care about
|
|
|
|
ldal osc_interrupt ; which oscillator generated the interrupt?
|
|
and #%00111110
|
|
cmp #2*interrupt_oscillator
|
|
beq *+5
|
|
brl :not_timer ; Only service timer interrupts
|
|
|
|
; Update the frame counter and leave the doubled countin x-register for dispatch
|
|
ldx apu_frame_counter
|
|
inx
|
|
inx
|
|
cpx #2*apu_frame_steps ; TODO: This is set by MSB in $4017 (4 or 5). 4 = PAL, 5 = NTSC.
|
|
bcc *+4
|
|
ldx #0
|
|
stx apu_frame_counter
|
|
|
|
; Figure out which speed we are dispatching
|
|
lda apu_mode
|
|
beq :do_240hz_mode
|
|
jmp (:apu_120hz_table,x)
|
|
:do_240hz_mode jmp (:apu_240hz_table,x)
|
|
:apu_240hz_table da :quarter_frame_240,:half_frame_240,:quarter_frame_240,no_frame,:half_frame_240
|
|
:apu_120hz_table da :quarter_frame_120,:half_frame_120,:quarter_frame_120,no_frame,:half_frame_120
|
|
|
|
; Full speed emulation (240Hz)
|
|
:half_frame_240 jsr half_frame_clock
|
|
:quarter_frame_240 jsr quarter_frame_clock
|
|
bra update_doc_registers
|
|
|
|
; Half-speed interrupts (120Hz) -- clock twice in each handler
|
|
:half_frame_120
|
|
:quarter_frame_120
|
|
jsr half_frame_clock
|
|
jsr quarter_frame_clock
|
|
jsr quarter_frame_clock
|
|
|
|
; Apply any changes to the DOC registers
|
|
update_doc_registers
|
|
|
|
jsr access_doc_registers
|
|
|
|
; Set the parameters for the first square wave channel.
|
|
;
|
|
; First, set the frequency, if the period is <8 then the pulse channel is muted,
|
|
; to test that first
|
|
lda APU_PULSE1_MUTE ; If the sweep muted the channel, no output
|
|
bne :mute_pulse1
|
|
lda APU_PULSE1_LENGTH_COUNTER ; If the length counter is zero, no output
|
|
beq :mute_pulse1
|
|
rep #$30
|
|
lda APU_PULSE1_CURRENT_PERIOD
|
|
cmp #8
|
|
bcc :mute_pulse1
|
|
|
|
cmp _apu_pulse1_last_period ; it's expensive to recalc frequencies, so avoid it when possible
|
|
beq :freq_end_pulse1
|
|
sta _apu_pulse1_last_period
|
|
jsr get_pulse_freq ; return freq in 16-bit accumulator
|
|
sep #$30
|
|
ldx #$00+pulse1_oscillator
|
|
stx sound_address
|
|
sta sound_data
|
|
ldx #$20+pulse1_oscillator
|
|
stx sound_address
|
|
xba
|
|
sta sound_data
|
|
:freq_end_pulse1 sep #$30 ; redundent, but avoids extra branches
|
|
|
|
lda #$80+pulse1_oscillator
|
|
sta sound_address
|
|
lda APU_PULSE1_REG1 ; Get the cycle duty bits
|
|
jsr set_pulse_duty_cycle
|
|
|
|
lda #$40+pulse1_oscillator
|
|
sta sound_address
|
|
lda APU_PULSE1_REG1
|
|
bit #PULSE_CONST_VOL_FLAG ; Check the constant volume bit
|
|
bne :set_volume_pulse1
|
|
lda APU_PULSE1_ENVELOPE
|
|
bra :set_volume_pulse1
|
|
|
|
:mute_pulse1
|
|
sep #$30
|
|
lda #$40+pulse1_oscillator
|
|
sta sound_address
|
|
lda #0
|
|
:set_volume_pulse1 jsr set_pulse_volume
|
|
|
|
; Now do the second square wave
|
|
lda APU_PULSE2_MUTE ; If the sweep muted the channel, no output
|
|
bne :mute_pulse2
|
|
lda APU_PULSE2_LENGTH_COUNTER ; If the length counter is zero, no output
|
|
beq :mute_pulse2
|
|
rep #$30
|
|
lda APU_PULSE2_CURRENT_PERIOD
|
|
cmp #8
|
|
bcc :mute_pulse2
|
|
|
|
cmp _apu_pulse2_last_period
|
|
beq :freq_end_pulse2
|
|
sta _apu_pulse2_last_period
|
|
jsr get_pulse_freq ; return freq in 16-bic accumulator
|
|
sep #$30
|
|
ldx #$00+pulse2_oscillator
|
|
stx sound_address
|
|
sta sound_data
|
|
ldx #$20+pulse2_oscillator
|
|
stx sound_address
|
|
xba
|
|
sta sound_data
|
|
:freq_end_pulse2 sep #$30
|
|
|
|
lda #$80+pulse2_oscillator
|
|
sta sound_address
|
|
lda APU_PULSE2_REG1 ; Get the cycle duty bits
|
|
jsr set_pulse_duty_cycle
|
|
|
|
lda #$40+pulse2_oscillator
|
|
sta sound_address
|
|
lda APU_PULSE2_REG1
|
|
bit #PULSE_CONST_VOL_FLAG ; Check the constant volume bit
|
|
bne :set_volume_pulse2
|
|
lda APU_PULSE2_ENVELOPE
|
|
bra :set_volume_pulse2
|
|
:mute_pulse2
|
|
sep #$30
|
|
lda #$40+pulse2_oscillator
|
|
sta sound_address
|
|
lda #0
|
|
:set_volume_pulse2 jsr set_pulse_volume
|
|
|
|
; Now the triangle wave. This wave needs linear counter support to be silenced
|
|
|
|
lda APU_TRIANGLE_LENGTH_COUNTER ; If the length counter is zero, no output
|
|
beq :mute_triangle
|
|
lda APU_TRIANGLE_LINEAR_COUNTER ; If the linear counter is zero, no output
|
|
beq :mute_triangle
|
|
rep #$30
|
|
lda APU_TRIANGLE_CURRENT_PERIOD
|
|
cmp #2
|
|
bcc :mute_triangle
|
|
|
|
; NOTE on Triangle channel frequence from https://www.nesdev.org/wiki/APU_Triangle
|
|
;
|
|
; Unlike the pulse channels, the triangle channel supports frequencies up to the maximum frequency the
|
|
; timer will allow, meaning frequencies up to fCPU/32 (about 55.9 kHz for NTSC) are possible - far above
|
|
; the audible range. Some games, e.g. Mega Man 2, "silence" the triangle channel by setting the timer to
|
|
; zero, which produces a popping sound when an audible frequency is resumed, easily heard e.g. in Crash
|
|
; Man's stage. At the expense of accuracy, these can be eliminated in an emulator e.g. by halting the
|
|
; triangle channel when an ultrasonic frequency is set (a timer value less than 2).
|
|
|
|
cmp _apu_triangle_last_period
|
|
beq :freq_end_triangle
|
|
sta _apu_triangle_last_period
|
|
jsr get_pulse_freq ; return freq in 16-bic accumulator
|
|
lsr
|
|
sep #$30
|
|
ldx #$00+triangle_oscillator
|
|
stx sound_address
|
|
sta sound_data
|
|
ldx #$20+triangle_oscillator
|
|
stx sound_address
|
|
xba
|
|
sta sound_data
|
|
:freq_end_triangle sep #$30
|
|
|
|
lda #$40+triangle_oscillator
|
|
sta sound_address
|
|
lda #12 ; Triangle is a bit softer than pulse channels
|
|
bra :set_volume_triangle
|
|
|
|
:mute_triangle
|
|
sep #$30
|
|
lda #$40+triangle_oscillator
|
|
sta sound_address
|
|
lda #0
|
|
:set_volume_triangle jsr set_pulse_volume
|
|
|
|
; Now the noise channel. It's mixer volume output is ~half of the pulse channels
|
|
|
|
lda APU_NOISE_LENGTH_COUNTER ; If the length counter is zero, no output
|
|
beq :mute_noise
|
|
|
|
ldx #$00+noise_oscillator
|
|
stx sound_address
|
|
lda APU_NOISE_CURRENT_PERIOD
|
|
sta sound_data
|
|
ldx #$20+noise_oscillator
|
|
stx sound_address
|
|
lda APU_NOISE_CURRENT_PERIOD+1
|
|
sta sound_data
|
|
|
|
lda #$40+noise_oscillator
|
|
sta sound_address
|
|
lda APU_NOISE_REG1
|
|
bit #NOISE_CONST_VOL_FLAG ; Check the constant volume bit
|
|
bne :set_volume_noise
|
|
lda APU_NOISE_ENVELOPE
|
|
bra :set_volume_noise
|
|
:mute_noise
|
|
lda #$40+noise_oscillator
|
|
sta sound_address
|
|
lda #0
|
|
:set_volume_noise
|
|
and #$0F
|
|
asl
|
|
asl
|
|
asl
|
|
pha
|
|
lda APU_NOISE_REG3 ; Up the volume for low sounds
|
|
bit #$08
|
|
beq :high_pitch
|
|
pla
|
|
asl
|
|
pha
|
|
:high_pitch pla
|
|
sta sound_data
|
|
|
|
:not_timer
|
|
no_frame
|
|
ldal show_border
|
|
beq :no_show2
|
|
ldal border_color
|
|
jsr setborder
|
|
:no_show2
|
|
|
|
pld
|
|
plb
|
|
clc
|
|
rtl
|
|
|
|
set_pulse_duty_cycle
|
|
mx %11
|
|
rol
|
|
rol
|
|
rol
|
|
and #$03
|
|
tax
|
|
|
|
lda duty_cycle_page,x
|
|
sta sound_data
|
|
rts
|
|
|
|
set_pulse_volume
|
|
and #$0F
|
|
asl
|
|
asl
|
|
asl
|
|
asl
|
|
sta sound_data
|
|
rts
|
|
|
|
; This is a bit different because we actually calculate a scan rate directly to match the
|
|
; rate at which new samples are read form DOC RAM to the period of the noise channel
|
|
;
|
|
; IIgs Scan Rate (SR) = 894886 Hz / (OSC + 2) = 894886 Hz / 34 = 26320.1765 samples / sec
|
|
; IIgs Sample Rate = 51.406 * F_HL samples / sec
|
|
|
|
; We have 256 samples
|
|
; NES Noise Sample Rate = 1789772 Hz / P
|
|
;
|
|
; An as example, let P = 8, so a new sample should be output
|
|
; Solving for F_HL: F_HL = 1789772 / (51.406 * 8) = 4352
|
|
get_noise_freq
|
|
|
|
|
|
; NES freq = f_CPU / (16 * (t + 1))
|
|
; = 1.789773 MHz / (16 * (t + 1))
|
|
; = 111860.812 Hz / (t + 1)
|
|
;
|
|
; IIgs freq = 0.200807 * F_HL (for 32 oscillators with DOC RES = 0)
|
|
;
|
|
; Solving for F_HL = (1 / 0.200807) * 111860.812 / (t + 1)
|
|
; = 557056.338 / (t + 1)
|
|
;
|
|
; if t < 8 this value is out of range and the oscillator should be silenced
|
|
;
|
|
; otherwise, break apart the ratio
|
|
;
|
|
; f_HL = 10 * (55706 / (t + 1))
|
|
;
|
|
get_pulse_freq
|
|
mx %00
|
|
and #$7FF ; prevent overflow...
|
|
inc
|
|
sta divisor
|
|
lda #55706
|
|
sta dividend
|
|
|
|
lda #0
|
|
ldx #16 ; 16 bits of division
|
|
asl dividend
|
|
:dl1 rol
|
|
cmp divisor
|
|
bcc :dl2
|
|
sbc divisor
|
|
:dl2 rol dividend
|
|
dex
|
|
bne :dl1
|
|
|
|
lda dividend
|
|
sta dividend
|
|
asl
|
|
asl
|
|
clc
|
|
adc dividend ; multiple by 10 to get the DOC value
|
|
asl
|
|
rts
|
|
|
|
turn_off_interrupts
|
|
php
|
|
sep #$20
|
|
lda #$a0+interrupt_oscillator
|
|
sta sound_address
|
|
lda #0
|
|
sta sound_data
|
|
plp
|
|
rts
|
|
|
|
; Internal APU registers.
|
|
;
|
|
; These variables track the internal flags, counters and other status bits that make up
|
|
; the core functionality of the different channel hardware
|
|
|
|
apu_frame_counter dw 0 ; frame counter, clocked at 240Hz from the interrupt handler
|
|
|
|
duty_cycle_page dfb $01,$02,$03,$04 ; Page of DOC RAM that holds the different duty cycle wavforms
|
|
show_border dw 0
|
|
border_color dw 0
|
|
dividend dw 0 ; Used when converting from NES APU values to DOC values
|
|
divisor dw 0
|
|
|
|
; Pulse Channel 1
|
|
APU_PULSE1
|
|
APU_PULSE1_REG1 ds 1 ; DDLC NNNN - Duty, length counter halt, constant volume/evelope, envelope period/volume
|
|
APU_PULSE1_REG2 ds 1 ; EPPP NSSS - Sweep unit: enabled, period, negative, shift count
|
|
APU_PULSE1_REG3 ds 1 ; LLLL LLLL - Timer Low
|
|
APU_PULSE1_REG4 ds 1 ; llll lHHH - Length counter load, timer high (also resets duty and starts envelope)
|
|
|
|
APU_PULSE1_LENGTH_COUNTER dfb 0 ; internal register for the length counter
|
|
APU_PULSE1_RELOAD_FLAG dfb 0 ; internal register to reload the sweep divider value
|
|
APU_PULSE1_SWEEP_DIVIDER dfb 0 ; internal register to track the sweep divider value
|
|
APU_PULSE1_TARGET_PERIOD dw 0 ; internal register to hold the sweep unit target period
|
|
APU_PULSE1_CURRENT_PERIOD dw 0 ; internal register to hold the current period driving the oscillator
|
|
APU_PULSE1_MUTE dfb 0
|
|
APU_PULSE1_START_FLAG dfb 0
|
|
APU_PULSE1_ENVELOPE_DIVIDER dfb 0
|
|
APU_PULSE1_ENVELOPE dfb 0
|
|
|
|
_apu_pulse1_last_period dw $FFFF ; optimization
|
|
|
|
|
|
APU_PULSE2
|
|
APU_PULSE2_REG1 ds 1 ; DDLC NNNN - Duty, length counter halt, constant volume/evelope, envelope period/volume
|
|
APU_PULSE2_REG2 ds 1 ; EPPP NSSS - Sweep unit: enabled, period, negative, shift count
|
|
APU_PULSE2_REG3 ds 1 ; LLLL LLLL - Timer Low
|
|
APU_PULSE2_REG4 ds 1 ; llll lHHH - Length counter load, timer high (also resets duty and starts envelope)
|
|
|
|
APU_PULSE2_LENGTH_COUNTER dfb 0 ; internal register for the length counter
|
|
APU_PULSE2_RELOAD_FLAG dfb 0 ; internal register to reload the sweep divider value
|
|
APU_PULSE2_SWEEP_DIVIDER dfb 0 ; internal register to track the sweep divider value
|
|
APU_PULSE2_TARGET_PERIOD dw 0 ; internal register to hold the sweep unit target period
|
|
APU_PULSE2_CURRENT_PERIOD dw 0 ; internal register to hold the current period driving the oscillator
|
|
APU_PULSE2_MUTE dfb 0
|
|
APU_PULSE2_START_FLAG dfb 0
|
|
APU_PULSE2_ENVELOPE_DIVIDER dfb 0
|
|
APU_PULSE2_ENVELOPE dfb 0
|
|
|
|
_apu_pulse2_last_period dw $FFFF ; optimization
|
|
|
|
|
|
APU_TRIANGLE
|
|
APU_TRIANGLE_REG1 ds 1 ; DDLC NNNN - Duty, loop envelope/disable length counter, constant volume, envelope period/volume
|
|
APU_TRIANGLE_REG2 ds 1 ; EPPP NSSS - Sweep unit: enabled, period, negative, shift count
|
|
APU_TRIANGLE_REG3 ds 1 ; LLLL LLLL - Timer Low
|
|
APU_TRIANGLE_REG4 ds 1 ; llll lHHH - Length counter load, timer high (also resets duty and starts envelope)
|
|
|
|
APU_TRIANGLE_LENGTH_COUNTER dfb 0
|
|
APU_TRIANGLE_CURRENT_PERIOD dw 0
|
|
APU_TRIANGLE_START_FLAG dfb 0
|
|
APU_TRIANGLE_LINEAR_COUNTER dfb 0
|
|
|
|
_apu_triangle_last_period dw $FFFF ; optimization
|
|
|
|
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APU_NOISE
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APU_NOISE_REG1 ds 1 ; --LC NNNN - length counter halt, constant volume/evelope, envelope period/volume
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APU_NOISE_REG2 ds 1 ; ---- ---- - Unused
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APU_NOISE_REG3 ds 1 ; M--- PPPP - Mode and period lookup
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APU_NOISE_REG4 ds 1 ; llll l--- - Length counter load
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APU_NOISE_LENGTH_COUNTER dfb 0 ; internal register for the length counter
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APU_NOISE_RELOAD_FLAG dfb 0 ; unused
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APU_NOISE_SWEEP_DIVIDER dfb 0 ; unused
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APU_NOISE_TARGET_PERIOD dw 0 ; unused
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APU_NOISE_CURRENT_PERIOD dw 0 ; internal register to hold the current period driving the oscillator
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APU_NOISE_MUTE dfb 0 ; unused
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APU_NOISE_START_FLAG dfb 0
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APU_NOISE_ENVELOPE_DIVIDER dfb 0
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APU_NOISE_ENVELOPE dfb 0
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_apu_noise_last_period dw $FFFF ; optimization
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APU_STATUS ds 1
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mx %11
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APU_PULSE1_REG1_WRITE ENT
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stal APU_PULSE1_REG1
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rtl
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APU_PULSE1_REG2_WRITE ENT
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php
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pha
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stal APU_PULSE1_REG2
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lda #1
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stal APU_PULSE1_RELOAD_FLAG ; mark that this register was written to
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pla
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plp
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rtl
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APU_PULSE1_REG3_WRITE ENT
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stal APU_PULSE1_CURRENT_PERIOD
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stal APU_PULSE1_REG3
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rtl
|
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APU_PULSE1_REG4_WRITE ENT
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php
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phx
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pha
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stal APU_PULSE1_REG4
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and #$07
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stal APU_PULSE1_CURRENT_PERIOD+1
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; If the APU_STATUS bit is enabled, then load the length counter
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ldal APU_STATUS
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bit #$01
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beq :no_reload
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ldal APU_PULSE1_REG4
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and #$F8
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lsr
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lsr
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lsr
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tax
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ldal LengthTable,x
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stal APU_PULSE1_LENGTH_COUNTER ; Immediately start the counter
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lda #1
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stal APU_PULSE1_START_FLAG
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:no_reload
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pla
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plx
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plp
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rtl
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; From https://www.nesdev.org/wiki/APU_Length_Counter
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LengthTable
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db 10,254, 20, 2, 40, 4, 80, 6, 160, 8, 60, 10, 14, 12, 26, 14
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db 12, 16, 24, 18, 48, 20, 96, 22, 192, 24, 72, 26, 16, 28, 32, 30
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APU_PULSE2_REG1_WRITE ENT
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stal APU_PULSE2_REG1
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rtl
|
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APU_PULSE2_REG2_WRITE ENT
|
|
php
|
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pha
|
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stal APU_PULSE2_REG2
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lda #1
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stal APU_PULSE2_RELOAD_FLAG
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pla
|
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plp
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|
rtl
|
|
|
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APU_PULSE2_REG3_WRITE ENT
|
|
stal APU_PULSE2_CURRENT_PERIOD
|
|
stal APU_PULSE2_REG3
|
|
rtl
|
|
|
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APU_PULSE2_REG4_WRITE ENT
|
|
php
|
|
phx
|
|
pha
|
|
|
|
stal APU_PULSE2_REG4
|
|
and #$07
|
|
stal APU_PULSE2_CURRENT_PERIOD+1
|
|
|
|
ldal APU_STATUS
|
|
bit #$02
|
|
beq :no_reload
|
|
|
|
ldal APU_PULSE2_REG4
|
|
and #$F8
|
|
lsr
|
|
lsr
|
|
lsr
|
|
tax
|
|
ldal LengthTable,x
|
|
stal APU_PULSE2_LENGTH_COUNTER ; Immediately start the counter
|
|
lda #1
|
|
stal APU_PULSE2_START_FLAG
|
|
|
|
:no_reload
|
|
pla
|
|
plx
|
|
plp
|
|
rtl
|
|
|
|
|
|
APU_TRIANGLE_REG1_WRITE ENT
|
|
stal APU_TRIANGLE_REG1
|
|
rtl
|
|
|
|
APU_TRIANGLE_REG2_WRITE ENT
|
|
stal APU_TRIANGLE_REG2
|
|
rtl
|
|
|
|
APU_TRIANGLE_REG3_WRITE ENT
|
|
stal APU_TRIANGLE_CURRENT_PERIOD
|
|
stal APU_TRIANGLE_REG3
|
|
rtl
|
|
|
|
APU_TRIANGLE_REG4_WRITE ENT
|
|
php
|
|
phx
|
|
pha
|
|
|
|
stal APU_TRIANGLE_REG4
|
|
and #$07
|
|
stal APU_TRIANGLE_CURRENT_PERIOD+1
|
|
|
|
ldal APU_STATUS
|
|
bit #$04
|
|
beq :no_reload
|
|
|
|
ldal APU_TRIANGLE_REG4
|
|
and #$F8
|
|
lsr
|
|
lsr
|
|
lsr
|
|
tax
|
|
ldal LengthTable,x
|
|
stal APU_TRIANGLE_LENGTH_COUNTER ; Immediately start the counter
|
|
lda #1
|
|
stal APU_TRIANGLE_START_FLAG
|
|
|
|
:no_reload
|
|
pla
|
|
plx
|
|
plp
|
|
rtl
|
|
|
|
|
|
APU_NOISE_REG1_WRITE ENT
|
|
stal APU_NOISE_REG1
|
|
rtl
|
|
|
|
APU_NOISE_REG2_WRITE ENT
|
|
stal APU_NOISE_REG2
|
|
rtl
|
|
|
|
APU_NOISE_REG3_WRITE ENT
|
|
php
|
|
phx
|
|
pha
|
|
|
|
stal APU_NOISE_REG3
|
|
and #$0F
|
|
asl
|
|
tax
|
|
; ldal NoisePeriodTable,x
|
|
ldal EsqNoiseFreqTable,x
|
|
stal APU_NOISE_CURRENT_PERIOD
|
|
; ldal NoisePeriodTable+1,x
|
|
ldal EsqNoiseFreqTable+1,x
|
|
stal APU_NOISE_CURRENT_PERIOD+1
|
|
|
|
pla
|
|
plx
|
|
plp
|
|
rtl
|
|
|
|
APU_NOISE_REG4_WRITE ENT
|
|
php
|
|
phx
|
|
pha
|
|
|
|
stal APU_NOISE_REG4
|
|
|
|
ldal APU_STATUS
|
|
bit #$08
|
|
beq :no_reload
|
|
|
|
ldal APU_NOISE_REG4
|
|
and #$F8
|
|
lsr
|
|
lsr
|
|
lsr
|
|
tax
|
|
ldal LengthTable,x
|
|
stal APU_NOISE_LENGTH_COUNTER ; Immediately start the counter
|
|
lda #1
|
|
stal APU_NOISE_START_FLAG
|
|
|
|
:no_reload
|
|
pla
|
|
plx
|
|
plp
|
|
rtl
|
|
|
|
; Lookup from bottom 4 bits of NOISE_REG3 and pre-calculated ensoniq parameters
|
|
NoisePeriodTable dw 4, 8, 16, 32, 64, 96, 128, 160, 202, 254, 380, 508, 762, 1016, 2034, 4068
|
|
;EsqNoiseFreqTable dw 8704, 4352, 2176, 1088, 544, 363, 272, 218, 172, 137, 92, 69, 46, 34, 17, 9
|
|
EsqNoiseFreqTable dw 1088, 544, 272, 136, 68, 45,34,27,22,17,12,9,6,4,2,1
|
|
|
|
APU_FORCE_OFF dw 0
|
|
|
|
APU_STATUS_FORCE
|
|
phb
|
|
phk
|
|
plb
|
|
pha
|
|
bra force_entry
|
|
|
|
APU_STATUS_WRITE ENT
|
|
phb
|
|
phk
|
|
plb
|
|
pha
|
|
|
|
phx
|
|
ldx APU_FORCE_OFF
|
|
bne force_exit
|
|
plx
|
|
|
|
force_entry
|
|
sta APU_STATUS
|
|
|
|
; From NESDev Wiki: When the enabled bit is cleared (via $4015), the length counter is forced to 0
|
|
; and cannot be changed until enabled is set again (the length counter's previous value is lost).
|
|
; There is no immediate effect when enabled is set.
|
|
|
|
; Pulse 1
|
|
bit #$01
|
|
bne :pulse1_on
|
|
stz APU_PULSE1_LENGTH_COUNTER
|
|
:pulse1_on
|
|
|
|
; Pulse 2
|
|
bit #$02
|
|
bne :pulse2_on
|
|
stz APU_PULSE2_LENGTH_COUNTER
|
|
:pulse2_on
|
|
|
|
; Triangle
|
|
bit #$04
|
|
bne :triangle_on
|
|
stz APU_TRIANGLE_LENGTH_COUNTER
|
|
:triangle_on
|
|
|
|
; Noise
|
|
bit #$08
|
|
bne :noise_on
|
|
stz APU_NOISE_LENGTH_COUNTER
|
|
:noise_on
|
|
|
|
pla
|
|
plb
|
|
rtl
|
|
|
|
force_exit
|
|
plx
|
|
pla
|
|
plb
|
|
rtl
|