2021-09-19 22:49:29 +00:00
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lst off
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rel
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xc
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xc
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mx %11
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cas se
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* use vt.equ
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SCCBREG equ $c038
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SCCAREG equ $c039
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SCCBDATA equ $c03a
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SCCADATA equ $c03b
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2021-09-21 02:45:02 +00:00
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init_modem ent
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2021-09-22 02:35:33 +00:00
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* sep #$30
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2021-09-19 22:49:29 +00:00
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* reset channel B (modem port)
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ldx #9
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lda #%01010001
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stx SCCBREG
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sta SCCBREG
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nop
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nop
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* x16 clock mode, 1 stop bit, no parity
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ldx #4
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lda #%01000100
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stx SCCBREG
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sta SCCBREG
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* 8 bits/char, rx disabled.
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ldx #3
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lda #%11000000
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stx SCCBREG
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sta SCCBREG
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* 8 data bits, RTS
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ldx #5
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lda #%01100010
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stx SCCBREG
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sta SCCBREG
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ldx #11
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lda #%01010000
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stx SCCBREG
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sta SCCBREG
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* 9600 baud
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ldx #12
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lda #10
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stx SCCBREG
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sta SCCBREG
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* 9600 baud
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ldx #13
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lda #0
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stx SCCBREG
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sta SCCBREG
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* disable baud rate generator
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ldx #14
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lda #0
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stx SCCBREG
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sta SCCBREG
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* enable baud rate generator
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ldx #14
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lda #%00000001
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stx SCCBREG
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sta SCCBREG
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* 8 bits/char, rx enabled.
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ldx #3
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lda #%11000001
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stx SCCBREG
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sta SCCBREG
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* 8 data bits, tx enabled, RTS
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ldx #5
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lda #%01101010
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stx SCCBREG
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sta SCCBREG
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* disable interrupts
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ldx #15
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lda #0
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stx SCCBREG
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sta SCCBREG
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* reset ext/status interrupts
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ldx #0
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lda #%00010000
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stx SCCBREG
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sta SCCBREG
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* disable interrupts
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ldx #1
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lda #0
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stx SCCBREG
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sta SCCBREG
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* reset ch b ptr to 0?
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lda SCCBREG
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* status, visible, master interrupts disabled
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ldx #9
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lda #%00010001
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stx SCCBREG
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sta SCCBREG
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nop
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nop
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rts
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write_modem ent
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mx %11
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* a: byte to send
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tay ; save
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* ldx #0
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:mask = %0010_0100 ; tx buffer empty, clear to send
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:wait stz SCCBREG
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lda SCCBREG
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and #:mask
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cmp #:mask
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bne :wait
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sty SCCBDATA
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rts
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read_modem ent
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* c set if data read
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* v set if overrun
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mx %11
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* ldx #0
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rep #$41 ; clear C + V
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stz SCCBREG
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lda SCCBREG
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and #%0001
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beq :rts
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* read reg 1 for overrun
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lda #1
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sta SCCBREG
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lda SCCBREG
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and #%0010_0000
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beq :ok
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* clear the overrun
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lda #$30 ; reg0, error reset.
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sta SCCBREG
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stz SCCBREG
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sep #$40 ; V
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:ok
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* lda #8
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* sta SCCBREG
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* lda SCCBREG
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lda SCCBDATA
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sec
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:rts rts
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sav vt100.modem.L
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