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cda - improve ssc register display

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Kelvin Sherlock 2021-12-06 20:14:35 -05:00
parent e1639db6e4
commit 279f424cee
1 changed files with 129 additions and 54 deletions
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167
vt100.cda.S
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@ -384,7 +384,7 @@ lnm
sgr sgr
mx %10 mx %10
ldy #line_12+4 ldy #line_13+4
ldx #:str ldx #:str
jsr print_xy_str jsr print_xy_str
lda DPAGE+SGR lda DPAGE+SGR
@ -608,17 +608,18 @@ ssc_registers
xba xba
* sei * sei
ldx #0 ldx #0
lda SCCBREG ; sync
lda SCCAREG ; sync lda SCCAREG ; sync
lda SCCBREG ; sync
stx SCCBREG stx SCCAREG
lda SCCBREG lda SCCAREG
sta ssc_data+0 sta ssc_data+0
inx ;1
stx SCCBREG stx SCCBREG
lda SCCBREG lda SCCBREG
sta ssc_data+1 sta ssc_data+1
inx ;2 - A and B both needed.
inx ;1
stx SCCAREG stx SCCAREG
lda SCCAREG lda SCCAREG
sta ssc_data+2 sta ssc_data+2
@ -626,34 +627,69 @@ ssc_registers
lda SCCBREG lda SCCBREG
sta ssc_data+3 sta ssc_data+3
inx ;3 - A only inx ;2
stx SCCAREG stx SCCAREG
lda SCCAREG lda SCCAREG
sta ssc_data+4 sta ssc_data+4
ldx #10
stx SCCBREG stx SCCBREG
lda SCCBREG lda SCCBREG
sta ssc_data+5 sta ssc_data+5
ldx #12
stx SCCBREG inx ;3
lda SCCBREG
stx SCCAREG
lda SCCAREG
sta ssc_data+6 sta ssc_data+6
inx ; 13
stx SCCBREG stx SCCBREG
lda SCCBREG lda SCCBREG
sta ssc_data+7 sta ssc_data+7
ldx #15
ldx #10 ; 10
stx SCCAREG
lda SCCAREG
sta ssc_data+8
stx SCCBREG stx SCCBREG
lda SCCBREG lda SCCBREG
sta ssc_data+8 sta ssc_data+9
ldx #12 ; 12
stx SCCAREG
lda SCCAREG
sta ssc_data+10
stx SCCBREG
lda SCCBREG
sta ssc_data+11
inx ; 13
stx SCCAREG
lda SCCAREG
sta ssc_data+12
stx SCCBREG
lda SCCBREG
sta ssc_data+13
ldx #15 ; 15
stx SCCAREG
lda SCCAREG
sta ssc_data+14
stx SCCBREG
lda SCCBREG
sta ssc_data+15
cli cli
rep #$10 ; long x rep #$10 ; long x
mx %10 mx %10
jsr rr0 jsr rr0
jsr rr1 jsr rr1
jsr rr2a jsr rr2
jsr rr2b
jsr rr3 ; only exists in channel A. jsr rr3 ; only exists in channel A.
jsr rr10 jsr rr10
jsr rr12 ; baud low jsr rr12 ; baud low
@ -662,7 +698,7 @@ ssc_registers
plp plp
rts rts
ssc_data ds 10 ssc_data ds 16
rr0 rr0
mx %10 mx %10
@ -670,83 +706,122 @@ rr0
ldx #:str ldx #:str
jsr print_xy_str jsr print_xy_str
lda ssc_data+0 lda ssc_data+0
jsr print_binary
iny
iny
lda ssc_data+1
jmp print_binary jmp print_binary
:str asc "reg 0: ",00 :str asc "RR 0: ",00
rr1 rr1
mx %10 mx %10
ldy #line_6+4 ldy #line_6+4
ldx #:str ldx #:str
jsr print_xy_str jsr print_xy_str
lda ssc_data+1 lda ssc_data+2
jsr print_binary
iny
iny
lda ssc_data+3
jmp print_binary jmp print_binary
:str asc "reg 1: ",00 :str asc "RR 1: ",00
rr2a rr2
mx %10 mx %10
ldy #line_7+4 ldy #line_7+4
ldx #:str ldx #:str
jsr print_xy_str jsr print_xy_str
lda ssc_data+2 lda ssc_data+4
jsr print_binary
iny
iny
lda ssc_data+5
jmp print_binary jmp print_binary
:str asc "reg 2A: ",00 :str asc "RR 2: ",00
rr2b rr3
mx %10 mx %10
ldy #line_8+4 ldy #line_8+4
ldx #:str ldx #:str
jsr print_xy_str jsr print_xy_str
lda ssc_data+3 lda ssc_data+6
jsr print_binary
iny
iny
lda ssc_data+7
jmp print_binary jmp print_binary
:str asc "reg 2B: ",00 :str asc "RR 3: ",00
rr3 rr10
mx %10 mx %10
ldy #line_9+4 ldy #line_9+4
ldx #:str ldx #:str
jsr print_xy_str jsr print_xy_str
lda ssc_data+4 lda ssc_data+8
jsr print_binary
iny
iny
lda ssc_data+9
jmp print_binary jmp print_binary
:str asc "reg 3: ",00 :str asc "RR 10: ",00
rr10
mx %10
ldy #line_10+4
ldx #:str
jsr print_xy_str
lda ssc_data+5
jmp print_binary
:str asc "reg 10: ",00
* 12/13 are baud * 12/13 are baud
rr12 rr12
mx %10 mx %10
ldy #line_11+4 ldy #line_10+4
ldx #:str ldx #:str
jsr print_xy_str jsr print_xy_str
lda ssc_data+7
iny
iny
iny
iny
lda ssc_data+12
jsr print_hex jsr print_hex
lda ssc_data+6 lda ssc_data+10
jsr print_hex
iny
iny
iny
iny
iny
iny
lda ssc_data+13
jsr print_hex
lda ssc_data+11
jmp print_hex jmp print_hex
:str asc "reg 12/13: ",00
:str asc "RR 12: ",00
rr15 rr15
mx %10 mx %10
ldy #line_12+4 ldy #line_11+4
ldx #:str ldx #:str
jsr print_xy_str jsr print_xy_str
lda ssc_data+8
lda ssc_data+14
jsr print_binary
iny
iny
lda ssc_data+15
jmp print_binary jmp print_binary
:str asc "reg 15: ",00 :str asc "RR 15: ",00
text text
dw $0400 dw $0400