#$ TOOL ispLEVER Classic 2.0.00.17.20.15
#$ DATE Wed Aug 17 17:45:46 2016
#$ MODULE 68030_tk
#$ PINS 61 SIZE_1_ A_31_ IPL_030_2_ IPL_030_1_ IPL_2_ IPL_030_0_ IPL_1_ FC_1_ IPL_0_ \
#  AS_030 FC_0_ AS_000 RW_000 DS_030 UDS_000 LDS_000 A0 A1 nEXP_SPACE BERR BG_030 BG_000 \
#  BGACK_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS FPU_SENSE \
#  DSACK1 DTACK AVEC E VPA VMA RST RESET RW AMIGA_ADDR_ENABLE SIZE_0_ AMIGA_BUS_DATA_DIR \
#  A_30_ AMIGA_BUS_ENABLE_LOW A_29_ AMIGA_BUS_ENABLE_HIGH A_28_ CIIN A_27_ A_26_ A_25_ \
#  A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_
#$ NODES 79 inst_BGACK_030_INTreg inst_VMA_INTreg N_317_i cpu_est_2_ cpu_est_3_ \
#  cpu_est_0_ cpu_est_1_ inst_AS_000_INT SM_AMIGA_5_ inst_AMIGA_BUS_ENABLE_DMA_LOW \
#  inst_AS_030_D0 inst_nEXP_SPACE_D0reg inst_AS_030_000_SYNC inst_BGACK_030_INT_D \
#  inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ \
#  inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT inst_CLK_OUT_PRE_D inst_DTACK_D0 \
#  inst_RESET_OUT inst_CLK_OUT_PRE_50 CLK_000_D_1_ CLK_000_D_0_ inst_CLK_000_PE \
#  CLK_000_P_SYNC_9_ inst_CLK_000_NE CLK_000_N_SYNC_11_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ \
#  inst_CLK_000_NE_D0 SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_DSACK1_INTreg \
#  SM_AMIGA_4_ inst_DS_000_ENABLE RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ CLK_000_P_SYNC_0_ \
#  CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ \
#  CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ \
#  CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ \
#  CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ \
#  CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ inst_RW_000_INT \
#  inst_RW_000_DMA inst_A0_DMA SM_AMIGA_6_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_3_ \
#  SM_AMIGA_2_ SM_AMIGA_i_7_ BG_000DFFreg CLK_OUT_INTreg IPL_030DFF_0_reg \
#  IPL_030DFF_1_reg IPL_030DFF_2_reg
.model bus68030
.inputs A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF A1.BLIF nEXP_SPACE.BLIF BG_030.BLIF \
BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF FPU_SENSE.BLIF \
DTACK.BLIF VPA.BLIF RST.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF \
A_26_.BLIF A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF \
A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF \
inst_BGACK_030_INTreg.BLIF inst_VMA_INTreg.BLIF N_317_i.BLIF cpu_est_2_.BLIF \
cpu_est_3_.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF inst_AS_000_INT.BLIF \
SM_AMIGA_5_.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF inst_AS_030_D0.BLIF \
inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INT_D.BLIF \
inst_AS_000_DMA.BLIF inst_DS_000_DMA.BLIF CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF \
SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF inst_VPA_D.BLIF inst_UDS_000_INT.BLIF \
inst_LDS_000_INT.BLIF inst_CLK_OUT_PRE_D.BLIF inst_DTACK_D0.BLIF \
inst_RESET_OUT.BLIF inst_CLK_OUT_PRE_50.BLIF CLK_000_D_1_.BLIF \
CLK_000_D_0_.BLIF inst_CLK_000_PE.BLIF CLK_000_P_SYNC_9_.BLIF \
inst_CLK_000_NE.BLIF CLK_000_N_SYNC_11_.BLIF IPL_D0_0_.BLIF IPL_D0_1_.BLIF \
IPL_D0_2_.BLIF inst_CLK_000_NE_D0.BLIF SM_AMIGA_0_.BLIF \
inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF inst_DSACK1_INTreg.BLIF SM_AMIGA_4_.BLIF \
inst_DS_000_ENABLE.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF RST_DLY_2_.BLIF \
CLK_000_P_SYNC_0_.BLIF CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.BLIF \
CLK_000_P_SYNC_3_.BLIF CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.BLIF \
CLK_000_P_SYNC_6_.BLIF CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.BLIF \
CLK_000_N_SYNC_0_.BLIF CLK_000_N_SYNC_1_.BLIF CLK_000_N_SYNC_2_.BLIF \
CLK_000_N_SYNC_3_.BLIF CLK_000_N_SYNC_4_.BLIF CLK_000_N_SYNC_5_.BLIF \
CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.BLIF \
CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.BLIF inst_RW_000_INT.BLIF \
inst_RW_000_DMA.BLIF inst_A0_DMA.BLIF SM_AMIGA_6_.BLIF inst_CLK_030_H.BLIF \
SM_AMIGA_1_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_i_7_.BLIF \
BG_000DFFreg.BLIF CLK_OUT_INTreg.BLIF IPL_030DFF_0_reg.BLIF \
IPL_030DFF_1_reg.BLIF IPL_030DFF_2_reg.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF \
RW_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF \
SIZE_1_.PIN.BLIF A0.PIN.BLIF BERR.PIN.BLIF RW.PIN.BLIF
.outputs IPL_030_2_ DS_030 BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 \
AVEC E VMA RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \
AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_4_.D SM_AMIGA_4_.C \
SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C \
SM_AMIGA_0_.D SM_AMIGA_0_.C IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C \
IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D IPL_030DFF_2_reg.C \
IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D IPL_D0_2_.C \
SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_5_.D \
SM_AMIGA_5_.C CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.D \
CLK_000_N_SYNC_11_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D \
CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C \
cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C \
cpu_est_3_.D cpu_est_3_.C CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C \
CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.D \
CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C \
CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.D \
CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C \
CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.D \
CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C \
CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.D \
CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C \
CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.D \
CLK_000_N_SYNC_9_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C \
CLK_000_D_0_.D CLK_000_D_0_.C CLK_000_D_1_.D CLK_000_D_1_.C \
CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.D \
CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_2_.C \
CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.D \
CLK_000_P_SYNC_4_.C RST_DLY_0_.D RST_DLY_0_.C inst_AS_000_INT.D \
inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C inst_DS_000_DMA.D \
inst_DS_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.D \
inst_nEXP_SPACE_D0reg.C inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D \
inst_DTACK_D0.C inst_CLK_030_H.C inst_RESET_OUT.D inst_RESET_OUT.C \
inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C BG_000DFFreg.D BG_000DFFreg.C \
inst_AMIGA_BUS_ENABLE_DMA_HIGH.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.C \
inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AMIGA_BUS_ENABLE_DMA_LOW.C \
inst_VMA_INTreg.D inst_VMA_INTreg.C inst_UDS_000_INT.D inst_UDS_000_INT.C \
inst_A0_DMA.D inst_A0_DMA.C inst_RW_000_DMA.D inst_RW_000_DMA.C \
inst_RW_000_INT.D inst_RW_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C \
inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_AS_000_DMA.D \
inst_AS_000_DMA.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \
inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_CLK_000_NE_D0.D \
inst_CLK_000_NE_D0.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C \
CLK_OUT_INTreg.D CLK_OUT_INTreg.C inst_CLK_000_PE.D inst_CLK_000_PE.C \
inst_CLK_000_NE.D inst_CLK_000_NE.C inst_CLK_OUT_PRE_50.D \
inst_CLK_OUT_PRE_50.C SIZE_1_ AS_030 AS_000 RW_000 UDS_000 LDS_000 A0 BERR RW \
SIZE_0_ N_317_i AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE \
SIZE_1_.OE A0.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE CIIN.OE \
inst_CLK_030_H.D.X1 inst_CLK_030_H.D.X2 SM_AMIGA_3_.D.X1 SM_AMIGA_3_.D.X2
.names RST.BLIF SM_AMIGA_5_.BLIF inst_CLK_000_PE.BLIF inst_CLK_000_NE.BLIF \
SM_AMIGA_4_.BLIF BERR.PIN.BLIF SM_AMIGA_4_.D
1-0-11 1
11-1-- 1
11--1- 1
---00- 0
-01--- 0
-0--0- 0
0----- 0
-0---0 0
.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_2_.BLIF cpu_est_3_.BLIF \
cpu_est_0_.BLIF cpu_est_1_.BLIF inst_VPA_D.BLIF inst_DTACK_D0.BLIF \
inst_CLK_000_PE.BLIF inst_CLK_000_NE_D0.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF \
BERR.PIN.BLIF SM_AMIGA_2_.D
1001000--11-- 1
1-----10-11-- 1
1-------0--11 1
1---------11- 1
------11---0- 0
--------1-0-- 0
-----10----0- 0
----1-0----0- 0
---0--0----0- 0
--1---0----0- 0
-1----0----0- 0
---------0-0- 0
----------00- 0
0------------ 0
----------0-0 0
.names RST.BLIF inst_CLK_000_PE.BLIF inst_CLK_000_NE.BLIF SM_AMIGA_1_.BLIF \
SM_AMIGA_2_.BLIF BERR.PIN.BLIF SM_AMIGA_1_.D
11-01- 1
1-01-1 1
1--111 1
--1-0- 0
-0-0-- 0
---00- 0
---1-0 0
0----- 0
.names RST.BLIF inst_CLK_000_PE.BLIF inst_CLK_000_NE.BLIF SM_AMIGA_0_.BLIF \
SM_AMIGA_1_.BLIF BERR.PIN.BLIF SM_AMIGA_0_.D
1-101- 1
10-1-1 1
-1-1-- 0
---00- 0
--00-- 0
---1-0 0
0----- 0
.names IPL_2_.BLIF RST.BLIF IPL_1_.BLIF IPL_0_.BLIF IPL_D0_0_.BLIF \
IPL_D0_1_.BLIF IPL_D0_2_.BLIF IPL_030DFF_0_reg.BLIF IPL_030DFF_0_reg.D
0-01100- 1
0-11110- 1
1-01101- 1
1-11111- 1
1-----01 1
0-----11 1
--1--0-1 1
--0--1-1 1
---1---1 1
----1--1 1
-0------ 1
0100000- 0
0110010- 0
1100001- 0
1110011- 0
11----00 0
01----10 0
-11--0-0 0
-10--1-0 0
-1--0--0 0
-1-0---0 0
.names IPL_2_.BLIF RST.BLIF IPL_1_.BLIF IPL_0_.BLIF IPL_D0_0_.BLIF \
IPL_D0_1_.BLIF IPL_D0_2_.BLIF IPL_030DFF_1_reg.BLIF IPL_030DFF_1_reg.D
0-10010- 1
0-11110- 1
1-10011- 1
1-11111- 1
1-----01 1
0-----11 1
--1----1 1
-----1-1 1
---10--1 1
---01--1 1
-0------ 1
0100000- 0
0101100- 0
1100001- 0
1101101- 0
11----00 0
01----10 0
-1-10--0 0
-1-01--0 0
-1---0-0 0
-10----0 0
.names IPL_2_.BLIF RST.BLIF IPL_1_.BLIF IPL_0_.BLIF IPL_D0_0_.BLIF \
IPL_D0_1_.BLIF IPL_D0_2_.BLIF IPL_030DFF_2_reg.BLIF IPL_030DFF_2_reg.D
1-00001- 1
1-01101- 1
1-10011- 1
1-11111- 1
1------1 1
------11 1
--1--0-1 1
--0--1-1 1
---10--1 1
---01--1 1
-0------ 1
0100000- 0
0101100- 0
0110010- 0
0111110- 0
-11--0-0 0
-10--1-0 0
-1-10--0 0
-1-01--0 0
-1----00 0
01-----0 0
.names RST.BLIF IPL_0_.BLIF IPL_D0_0_.D
0- 1
-1 1
10 0
.names RST.BLIF IPL_1_.BLIF IPL_D0_1_.D
0- 1
-1 1
10 0
.names IPL_2_.BLIF RST.BLIF IPL_D0_2_.D
1- 1
-0 1
01 0
.names RST.BLIF inst_VMA_INTreg.BLIF N_317_i.BLIF cpu_est_2_.BLIF \
cpu_est_3_.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF SM_AMIGA_5_.BLIF \
inst_VPA_D.BLIF inst_DTACK_D0.BLIF inst_CLK_000_PE.BLIF inst_CLK_000_NE.BLIF \
inst_CLK_000_NE_D0.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_6_.BLIF \
SM_AMIGA_1_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF BERR.PIN.BLIF \
SM_AMIGA_i_7_.D
101010000---10000-0- 1
1010100-0--11000--0- 1
101010000-1-10--0--- 1
1010100-0-1110------ 1
1-1----010--10000-0- 1
1-1-----10-11000--0- 1
1-1----0-----000000- 1
1-1----0101-10--0--- 1
1-1--------1-000-00- 1
1-1-----101110------ 1
1-1----0--1--0--00-- 1
1-1-------11-0---0-- 1
1-1-------0--------1 1
1-1----------0-----1 1
--------11-------1-0 0
----------1--1------ 0
------1-0--------1-0 0
-----1--0--------1-0 0
----0---0--------1-0 0
---1----0--------1-0 0
-1------0--------1-0 0
-----------0----1--0 0
-------1---0-------0 0
----------0-------10 0
----------0----1---0 0
----------0---1----0 0
------------0----1-0 0
--0----------------- 0
0------------------- 0
-------------1-----0 0
.names RST.BLIF inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_000_SYNC.BLIF \
CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF inst_CLK_000_PE.BLIF SM_AMIGA_6_.BLIF \
SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF SM_AMIGA_6_.D
11010--0- 1
1----01-1 1
1-----10- 1
-----1-1- 0
----1-0-- 0
---0--0-- 0
--1---0-- 0
-0----0-- 0
------01- 0
0-------- 0
-------10 0
.names RST.BLIF SM_AMIGA_5_.BLIF inst_CLK_000_PE.BLIF inst_CLK_000_NE.BLIF \
SM_AMIGA_6_.BLIF BERR.PIN.BLIF SM_AMIGA_5_.D
101-1- 1
11-0-1 1
11--11 1
---10- 0
-00--- 0
-0--0- 0
-1---0 0
0----- 0
.names RST.BLIF inst_BGACK_030_INTreg.BLIF CYCLE_DMA_0_.BLIF \
inst_CLK_000_PE.BLIF AS_000.PIN.BLIF CYCLE_DMA_0_.D
10100 1
10010 1
--00- 0
--11- 0
-1--- 0
0---- 0
----1 0
.names RST.BLIF inst_BGACK_030_INTreg.BLIF CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF \
inst_CLK_000_PE.BLIF AS_000.PIN.BLIF CYCLE_DMA_1_.D
101010 1
10-100 1
1001-0 1
--111- 0
---00- 0
--00-- 0
-1---- 0
0----- 0
-----1 0
.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \
SIZE_DMA_0_.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_DMA_0_.D
-111-- 1
-0--1- 1
0----- 1
-0---1 1
10--00 0
11-0-- 0
110--- 0
.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \
SIZE_DMA_1_.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_DMA_1_.D
-111-- 1
-0--00 1
0----- 1
10--1- 0
11-0-- 0
110--- 0
10---1 0
.names cpu_est_3_.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF inst_CLK_000_NE_D0.BLIF \
cpu_est_1_.D
0101 1
-01- 1
--10 1
1-0- 0
-111 0
-00- 0
--00 0
.names cpu_est_2_.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF inst_CLK_000_NE_D0.BLIF \
cpu_est_2_.D
0111 1
1-0- 1
10-- 1
1--0 1
1111 0
0-0- 0
00-- 0
0--0 0
.names cpu_est_2_.BLIF cpu_est_3_.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF \
inst_CLK_000_NE_D0.BLIF cpu_est_3_.D
1-111 1
010-- 1
-1--0 1
--101 0
00--- 0
1-0-1 0
0-1-1 0
-0--0 0
.names RST.BLIF inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF \
RST_DLY_2_.BLIF RST_DLY_1_.D
1--11 1
1110- 1
1-01- 1
10-1- 1
-1110 0
--00- 0
-0-0- 0
0---- 0
.names RST.BLIF inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF \
RST_DLY_2_.BLIF RST_DLY_2_.D
1111- 1
1---1 1
0---- 0
---00 0
--0-0 0
-0--0 0
.names CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF CLK_000_P_SYNC_0_.D
01 1
1- 0
-0 0
.names RST.BLIF inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF \
RST_DLY_2_.BLIF RST_DLY_0_.D
1-111 1
110-- 1
101-- 1
-110- 0
-00-- 0
-11-0 0
0---- 0
.names RST.BLIF inst_AS_000_INT.BLIF SM_AMIGA_5_.BLIF inst_AS_030_D0.BLIF \
BERR.PIN.BLIF inst_AS_000_INT.D
-10-- 1
--01- 1
0---- 1
--0-0 1
10-01 0
1-1-- 0
.names CLK_030.BLIF RST.BLIF inst_AS_030_D0.BLIF inst_CLK_OUT_PRE_D.BLIF \
inst_DSACK1_INTreg.BLIF CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.BLIF \
SM_AMIGA_1_.BLIF BERR.PIN.BLIF inst_DSACK1_INTreg.D
1--01-0-- 1
----100-- 1
1-10--0-- 1
1--0--0-0 1
----1--0- 1
--1--00-- 1
-----00-0 1
--1----0- 1
-0------- 1
-------00 1
-10-0---1 0
-1-1-1-1- 0
01---1-1- 0
-1----11- 0
.names CLK_030.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \
inst_DS_000_DMA.BLIF CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF inst_CLK_030_H.BLIF \
AS_000.PIN.BLIF RW_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF \
inst_DS_000_DMA.D
1--1---1-0-- 1
----1--0-0-- 1
0---1----0-- 1
-----00----- 1
-----11----- 1
--------1--- 1
--1--------- 1
-0---------- 1
----------11 1
1100-1010-0- 0
1100-0110-0- 0
1100-1010--0 0
1100-0110--0 0
-10-01000-0- 0
-10-00100-0- 0
010-010-0-0- 0
010-001-0-0- 0
-10-01000--0 0
-10-00100--0 0
010-010-0--0 0
010-001-0--0 0
-10--10-010- 0
-10--01-010- 0
-10--10-01-0 0
-10--01-01-0 0
.names RST.BLIF AS_030.PIN.BLIF inst_AS_030_D0.D
0- 1
-1 1
10 0
.names nEXP_SPACE.BLIF RST.BLIF inst_nEXP_SPACE_D0reg.D
1- 1
-0 1
01 0
.names VPA.BLIF RST.BLIF inst_VPA_D.D
1- 1
-0 1
01 0
.names DTACK.BLIF RST.BLIF inst_DTACK_D0.D
1- 1
-0 1
01 0
.names RST.BLIF inst_RESET_OUT.BLIF inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF \
RST_DLY_1_.BLIF RST_DLY_2_.BLIF inst_RESET_OUT.D
1-1111 1
11---- 1
-0--0- 0
-0-0-- 0
-00--- 0
0----- 0
-0---0 0
.names RST.BLIF SM_AMIGA_5_.BLIF inst_AS_030_D0.BLIF inst_CLK_000_PE.BLIF \
SM_AMIGA_0_.BLIF SM_AMIGA_4_.BLIF inst_DS_000_ENABLE.BLIF SM_AMIGA_6_.BLIF \
SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF RW.PIN.BLIF inst_DS_000_ENABLE.D
10--00-01-- 1
10-10--01-- 1
1-0---1--1- 1
1---00-01-1 1
1--10--01-1 1
---0-1---0- 0
---0-10---- 0
--10-1----- 0
-1-------00 0
-1----0---0 0
-11-------0 0
--------00- 0
-------1-0- 0
----1----0- 0
------0-0-- 0
--1-----0-- 0
------01--- 0
--1----1--- 0
----1-0---- 0
--1-1------ 0
0---------- 0
.names BG_030.BLIF RST.BLIF inst_AS_030_D0.BLIF inst_nEXP_SPACE_D0reg.BLIF \
CLK_000_D_0_.BLIF BG_000DFFreg.BLIF BG_000DFFreg.D
----01 1
---0-1 1
--0--1 1
-0---- 1
1----- 1
01111- 0
01---0 0
.names A1.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \
inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D
--1-1 1
1-0-- 1
--10- 1
-0--- 1
-1110 0
010-- 0
.names A1.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF \
inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF inst_BGACK_030_INT_D.BLIF \
inst_AMIGA_BUS_ENABLE_DMA_LOW.D
--11- 1
0-0-- 1
--1-0 1
-0--- 1
-1101 0
110-- 0
.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_2_.BLIF cpu_est_3_.BLIF \
cpu_est_0_.BLIF cpu_est_1_.BLIF inst_VPA_D.BLIF inst_CLK_000_PE.BLIF \
inst_CLK_000_NE.BLIF inst_VMA_INTreg.D
--0000-1- 1
-1----1-- 1
-1---0--- 1
-1--0---- 1
-1------0 1
0-------- 1
-1-1----- 1
-11------ 1
1-00110-1 0
10-----0- 0
10-1----- 0
101------ 0
10---1--- 0
10--1---- 0
.names RST.BLIF inst_UDS_000_INT.BLIF SM_AMIGA_6_.BLIF A0.PIN.BLIF \
inst_UDS_000_INT.D
-10- 1
0--- 1
--11 1
100- 0
1-10 0
.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \
inst_A0_DMA.BLIF UDS_000.PIN.BLIF inst_A0_DMA.D
-111- 1
0---- 1
-0--1 1
11-0- 0
110-- 0
10--0 0
.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \
inst_RW_000_DMA.BLIF RW_000.PIN.BLIF inst_RW_000_DMA.D
-1-1- 1
-10-- 1
0---- 1
-0--1 1
1110- 0
10--0 0
.names RST.BLIF SM_AMIGA_5_.BLIF inst_CLK_000_PE.BLIF SM_AMIGA_0_.BLIF \
inst_RW_000_INT.BLIF SM_AMIGA_i_7_.BLIF RW.PIN.BLIF inst_RW_000_INT.D
-0--1-- 1
-011--- 1
-0---0- 1
0------ 1
-1----1 1
10-001- 0
100-01- 0
11----0 0
.names RST.BLIF inst_LDS_000_INT.BLIF SM_AMIGA_6_.BLIF SIZE_0_.PIN.BLIF \
SIZE_1_.PIN.BLIF A0.PIN.BLIF inst_LDS_000_INT.D
--1100 1
-10--- 1
0----- 1
100--- 0
1-1-1- 0
1-10-- 0
1-1--1 0
.names BGACK_000.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_CLK_000_PE.BLIF \
AS_000.PIN.BLIF inst_BGACK_030_INTreg.D
1-1-- 1
1--11 1
-0--- 1
-100- 0
-10-0 0
01--- 0
.names CLK_030.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \
CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF AS_000.PIN.BLIF UDS_000.PIN.BLIF \
LDS_000.PIN.BLIF inst_AS_000_DMA.D
----00--- 1
----11--- 1
0--1----- 1
------1-- 1
--1------ 1
-0------- 1
-------11 1
-1001000- 0
110-1000- 0
-1000100- 0
110-0100- 0
-100100-0 0
110-100-0 0
-100010-0 0
110-010-0 0
.names FC_1_.BLIF RST.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF \
FC_0_.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_030_D0.BLIF \
inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INT_D.BLIF \
SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF inst_AS_030_000_SYNC.D
1-00101---1--- 1
----------1-1- 1
----------10-- 1
---------01--- 1
-------0--1--- 1
--------1----- 1
-0------------ 1
-------------0 1
-1----0101-101 0
-1---1-101-101 0
-1--0--101-101 0
-1-1---101-101 0
-11----101-101 0
01-----101-101 0
-1------0-0--1 0
.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.D
0- 1
-1 1
10 0
.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D
0 1
1 0
.names SM_AMIGA_5_.BLIF inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_000_SYNC.BLIF \
CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_4_.BLIF \
SM_AMIGA_6_.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF N_317_i
-1010------ 1
---------1- 1
--------1-- 1
-------1--- 1
------1---- 1
-----1----- 1
1---------- 1
----------1 1
0---1000000 0
0--0-000000 0
0-1--000000 0
00---000000 0
.names IPL_030DFF_2_reg.BLIF IPL_030_2_
1 1
0 0
.names inst_DS_000_DMA.BLIF AS_000.PIN.BLIF DS_030
1- 1
-1 1
00 0
.names BG_000DFFreg.BLIF BG_000
1 1
0 0
.names inst_BGACK_030_INTreg.BLIF BGACK_030
1 1
0 0
.names CLK_OUT_INTreg.BLIF CLK_DIV_OUT
1 1
0 0
.names CLK_OUT_INTreg.BLIF CLK_EXP
1 1
0 0
.names FC_1_.BLIF BGACK_000.BLIF FPU_SENSE.BLIF A_19_.BLIF A_18_.BLIF \
A_17_.BLIF A_16_.BLIF FC_0_.BLIF AS_030.PIN.BLIF FPU_CS
-------0- 1
------1-- 1
-----0--- 1
----1---- 1
---1----- 1
--1------ 1
-0------- 1
0-------- 1
--------1 1
110001010 0
.names inst_DSACK1_INTreg.BLIF DSACK1
1 1
0 0
.names AVEC
 1
.names cpu_est_2_.BLIF cpu_est_3_.BLIF cpu_est_1_.BLIF E
010 1
101 1
-00 0
0-1 0
11- 0
.names inst_VMA_INTreg.BLIF VMA
1 1
0 0
.names RESET
 0
.names AMIGA_ADDR_ENABLE
 0
.names inst_BGACK_030_INTreg.BLIF inst_nEXP_SPACE_D0reg.BLIF AS_000.PIN.BLIF \
RW_000.PIN.BLIF AMIGA_BUS_DATA_DIR
0001 1
1--0 1
-1-1 0
--11 0
0--0 0
1--1 0
.names inst_BGACK_030_INTreg.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF \
AMIGA_BUS_ENABLE_LOW
1- 1
-1 1
00 0
.names inst_BGACK_030_INTreg.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \
SM_AMIGA_i_7_.BLIF AMIGA_BUS_ENABLE_HIGH
01- 1
1-0 1
00- 0
1-1 0
.names A_31_.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF A_26_.BLIF \
A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF \
inst_AS_030_D0.BLIF CIIN
0000000011110 1
-----------0- 0
----------0-- 0
---------0--- 0
--------0---- 0
-------1----- 0
------1------ 0
-----1------- 0
----1-------- 0
---1--------- 0
--1---------- 0
-1----------- 0
1------------ 0
------------1 0
.names IPL_030DFF_1_reg.BLIF IPL_030_1_
1 1
0 0
.names IPL_030DFF_0_reg.BLIF IPL_030_0_
1 1
0 0
.names CLK_OSZI.BLIF SM_AMIGA_4_.C
1 1
0 0
.names CLK_OSZI.BLIF SM_AMIGA_3_.C
1 1
0 0
.names CLK_OSZI.BLIF SM_AMIGA_2_.C
1 1
0 0
.names CLK_OSZI.BLIF SM_AMIGA_1_.C
1 1
0 0
.names CLK_OSZI.BLIF SM_AMIGA_0_.C
1 1
0 0
.names CLK_OSZI.BLIF IPL_030DFF_0_reg.C
1 1
0 0
.names CLK_OSZI.BLIF IPL_030DFF_1_reg.C
1 1
0 0
.names CLK_OSZI.BLIF IPL_030DFF_2_reg.C
1 1
0 0
.names CLK_OSZI.BLIF IPL_D0_0_.C
1 1
0 0
.names CLK_OSZI.BLIF IPL_D0_1_.C
1 1
0 0
.names CLK_OSZI.BLIF IPL_D0_2_.C
1 1
0 0
.names CLK_OSZI.BLIF SM_AMIGA_i_7_.C
1 1
0 0
.names CLK_OSZI.BLIF SM_AMIGA_6_.C
1 1
0 0
.names CLK_OSZI.BLIF SM_AMIGA_5_.C
1 1
0 0
.names CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.D
1 1
0 0
.names CLK_OSZI.BLIF CLK_000_N_SYNC_10_.C
1 1
0 0
.names CLK_000_N_SYNC_10_.BLIF CLK_000_N_SYNC_11_.D
1 1
0 0
.names CLK_OSZI.BLIF CLK_000_N_SYNC_11_.C
1 1
0 0
.names CLK_OSZI.BLIF CYCLE_DMA_0_.C
1 1
0 0
.names CLK_OSZI.BLIF CYCLE_DMA_1_.C
1 1
0 0
.names CLK_OSZI.BLIF SIZE_DMA_0_.C
1 1
0 0
.names CLK_OSZI.BLIF SIZE_DMA_1_.C
1 1
0 0
.names cpu_est_0_.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_.D
10 1
01 1
00 0
11 0
.names CLK_OSZI.BLIF cpu_est_0_.C
1 1
0 0
.names CLK_OSZI.BLIF cpu_est_1_.C
1 1
0 0
.names CLK_OSZI.BLIF cpu_est_2_.C
1 1
0 0
.names CLK_OSZI.BLIF cpu_est_3_.C
1 1
0 0
.names CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.D
1 1
0 0
.names CLK_OSZI.BLIF CLK_000_P_SYNC_5_.C
1 1
0 0
.names CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.D
1 1
0 0
.names CLK_OSZI.BLIF CLK_000_P_SYNC_6_.C
1 1
0 0
.names CLK_000_P_SYNC_6_.BLIF CLK_000_P_SYNC_7_.D
1 1
0 0
.names CLK_OSZI.BLIF CLK_000_P_SYNC_7_.C
1 1
0 0
.names CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.D
1 1
0 0
.names CLK_OSZI.BLIF CLK_000_P_SYNC_8_.C
1 1
0 0
.names CLK_000_P_SYNC_8_.BLIF CLK_000_P_SYNC_9_.D
1 1
0 0
.names CLK_OSZI.BLIF CLK_000_P_SYNC_9_.C
1 1
0 0
.names CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF CLK_000_N_SYNC_0_.D
10 1
0- 0
-1 0
.names CLK_OSZI.BLIF CLK_000_N_SYNC_0_.C
1 1
0 0
.names CLK_000_N_SYNC_0_.BLIF CLK_000_N_SYNC_1_.D
1 1
0 0
.names CLK_OSZI.BLIF CLK_000_N_SYNC_1_.C
1 1
0 0
.names CLK_000_N_SYNC_1_.BLIF CLK_000_N_SYNC_2_.D
1 1
0 0
.names CLK_OSZI.BLIF CLK_000_N_SYNC_2_.C
1 1
0 0
.names CLK_000_N_SYNC_2_.BLIF CLK_000_N_SYNC_3_.D
1 1
0 0
.names CLK_OSZI.BLIF CLK_000_N_SYNC_3_.C
1 1
0 0
.names CLK_000_N_SYNC_3_.BLIF CLK_000_N_SYNC_4_.D
1 1
0 0
.names CLK_OSZI.BLIF CLK_000_N_SYNC_4_.C
1 1
0 0
.names CLK_000_N_SYNC_4_.BLIF CLK_000_N_SYNC_5_.D
1 1
0 0
.names CLK_OSZI.BLIF CLK_000_N_SYNC_5_.C
1 1
0 0
.names CLK_000_N_SYNC_5_.BLIF CLK_000_N_SYNC_6_.D
1 1
0 0
.names CLK_OSZI.BLIF CLK_000_N_SYNC_6_.C
1 1
0 0
.names CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.D
1 1
0 0
.names CLK_OSZI.BLIF CLK_000_N_SYNC_7_.C
1 1
0 0
.names CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.D
1 1
0 0
.names CLK_OSZI.BLIF CLK_000_N_SYNC_8_.C
1 1
0 0
.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D
1 1
0 0
.names CLK_OSZI.BLIF CLK_000_N_SYNC_9_.C
1 1
0 0
.names CLK_OSZI.BLIF RST_DLY_1_.C
1 1
0 0
.names CLK_OSZI.BLIF RST_DLY_2_.C
1 1
0 0
.names CLK_000.BLIF CLK_000_D_0_.D
1 1
0 0
.names CLK_OSZI.BLIF CLK_000_D_0_.C
1 1
0 0
.names CLK_000_D_0_.BLIF CLK_000_D_1_.D
1 1
0 0
.names CLK_OSZI.BLIF CLK_000_D_1_.C
1 1
0 0
.names CLK_OSZI.BLIF CLK_000_P_SYNC_0_.C
1 1
0 0
.names CLK_000_P_SYNC_0_.BLIF CLK_000_P_SYNC_1_.D
1 1
0 0
.names CLK_OSZI.BLIF CLK_000_P_SYNC_1_.C
1 1
0 0
.names CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.D
1 1
0 0
.names CLK_OSZI.BLIF CLK_000_P_SYNC_2_.C
1 1
0 0
.names CLK_000_P_SYNC_2_.BLIF CLK_000_P_SYNC_3_.D
1 1
0 0
.names CLK_OSZI.BLIF CLK_000_P_SYNC_3_.C
1 1
0 0
.names CLK_000_P_SYNC_3_.BLIF CLK_000_P_SYNC_4_.D
1 1
0 0
.names CLK_OSZI.BLIF CLK_000_P_SYNC_4_.C
1 1
0 0
.names CLK_OSZI.BLIF RST_DLY_0_.C
1 1
0 0
.names CLK_OSZI.BLIF inst_AS_000_INT.C
1 1
0 0
.names CLK_OSZI.BLIF inst_DSACK1_INTreg.C
1 1
0 0
.names CLK_OSZI.BLIF inst_DS_000_DMA.C
1 1
0 0
.names CLK_OSZI.BLIF inst_AS_030_D0.C
1 1
0 0
.names CLK_OSZI.BLIF inst_nEXP_SPACE_D0reg.C
1 1
0 0
.names CLK_OSZI.BLIF inst_VPA_D.C
1 1
0 0
.names CLK_OSZI.BLIF inst_DTACK_D0.C
1 1
0 0
.names CLK_OSZI.BLIF inst_CLK_030_H.C
1 1
0 0
.names CLK_OSZI.BLIF inst_RESET_OUT.C
1 1
0 0
.names CLK_OSZI.BLIF inst_DS_000_ENABLE.C
1 1
0 0
.names CLK_OSZI.BLIF BG_000DFFreg.C
1 1
0 0
.names CLK_OSZI.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.C
1 1
0 0
.names CLK_OSZI.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.C
1 1
0 0
.names CLK_OSZI.BLIF inst_VMA_INTreg.C
1 1
0 0
.names CLK_OSZI.BLIF inst_UDS_000_INT.C
1 1
0 0
.names CLK_OSZI.BLIF inst_A0_DMA.C
1 1
0 0
.names CLK_OSZI.BLIF inst_RW_000_DMA.C
1 1
0 0
.names CLK_OSZI.BLIF inst_RW_000_INT.C
1 1
0 0
.names CLK_OSZI.BLIF inst_LDS_000_INT.C
1 1
0 0
.names CLK_OSZI.BLIF inst_BGACK_030_INTreg.C
1 1
0 0
.names CLK_OSZI.BLIF inst_AS_000_DMA.C
1 1
0 0
.names CLK_OSZI.BLIF inst_AS_030_000_SYNC.C
1 1
0 0
.names CLK_OSZI.BLIF inst_BGACK_030_INT_D.C
1 1
0 0
.names inst_CLK_000_NE.BLIF inst_CLK_000_NE_D0.D
1 1
0 0
.names CLK_OSZI.BLIF inst_CLK_000_NE_D0.C
1 1
0 0
.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_D.D
1 1
0 0
.names CLK_OSZI.BLIF inst_CLK_OUT_PRE_D.C
1 1
0 0
.names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_INTreg.D
1 1
0 0
.names CLK_OSZI.BLIF CLK_OUT_INTreg.C
1 1
0 0
.names CLK_000_P_SYNC_9_.BLIF inst_CLK_000_PE.D
1 1
0 0
.names CLK_OSZI.BLIF inst_CLK_000_PE.C
1 1
0 0
.names CLK_000_N_SYNC_11_.BLIF inst_CLK_000_NE.D
1 1
0 0
.names CLK_OSZI.BLIF inst_CLK_000_NE.C
1 1
0 0
.names CLK_OSZI.BLIF inst_CLK_OUT_PRE_50.C
1 1
0 0
.names SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF SIZE_1_
01 1
1- 0
-0 0
.names inst_AS_000_DMA.BLIF AS_000.PIN.BLIF AS_030
1- 1
-1 1
00 0
.names inst_AS_000_INT.BLIF AS_030.PIN.BLIF AS_000
1- 1
-1 1
00 0
.names inst_RW_000_INT.BLIF RW_000
1 1
0 0
.names inst_UDS_000_INT.BLIF inst_DS_000_ENABLE.BLIF UDS_000
1- 1
-0 1
01 0
.names inst_LDS_000_INT.BLIF inst_DS_000_ENABLE.BLIF LDS_000
1- 1
-0 1
01 0
.names inst_A0_DMA.BLIF A0
1 1
0 0
.names BERR
 0
.names inst_RW_000_DMA.BLIF RW
1 1
0 0
.names SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF SIZE_0_
10 1
0- 0
-1 0
.names inst_BGACK_030_INTreg.BLIF inst_nEXP_SPACE_D0reg.BLIF \
inst_RESET_OUT.BLIF AS_030.OE
001 1
-1- 0
1-- 0
--0 0
.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF AS_000.OE
11 1
0- 0
-0 0
.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF RW_000.OE
11 1
0- 0
-0 0
.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF UDS_000.OE
11 1
0- 0
-0 0
.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF LDS_000.OE
11 1
0- 0
-0 0
.names inst_BGACK_030_INTreg.BLIF inst_nEXP_SPACE_D0reg.BLIF SIZE_0_.OE
00 1
1- 0
-1 0
.names inst_BGACK_030_INTreg.BLIF inst_nEXP_SPACE_D0reg.BLIF SIZE_1_.OE
00 1
1- 0
-1 0
.names inst_BGACK_030_INTreg.BLIF inst_nEXP_SPACE_D0reg.BLIF \
inst_RESET_OUT.BLIF A0.OE
001 1
-1- 0
1-- 0
--0 0
.names FC_1_.BLIF BGACK_000.BLIF FPU_SENSE.BLIF A_19_.BLIF A_18_.BLIF \
A_17_.BLIF A_16_.BLIF FC_0_.BLIF AS_030.PIN.BLIF BERR.OE
111001010 1
-------0- 0
------1-- 0
-----0--- 0
----1---- 0
---1----- 0
--0------ 0
-0------- 0
0-------- 0
--------1 0
.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF RW.OE
01 1
1- 0
-0 0
.names inst_BGACK_030_INTreg.BLIF inst_nEXP_SPACE_D0reg.BLIF \
inst_RESET_OUT.BLIF DS_030.OE
001 1
-1- 0
1-- 0
--0 0
.names inst_nEXP_SPACE_D0reg.BLIF DSACK1.OE
1 1
0 0
.names inst_RESET_OUT.BLIF RESET.OE
0 1
1 0
.names A_31_.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF A_26_.BLIF \
A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF \
inst_AS_030_D0.BLIF inst_nEXP_SPACE_D0reg.BLIF CIIN.OE
0000000011110- 1
-------------1 1
------------10 0
-----------0-0 0
----------0--0 0
---------0---0 0
--------0----0 0
-------1-----0 0
------1------0 0
-----1-------0 0
----1--------0 0
---1---------0 0
--1----------0 0
-1-----------0 0
1------------0 0
.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_CLK_030_H.D.X1
10 1
0- 0
-1 0
.names CLK_030.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \
CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF inst_CLK_030_H.BLIF AS_000.PIN.BLIF \
UDS_000.PIN.BLIF LDS_000.PIN.BLIF inst_CLK_030_H.D.X2
-10-00---- 1
-10----1-- 1
110---0--- 1
-101--0--- 1
-10-----11 1
-10-11---- 1
-0-------- 0
--1------- 0
----01100- 0
----10100- 0
----0110-0 0
----1010-0 0
0--001-00- 0
0--010-00- 0
0--001-0-0 0
0--010-0-0 0
.names RST.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_3_.D.X1
11 1
0- 0
-0 0
.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_2_.BLIF cpu_est_3_.BLIF \
cpu_est_0_.BLIF cpu_est_1_.BLIF inst_VPA_D.BLIF inst_DTACK_D0.BLIF \
inst_CLK_000_PE.BLIF inst_CLK_000_NE_D0.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_3_.BLIF \
BERR.PIN.BLIF SM_AMIGA_3_.D.X2
1-------1-10- 1
1----------10 1
1001000--101- 1
1-----10-101- 1
0------------ 0
--------0--0- 0
----------00- 0
---------0-11 0
----------111 0
-1----0----11 0
--1---0----11 0
---0--0----11 0
----1-0----11 0
-----10----11 0
------11---11 0
.end
