#-- Lattice Semiconductor Corporation Ltd.
#-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj
#-- Written on Tue Aug 12 21:21:07 2014


#device options
set_option -technology mach
set_option -part M4A5-128

#compilation/mapping options

#map options

#simulation options
set_option -write_verilog false
set_option -write_vhdl false

#timing analysis options
set_option -synthesis_onoff_pragma false

#-- add_file options
add_file -vhdl -lib work "68030-68000-bus.vhd"

#-- top module name
set_option -top_module BUS68030

#-- set result format/file last
project -result_file "BUS68030.edi"

#-- error message log file
project -log_file bus68030.srf

#-- run Synplify with 'arrange VHDL file'
project -run
