MODEL
MODEL_VERSION "1.0";
DESIGN "68030_tk";
DATE "Sun Feb 01 21:13:56 2015";
VENDOR "Lattice Semiconductor Corporation";
PROGRAM "STAMP Model Generator";

/* port name and type */
INPUT A1;
INPUT A_16;
INPUT A_17;
INPUT A_18;
INPUT A_19;
INPUT A_20;
INPUT A_21;
INPUT A_22;
INPUT A_23;
INPUT A_24;
INPUT A_25;
INPUT A_26;
INPUT A_27;
INPUT A_28;
INPUT A_29;
INPUT A_30;
INPUT A_31;
INPUT BGACK_000;
INPUT BG_030;
INPUT CLK_000;
INPUT CLK_030;
INPUT CLK_OSZI;
INPUT DTACK;
INPUT FC_0;
INPUT FC_1;
INPUT FPU_SENSE;
INPUT IPL_0;
INPUT IPL_1;
INPUT IPL_2;
INPUT RST;
INPUT VPA;
INPUT nEXP_SPACE;
OUTPUT AMIGA_ADDR_ENABLE;
OUTPUT AMIGA_BUS_DATA_DIR;
OUTPUT AMIGA_BUS_ENABLE_HIGH;
OUTPUT AMIGA_BUS_ENABLE_LOW;
OUTPUT AVEC;
OUTPUT BGACK_030;
OUTPUT BG_000;
OUTPUT CIIN;
OUTPUT CLK_DIV_OUT;
OUTPUT CLK_EXP;
OUTPUT DSACK1;
OUTPUT E;
OUTPUT FPU_CS;
OUTPUT IPL_030_0;
OUTPUT IPL_030_1;
OUTPUT IPL_030_2;
OUTPUT RESET;
OUTPUT VMA;
INOUT A0;
INOUT AS_000;
INOUT AS_030;
INOUT BERR;
INOUT DS_030;
INOUT LDS_000;
INOUT RW;
INOUT RW_000;
INOUT SIZE_0;
INOUT SIZE_1;
INOUT UDS_000;

/* timing arc definitions */
AS_030_AS_000_delay: DELAY AS_030 AS_000;
A_20_CIIN_delay: DELAY A_20 CIIN;
A_21_CIIN_delay: DELAY A_21 CIIN;
A_22_CIIN_delay: DELAY A_22 CIIN;
A_23_CIIN_delay: DELAY A_23 CIIN;
A_24_CIIN_delay: DELAY A_24 CIIN;
A_25_CIIN_delay: DELAY A_25 CIIN;
A_26_CIIN_delay: DELAY A_26 CIIN;
A_27_CIIN_delay: DELAY A_27 CIIN;
A_28_CIIN_delay: DELAY A_28 CIIN;
A_29_CIIN_delay: DELAY A_29 CIIN;
A_30_CIIN_delay: DELAY A_30 CIIN;
A_31_CIIN_delay: DELAY A_31 CIIN;
DS_030_LDS_000_delay: DELAY DS_030 LDS_000;
DS_030_UDS_000_delay: DELAY DS_030 UDS_000;
AS_000_AMIGA_BUS_DATA_DIR_delay: DELAY AS_000 AMIGA_BUS_DATA_DIR;
AS_030_FPU_CS_delay: DELAY AS_030 FPU_CS;
A_16_FPU_CS_delay: DELAY A_16 FPU_CS;
A_17_FPU_CS_delay: DELAY A_17 FPU_CS;
A_18_FPU_CS_delay: DELAY A_18 FPU_CS;
A_19_FPU_CS_delay: DELAY A_19 FPU_CS;
BGACK_000_FPU_CS_delay: DELAY BGACK_000 FPU_CS;
FC_0_FPU_CS_delay: DELAY FC_0 FPU_CS;
FC_1_FPU_CS_delay: DELAY FC_1 FPU_CS;
FPU_SENSE_FPU_CS_delay: DELAY FPU_SENSE FPU_CS;
RW_000_AMIGA_BUS_DATA_DIR_delay: DELAY RW_000 AMIGA_BUS_DATA_DIR;
CLK_OSZI_AS_000_delay: DELAY CLK_OSZI AS_000;
CLK_OSZI_CIIN_delay: DELAY CLK_OSZI CIIN;
CLK_OSZI_LDS_000_delay: DELAY CLK_OSZI LDS_000;
CLK_OSZI_LDS_000_delay: DELAY CLK_OSZI LDS_000;
CLK_OSZI_SIZE_0_delay: DELAY CLK_OSZI SIZE_0;
CLK_OSZI_SIZE_0_delay: DELAY CLK_OSZI SIZE_0;
CLK_OSZI_SIZE_1_delay: DELAY CLK_OSZI SIZE_1;
CLK_OSZI_SIZE_1_delay: DELAY CLK_OSZI SIZE_1;
CLK_OSZI_UDS_000_delay: DELAY CLK_OSZI UDS_000;
CLK_OSZI_UDS_000_delay: DELAY CLK_OSZI UDS_000;
CLK_OSZI_AMIGA_BUS_DATA_DIR_delay: DELAY CLK_OSZI AMIGA_BUS_DATA_DIR;
CLK_OSZI_AMIGA_BUS_DATA_DIR_delay: DELAY CLK_OSZI AMIGA_BUS_DATA_DIR;
CLK_OSZI_AMIGA_BUS_ENABLE_HIGH_delay: DELAY CLK_OSZI AMIGA_BUS_ENABLE_HIGH;
CLK_OSZI_AMIGA_BUS_ENABLE_HIGH_delay: DELAY CLK_OSZI AMIGA_BUS_ENABLE_HIGH;
CLK_OSZI_AMIGA_BUS_ENABLE_HIGH_delay: DELAY CLK_OSZI AMIGA_BUS_ENABLE_HIGH;
CLK_OSZI_AMIGA_BUS_ENABLE_LOW_delay: DELAY CLK_OSZI AMIGA_BUS_ENABLE_LOW;
CLK_OSZI_AMIGA_BUS_ENABLE_LOW_delay: DELAY CLK_OSZI AMIGA_BUS_ENABLE_LOW;
CLK_OSZI_CLK_DIV_OUT_delay: DELAY CLK_OSZI CLK_DIV_OUT;
CLK_OSZI_CLK_EXP_delay: DELAY CLK_OSZI CLK_EXP;
CLK_OSZI_A0_delay: DELAY CLK_OSZI A0;
CLK_OSZI_AS_030_delay: DELAY CLK_OSZI AS_030;
CLK_OSZI_BGACK_030_delay: DELAY CLK_OSZI BGACK_030;
CLK_OSZI_BG_000_delay: DELAY CLK_OSZI BG_000;
CLK_OSZI_DSACK1_delay: DELAY CLK_OSZI DSACK1;
CLK_OSZI_DS_030_delay: DELAY CLK_OSZI DS_030;
CLK_OSZI_E_delay: DELAY CLK_OSZI E;
CLK_OSZI_IPL_030_0_delay: DELAY CLK_OSZI IPL_030_0;
CLK_OSZI_IPL_030_1_delay: DELAY CLK_OSZI IPL_030_1;
CLK_OSZI_IPL_030_2_delay: DELAY CLK_OSZI IPL_030_2;
CLK_OSZI_RESET_delay: DELAY CLK_OSZI RESET;
CLK_OSZI_RW_delay: DELAY CLK_OSZI RW;
CLK_OSZI_RW_000_delay: DELAY CLK_OSZI RW_000;
CLK_OSZI_VMA_delay: DELAY CLK_OSZI VMA;
CLK_OSZI_AMIGA_ADDR_ENABLE_delay: DELAY CLK_OSZI AMIGA_ADDR_ENABLE;

/* timing check arc definitions */

ENDMODEL
