|--------------------------------------------|
|- ispLEVER Fitter Report File              -|
|- Version 1.7.00.05.28.13                       -|
|- (c)Copyright, Lattice Semiconductor 2002 -|
|--------------------------------------------|




Project_Summary
~~~~~~~~~~~~~~~

Project Name :          68030_tk
Project Path :          C:\Users\Matze\Documents\GitHub\68030tk\Logic
Project Fitted on :     Sun Feb 01 21:36:55 2015

Device :                M4A5-128/64
Package :               100TQFP
Speed :                 -10
Partnumber :            M4A5-128/64-10VC
Source Format :         Pure_VHDL


// Project '68030_tk' was Fitted Successfully! //


Compilation_Times
~~~~~~~~~~~~~~~~~
Reading/DRC                                   0 sec
Partition                                     0 sec
Place                                         0 sec
Route                                         0 sec
Jedec/Report generation                       0 sec
                                         --------
Fitter                                   00:00:00


Design_Summary
~~~~~~~~~~~~~~
  Total Input Pins :                 32
  Total Output Pins :                18
  Total Bidir I/O Pins :             11
  Total Flip-Flops :                 80
  Total Product Terms :             179
  Total Reserved Pins :               0
  Total Reserved Blocks :             0


Device_Resource_Summary
~~~~~~~~~~~~~~~~~~~~~~~
                                 Total
                               Available  Used  Available  Utilization
Dedicated Pins
  Input-Only Pins                 2        2      0    -->   100%
  Clock/Input Pins                4        4      0    -->   100%
I/O Pins                         64       55      9    -->    85%
Logic Macrocells                128       97     31    -->    75%
  Input Registers                64        0     64    -->     0%
  Unusable Macrocells            ..        0     ..

CSM Outputs/Total Block Inputs  264      235     29    -->    89%
Logical Product Terms           640      180    460    -->    28%
Product Term Clusters           128       44     84    -->    34%


Blocks_Resource_Summary
~~~~~~~~~~~~~~~~~~~~~~~
                                                                  # of PT  
                   I/O    Inp    Macrocells   Macrocells   logic  clusters 
          Fanin    Pins   Reg   Used Unusable  available    PTs   available  Pwr
---------------------------------------------------------------------------------
Maximum     33      8      8     --     --         16       80       16       -
---------------------------------------------------------------------------------
Block  A    28      8      0     15      0          1       25       11       Lo 
Block  B    31      8      0     10      0          6       18        9       Lo 
Block  C    28      7      0     15      0          1       29       10       Lo 
Block  D    29      8      0     14      0          2       19       12       Lo 
Block  E    31      4      0      9      0          7       12       13       Lo 
Block  F    29      5      0     10      0          6       34        5       Lo 
Block  G    27      7      0     15      0          1       25       12       Lo 
Block  H    32      8      0      9      0          7       18       12       Lo 
---------------------------------------------------------------------------------

<Note> Four rightmost columns above reflect last status of the placement process.
<Note> Pwr (Power) : Hi = High
                     Lo = Low.


Optimizer_and_Fitter_Options
~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Pin Assignment :                       Yes
Group Assignment :                     No
Pin Reservation :                      No (1)
Block Reservation :                    No

@Ignore_Project_Constraints :
  Pin Assignments :                    No
      Keep Block Assignment            --
      Keep Segment Assignment          --
  Group Assignments :                  No
  Macrocell Assignment :               No
      Keep Block Assignment            --
      Keep Segment Assignment          --

@Backannotate_Project_Constraints
  Pin Assignments :                    No
  Pin And Block Assignments :          No
  Pin, Macrocell and Block :           No

@Timing_Constraints :                  No

@Global_Project_Optimization :
  Balanced Partitioning :              Yes
  Spread Placement :                   Yes

  Note :
    Pack Design :
       Balanced Partitioning = No
       Spread Placement      = No
    Spread Design :
       Balanced Partitioning = Yes
       Spread Placement      = Yes

@Logic_Synthesis :
  Logic Reduction :                    Yes
  Node Collapsing :                    Yes
  D/T Synthesis :                      Yes
  Clock Optimization :                 No
  Input Register Optimization :        Yes
  XOR Synthesis :                      Yes
  Max. P-Term for Collapsing :         16
  Max. P-Term for Splitting :          16
  Max. Equation Fanin :                32
  Keep Xor :                           Yes

@Utilization_options
  Max. % of macrocells used :          100
  Max. % of block inputs used :        100
  Max. % of segment lines used :       ---
  Max. % of macrocells used :          ---


@Import_Source_Constraint_Option       No

@Zero_Hold_Time                        Yes

@Pull_up                               Yes

@User_Signature                        #H0

@Output_Slew_Rate                      Default = Slow(2)

@Power                                 Default = High(2)


Device Options:
<Note> 1 : Reserved unused I/Os can be independently driven to Low or High, and does not
           follow the drive level set for the Global Configure Unused I/O Option.
<Note> 2 : For user-specified constraints on individual signals, refer to the Output, 
           Bidir and Burried Signal Lists.




Pinout_Listing
~~~~~~~~~~~~~~
      | Pin  |Blk |Assigned|
Pin No| Type |Pad |Pin     | Signal name
---------------------------------------------------------------
    1 |  GND |    |        |
    2 | JTAG |    |        |
    3 |  I_O | B7 |   *    |RESET
4     |  I_O | B6 |   *    |A_31_
5     |  I_O | B5 |   *    |A_30_
6     |  I_O | B4 |   *    |A_29_
7     |  I_O | B3 |   *    |IPL_030_1_
8     |  I_O | B2 |   *    |IPL_030_0_
9     |  I_O | B1 |   *    |IPL_030_2_
10    |  I_O | B0 |   *    |CLK_EXP
11    | CkIn |    |   *    |CLK_000
12    |  Vcc |    |        |
13    |  GND |    |        |
14    | CkIn |    |   *    |nEXP_SPACE
15    |  I_O | C0 |   *    |A_28_
16    |  I_O | C1 |   *    |A_27_
17    |  I_O | C2 |   *    |A_26_
18    |  I_O | C3 |   *    |A_25_
19    |  I_O | C4 |   *    |A_24_
20    |  I_O | C5 |   *    |AMIGA_BUS_ENABLE_LOW
21    |  I_O | C6 |   *    |BG_030
22    |  I_O | C7 |        |
23    | JTAG |    |        |
24    | JTAG |    |        |
25    |  GND |    |        |
26    |  GND |    |        |
27    |  GND |    |        |
28    |  I_O | D7 |   *    |BGACK_000
29    |  I_O | D6 |   *    |BG_000
30    |  I_O | D5 |   *    |DTACK
31    |  I_O | D4 |   *    |LDS_000
32    |  I_O | D3 |   *    |UDS_000
33    |  I_O | D2 |   *    |AMIGA_ADDR_ENABLE
34    |  I_O | D1 |   *    |AMIGA_BUS_ENABLE_HIGH
35    |  I_O | D0 |   *    |VMA
36    |  Inp |    |   *    |VPA
37    |  Vcc |    |        |
38    |  GND |    |        |
39    |  GND |    |        |
40    |  Vcc |    |        |
41    |  I_O | E0 |   *    |BERR
42    |  I_O | E1 |   *    |AS_000
43    |  I_O | E2 |        |
44    |  I_O | E3 |        |
45    |  I_O | E4 |        |
46    |  I_O | E5 |        |
47    |  I_O | E6 |   *    |CIIN
48    |  I_O | E7 |   *    |AMIGA_BUS_DATA_DIR
49    |  GND |    |        |
50    |  GND |    |        |
51    |  GND |    |        |
52    | JTAG |    |        |
53    |  I_O | F7 |        |
54    |  I_O | F6 |        |
55    |  I_O | F5 |        |
56    |  I_O | F4 |   *    |IPL_1_
57    |  I_O | F3 |   *    |FC_0_
58    |  I_O | F2 |   *    |FC_1_
59    |  I_O | F1 |   *    |A_17_
60    |  I_O | F0 |   *    |A1
61    | CkIn |    |   *    |CLK_OSZI
62    |  Vcc |    |        |
63    |  GND |    |        |
64    | CkIn |    |   *    |CLK_030
65    |  I_O | G0 |   *    |CLK_DIV_OUT
66    |  I_O | G1 |   *    |E
67    |  I_O | G2 |   *    |IPL_0_
68    |  I_O | G3 |   *    |IPL_2_
69    |  I_O | G4 |   *    |A0
70    |  I_O | G5 |   *    |SIZE_0_
71    |  I_O | G6 |   *    |RW
72    |  I_O | G7 |        |
73    | JTAG |    |        |
74    | JTAG |    |        |
75    |  GND |    |        |
76    |  GND |    |        |
77    |  GND |    |        |
78    |  I_O | H7 |   *    |FPU_CS
79    |  I_O | H6 |   *    |SIZE_1_
80    |  I_O | H5 |   *    |RW_000
81    |  I_O | H4 |   *    |DSACK1
82    |  I_O | H3 |   *    |AS_030
83    |  I_O | H2 |   *    |BGACK_030
84    |  I_O | H1 |   *    |A_22_
85    |  I_O | H0 |   *    |A_23_
86    |  Inp |    |   *    |RST
87    |  Vcc |    |        |
88    |  GND |    |        |
89    |  GND |    |        |
90    |  Vcc |    |        |
91    |  I_O | A0 |   *    |FPU_SENSE
92    |  I_O | A1 |   *    |AVEC
93    |  I_O | A2 |   *    |A_20_
94    |  I_O | A3 |   *    |A_21_
95    |  I_O | A4 |   *    |A_18_
96    |  I_O | A5 |   *    |A_16_
97    |  I_O | A6 |   *    |A_19_
98    |  I_O | A7 |   *    |DS_030
99    |  GND |    |        |
100   |  GND |    |        |

---------------------------------------------------------------------------

<Note> Blk Pad : This notation refers to the Block I/O pad number in the device.
<Note> Assigned Pin : user or dedicated input assignment (E.g. Clock pins).
<Note> Pin Type : 
           CkIn : Dedicated input or clock pin 
           CLK  : Dedicated clock pin
           INP  : Dedicated input pin
           JTAG : JTAG Control and test pin
           NC   : No connected



Input_Signal_List
~~~~~~~~~~~~~~~~~
                 P R
            Pin  r e O   Input 
Pin Blk PTs Type e s E   Fanout    Pwr Slew      Signal 
----------------------------------------------------------------------
 60  F   .  I/O          AB------  Low Slow      A1   
 96  A   .  I/O          ----EF-H  Low Slow      A_16_   
 59  F   .  I/O          ----EF-H  Low Slow      A_17_   
 95  A   .  I/O          ----EF-H  Low Slow      A_18_   
 97  A   .  I/O          ----EF-H  Low Slow      A_19_   
 93  A   .  I/O          ----E---  Low Slow      A_20_   
 94  A   .  I/O          ----E---  Low Slow      A_21_   
 84  H   .  I/O          ----E---  Low Slow      A_22_   
 85  H   .  I/O          ----E---  Low Slow      A_23_   
 19  C   .  I/O          ----E---  Low Slow      A_24_   
 18  C   .  I/O          ----E---  Low Slow      A_25_   
 17  C   .  I/O          ----E---  Low Slow      A_26_   
 16  C   .  I/O          ----E---  Low Slow      A_27_   
 15  C   .  I/O          ----E---  Low Slow      A_28_   
  6  B   .  I/O          ----E---  Low Slow      A_29_   
  5  B   .  I/O          ----E---  Low Slow      A_30_   
  4  B   .  I/O          ----E---  Low Slow      A_31_   
 28  D   .  I/O          ----EF-H  Low Slow      BGACK_000   
 21  C   .  I/O          ---D----  Low Slow      BG_030   
 30  D   .  I/O          ------G-  Low Slow      DTACK   
 57  F   .  I/O          ----EF-H  Low Slow      FC_0_   
 58  F   .  I/O          ----EF-H  Low Slow      FC_1_   
 91  A   .  I/O          ----E--H  Low Slow      FPU_SENSE   
 67  G   .  I/O          -B------  Low Slow      IPL_0_   
 56  F   .  I/O          -B------  Low Slow      IPL_1_   
 68  G   .  I/O          -B------  Low Slow      IPL_2_   
 11  .   . Ck/I          ------G-   -  Slow      CLK_000   
 14  .   . Ck/I          --C-----   -  Slow      nEXP_SPACE   
 36  .   .  Ded          --C-----   -  Slow      VPA   
 61  .   . Ck/I          ABCDEFGH   -  Slow      CLK_OSZI   
 64  .   . Ck/I          A------H   -  Slow      CLK_030   
 86  .   .  Ded          ABCD-FGH   -  Slow      RST   
----------------------------------------------------------------------

<Note> Power : Hi = High
               MH = Medium High
               ML = Medium Low
               Lo = Low



Output_Signal_List
~~~~~~~~~~~~~~~~~~
                 P R
            Pin  r e O   Output 
Pin Blk PTs Type e s E   Fanout    Pwr Slew      Signal 
----------------------------------------------------------------------
 33  D   3  DFF  *       --------  Low Fast      AMIGA_ADDR_ENABLE   
 48  E   2  COM          --------  Low Fast      AMIGA_BUS_DATA_DIR   
 34  D   2  COM          --------  Low Fast      AMIGA_BUS_ENABLE_HIGH   
 20  C   1  COM          --------  Low Fast      AMIGA_BUS_ENABLE_LOW   
 92  A   1  COM          --------  Low Slow      AVEC   
 83  H   2  DFF  *       --------  Low Slow      BGACK_030   
 29  D   2  DFF  *       --------  Low Slow      BG_000   
 47  E   1  COM          --------  Low Slow      CIIN   
 65  G   1  COM          --------  Low Fast      CLK_DIV_OUT   
 10  B   1  COM          --------  Low Fast      CLK_EXP   
 81  H   4  DFF  *       --------  Low Slow      DSACK1   
 66  G   5  DFF          --------  Low Slow      E   
 78  H   1  COM          --------  Low Fast      FPU_CS   
  8  B   2  DFF  *       --------  Low Slow      IPL_030_0_   
  7  B   2  DFF  *       --------  Low Slow      IPL_030_1_   
  9  B   2  DFF  *       --------  Low Slow      IPL_030_2_   
  3  B   2  DFF    *     --------  Low Slow      RESET   
 35  D   2  TFF  *       --------  Low Slow      VMA   
----------------------------------------------------------------------

<Note> Power : Hi = High
               MH = Medium High
               ML = Medium Low
               Lo = Low



Bidir_Signal_List
~~~~~~~~~~~~~~~~~
                 P R
            Pin  r e O   Bidir 
Pin Blk PTs Type e s E   Fanout    Pwr Slew      Signal 
----------------------------------------------------------------------
 69  G   1  DFF  *       -B----G-  Low Slow      A0   
 42  E   1  COM          AB--E-GH  Low Slow      AS_000   
 82  H   4  DFF  *       ----E--H  Low Slow      AS_030   
 41  E   1  COM          --C--F-H  Low Slow      BERR   
 98  A   6  DFF  *       ---D----  Low Slow      DS_030   
 31  D   1  COM          AB----GH  Low Slow      LDS_000   
 71  G   2  DFF  *       -----F-H  Low Slow      RW   
 80  H   3  DFF  *       A---E-G-  Low Slow      RW_000   
 70  G   1  COM          -B------  Low Slow      SIZE_0_   
 79  H   1  COM          -B------  Low Slow      SIZE_1_   
 32  D   1  COM          AB----GH  Low Slow      UDS_000   
----------------------------------------------------------------------

<Note> Power : Hi = High
               MH = Medium High
               ML = Medium Low
               Lo = Low



Buried_Signal_List
~~~~~~~~~~~~~~~~~~
                 P R
            Pin  r e O   Node 
#Mc Blk PTs Type e s E   Fanout    Pwr Slew      Signal 
----------------------------------------------------------------------
 E5  E   2  COM          ----E---  Low Slow      CIIN_0   
 D14  D   1  DFF          --C-----  Low Slow      CLK_000_N_SYNC_0_   
 B13  B   1  DFF          -B-----H  Low Slow      CLK_000_N_SYNC_10_   
 B6  B   1  DFF          ----E---  Low Slow      CLK_000_N_SYNC_11_   
 C10  C   1  DFF          ------G-  Low Slow      CLK_000_N_SYNC_1_   
 G7  G   1  DFF          ---D----  Low Slow      CLK_000_N_SYNC_2_   
 D10  D   1  DFF          A-------  Low Slow      CLK_000_N_SYNC_3_   
 A10  A   1  DFF          ------G-  Low Slow      CLK_000_N_SYNC_4_   
 G3  G   1  DFF          --C-----  Low Slow      CLK_000_N_SYNC_5_   
 C6  C   1  DFF          -----F--  Low Slow      CLK_000_N_SYNC_6_   
 F2  F   1  DFF          ------G-  Low Slow      CLK_000_N_SYNC_7_   
 G14  G   1  DFF          ------G-  Low Slow      CLK_000_N_SYNC_8_   
 G6  G   1  DFF          -B-----H  Low Slow      CLK_000_N_SYNC_9_   
 D7  D   1  DFF          -----F--  Low Slow      CLK_000_P_SYNC_0_   
 F6  F   1  DFF          ---D----  Low Slow      CLK_000_P_SYNC_1_   
 D3  D   1  DFF          --C-----  Low Slow      CLK_000_P_SYNC_2_   
 C7  C   1  DFF          A-------  Low Slow      CLK_000_P_SYNC_3_   
 A7  A   1  DFF          --C-----  Low Slow      CLK_000_P_SYNC_4_   
 C3  C   1  DFF          --C-----  Low Slow      CLK_000_P_SYNC_5_   
 C14  C   1  DFF          A-------  Low Slow      CLK_000_P_SYNC_6_   
 A3  A   1  DFF          A-------  Low Slow      CLK_000_P_SYNC_7_   
 A14  A   1  DFF          --C-----  Low Slow      CLK_000_P_SYNC_8_   
 C11  C   1  DFF          ------G-  Low Slow      CLK_000_P_SYNC_9_   
 G13  G   1  DFF          -B----GH  Low Slow      CLK_OUT_PRE_Dreg   
 D9  D   1  TFF    *     AB-D----  Low Slow      RESET_DLY_0_   
 D13  D   1  TFF    *     AB------  Low Slow      RESET_DLY_1_   
 A13  A   1  TFF    *     AB------  Low Slow      RESET_DLY_2_   
 A9  A   1  TFF    *     AB------  Low Slow      RESET_DLY_3_   
 A5  A   1  TFF    *     AB------  Low Slow      RESET_DLY_4_   
 A1  A   1  TFF    *     AB------  Low Slow      RESET_DLY_5_   
 A12  A   1  TFF    *     AB------  Low Slow      RESET_DLY_6_   
 A11  A   1  TFF    *     -B------  Low Slow      RESET_DLY_7_   
 D4  D   3  DFF  *       ---D----  Low  -        RN_AMIGA_ADDR_ENABLE   --> AMIGA_ADDR_ENABLE
 H8  H   4  DFF  *       A------H  Low  -        RN_AS_030   --> AS_030
 H4  H   2  DFF  *       ABCDE-GH  Low  -        RN_BGACK_030   --> BGACK_030
 D1  D   2  DFF  *       ---D----  Low  -        RN_BG_000   --> BG_000
 H9  H   4  DFF  *       -------H  Low  -        RN_DSACK1   --> DSACK1
 A0  A   6  DFF  *       A-------  Low  -        RN_DS_030   --> DS_030
 G4  G   5  DFF          A-CD--G-  Low  -        RN_E   --> E
 B8  B   2  DFF  *       -B------  Low  -        RN_IPL_030_0_   --> IPL_030_0_
 B12  B   2  DFF  *       -B------  Low  -        RN_IPL_030_1_   --> IPL_030_1_
 B4  B   2  DFF  *       -B------  Low  -        RN_IPL_030_2_   --> IPL_030_2_
 B0  B   2  DFF    *     -B------  Low  -        RN_RESET   --> RESET
 H0  H   3  DFF  *       -------H  Low  -        RN_RW_000   --> RW_000
 D0  D   2  TFF  *       --CD----  Low  -        RN_VMA   --> VMA
 B9  B   2  DFF  *       ------GH  Low Slow      SIZE_DMA_0_   
 H13  H   1  DFF  *       ------GH  Low Slow      SIZE_DMA_1_   
 F13  F   2  DFF    *     -----F-H  Low Slow      SM_AMIGA_0_   
 F9  F   2  DFF    *     -----F-H  Low Slow      SM_AMIGA_1_   
 C5  C   3  DFF    *     --C--F--  Low Slow      SM_AMIGA_2_   
 C1  C   6  DFF    *     --C--F--  Low Slow      SM_AMIGA_3_   
 F5  F   2  DFF    *     --C--F--  Low Slow      SM_AMIGA_4_   
 F8  F   2  DFF    *     --C--F-H  Low Slow      SM_AMIGA_5_   
 F4  F   2  DFF    *     -B---FG-  Low Slow      SM_AMIGA_6_   
 F0  F  13  DFF  *       ---D-F-H  Low Slow      SM_AMIGA_7_   
 A8  A   2  DFF          A-CD--G-  Low Slow      cpu_est_0_   
 C8  C   5  DFF          A-CD--G-  Low Slow      cpu_est_1_   
 G5  G   4  DFF          A-CD--G-  Low Slow      cpu_est_2_   
 A6  A   2  DFF  *       ---D----  Low Slow      inst_AMIGA_BUS_ENABLE_DMA_HIGH   
 B2  B   2  DFF  *       --C-----  Low Slow      inst_AMIGA_BUS_ENABLE_DMA_LOW   
 C9  C   2  DFF  *       --C-E---  Low Slow      inst_AS_000_INT   
 F12  F   6  DFF  *       ---D-F--  Low Slow      inst_AS_030_000_SYNC   
 H5  H   1  DFF  *       --CDEF-H  Low Slow      inst_AS_030_D0   
 H2  H   1  DFF  *       ---D----  Low Slow      inst_BGACK_030_INT_D   
 G10  G   1  DFF          ---D-F--  Low Slow      inst_CLK_000_D0   
 D2  D   1  DFF          ---D-F--  Low Slow      inst_CLK_000_D1   
 E8  E   1  DFF          -BCD-F--  Low Slow      inst_CLK_000_NE   
 C12  C   1  DFF          A-CD--G-  Low Slow      inst_CLK_000_NE_D0   
 G9  G   1  DFF          --CD-F-H  Low Slow      inst_CLK_000_PE   
 A2  A   4  DFF    *     A-------  Low Slow      inst_CLK_030_H   
 E13  E   1  DFF          ------G-  Low Slow      inst_CLK_OUT_PRE   
 E2  E   1  DFF          ----E---  Low Slow      inst_CLK_OUT_PRE_50   
 F1  F   3  DFF    *     ---D-F--  Low Slow      inst_DS_000_ENABLE   
 D6  D   1  DFF  *       -B----G-  Low Slow      inst_DS_030_D0   
 G11  G   1  DFF  *       --C-----  Low Slow      inst_DTACK_D0   
 B5  B   3  DFF  *       -B-D----  Low Slow      inst_LDS_000_INT   
 G2  G   3  DFF  *       ---D--G-  Low Slow      inst_UDS_000_INT   
 C13  C   1  DFF  *       --CD----  Low Slow      inst_VPA_D   
 C4  C   1  DFF  *       A--DEFGH  Low Slow      inst_nEXP_SPACE_D0reg   
 C2  C   2  COM          -----F--  Low Slow      state_machine_un15_clk_000_ne_i_n   
 E9  E   2  COM          ----E---  Low Slow      un8_ciin   
----------------------------------------------------------------------

<Note> Power : Hi = High
               MH = Medium High
               ML = Medium Low
               Lo = Low




Signals_Fanout_List
~~~~~~~~~~~~~~~~~~~
Signal Source  :    Fanout List
-----------------------------------------------------------------------------
      A_23_{ I}:           CIIN{ E}         CIIN_0{ E}
      A_22_{ I}:           CIIN{ E}         CIIN_0{ E}
    SIZE_1_{ I}:inst_LDS_000_INT{ B}
      A_21_{ B}:           CIIN{ E}         CIIN_0{ E}
      A_20_{ B}:           CIIN{ E}         CIIN_0{ E}
      A_31_{ C}:           CIIN{ E}       un8_ciin{ E}         CIIN_0{ E}
      A_19_{ B}:           BERR{ E}         FPU_CS{ H}inst_AS_030_000_SYNC{ F}
      A_18_{ B}:           BERR{ E}         FPU_CS{ H}inst_AS_030_000_SYNC{ F}
      A_17_{ G}:           BERR{ E}         FPU_CS{ H}inst_AS_030_000_SYNC{ F}
      A_16_{ B}:           BERR{ E}         FPU_CS{ H}inst_AS_030_000_SYNC{ F}
     IPL_2_{ H}:     IPL_030_2_{ B}
      FC_1_{ G}:           BERR{ E}         FPU_CS{ H}inst_AS_030_000_SYNC{ F}
     IPL_1_{ G}:     IPL_030_1_{ B}
     IPL_0_{ H}:     IPL_030_0_{ B}
     AS_000{ F}:AMIGA_BUS_DATA_DIR{ E}         AS_030{ H}         DS_030{ A}
               :             A0{ G}             RW{ G}inst_AMIGA_BUS_ENABLE_DMA_LOW{ B}
               :    SIZE_DMA_0_{ B}    SIZE_DMA_1_{ H}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ A}
               : inst_CLK_030_H{ A}
      FC_0_{ G}:           BERR{ E}         FPU_CS{ H}inst_AS_030_000_SYNC{ F}
    UDS_000{ E}:         AS_030{ H}         DS_030{ A}             A0{ G}
               :             RW{ G}inst_AMIGA_BUS_ENABLE_DMA_LOW{ B}    SIZE_DMA_0_{ B}
               :    SIZE_DMA_1_{ H}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ A} inst_CLK_030_H{ A}
    LDS_000{ E}:         AS_030{ H}         DS_030{ A}             A0{ G}
               :             RW{ G}inst_AMIGA_BUS_ENABLE_DMA_LOW{ B}    SIZE_DMA_0_{ B}
               :    SIZE_DMA_1_{ H}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ A} inst_CLK_030_H{ A}
         A1{ G}:inst_AMIGA_BUS_ENABLE_DMA_LOW{ B}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ A}
 nEXP_SPACE{. }:inst_nEXP_SPACE_D0reg{ C}
       BERR{ F}:         RW_000{ H}         DSACK1{ H}inst_AS_000_INT{ C}
               :inst_AS_030_000_SYNC{ F}    SM_AMIGA_7_{ F}    SM_AMIGA_5_{ F}
               :    SM_AMIGA_3_{ C}    SM_AMIGA_0_{ F}    SM_AMIGA_6_{ F}
               :inst_DS_000_ENABLE{ F}    SM_AMIGA_1_{ F}    SM_AMIGA_4_{ F}
               :    SM_AMIGA_2_{ C}
     BG_030{ D}:         BG_000{ D}
  BGACK_000{ E}:           BERR{ E}         FPU_CS{ H}      BGACK_030{ H}
               :inst_AS_030_000_SYNC{ F}
    CLK_030{. }:         AS_030{ H}         DS_030{ A}         DSACK1{ H}
               : inst_CLK_030_H{ A}
    CLK_000{. }:inst_CLK_000_D0{ G}
  FPU_SENSE{ B}:           BERR{ E}         FPU_CS{ H}
      DTACK{ E}:  inst_DTACK_D0{ G}
        VPA{. }:     inst_VPA_D{ C}
        RST{. }:     IPL_030_2_{ B}     IPL_030_1_{ B}     IPL_030_0_{ B}
               :         AS_030{ H}         RW_000{ H}         DS_030{ A}
               :             A0{ G}         BG_000{ D}      BGACK_030{ H}
               :         DSACK1{ H}            VMA{ D}          RESET{ B}
               :             RW{ G}AMIGA_ADDR_ENABLE{ D}inst_AS_000_INT{ C}
               :inst_AMIGA_BUS_ENABLE_DMA_LOW{ B} inst_AS_030_D0{ H}inst_nEXP_SPACE_D0reg{ C}
               : inst_DS_030_D0{ D}inst_AS_030_000_SYNC{ F}inst_BGACK_030_INT_D{ H}
               :    SIZE_DMA_0_{ B}    SIZE_DMA_1_{ H}     inst_VPA_D{ C}
               :inst_UDS_000_INT{ G}inst_LDS_000_INT{ B}  inst_DTACK_D0{ G}
               :    SM_AMIGA_7_{ F}    SM_AMIGA_5_{ F}    SM_AMIGA_3_{ C}
               :    SM_AMIGA_0_{ F}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ A}    SM_AMIGA_6_{ F}
               :   RESET_DLY_0_{ D}   RESET_DLY_1_{ D}   RESET_DLY_2_{ A}
               :   RESET_DLY_3_{ A}   RESET_DLY_4_{ A}   RESET_DLY_5_{ A}
               :   RESET_DLY_6_{ A}   RESET_DLY_7_{ A} inst_CLK_030_H{ A}
               :inst_DS_000_ENABLE{ F}    SM_AMIGA_1_{ F}    SM_AMIGA_4_{ F}
               :    SM_AMIGA_2_{ C}
    SIZE_0_{ H}:inst_LDS_000_INT{ B}
      A_30_{ C}:           CIIN{ E}       un8_ciin{ E}         CIIN_0{ E}
      A_29_{ C}:           CIIN{ E}       un8_ciin{ E}         CIIN_0{ E}
      A_28_{ D}:           CIIN{ E}       un8_ciin{ E}         CIIN_0{ E}
      A_27_{ D}:           CIIN{ E}       un8_ciin{ E}         CIIN_0{ E}
      A_26_{ D}:           CIIN{ E}       un8_ciin{ E}         CIIN_0{ E}
      A_25_{ D}:           CIIN{ E}       un8_ciin{ E}         CIIN_0{ E}
      A_24_{ D}:           CIIN{ E}       un8_ciin{ E}         CIIN_0{ E}
RN_IPL_030_2_{ C}:     IPL_030_2_{ B}
RN_IPL_030_1_{ C}:     IPL_030_1_{ B}
RN_IPL_030_0_{ C}:     IPL_030_0_{ B}
     AS_030{ I}:         AS_000{ E}           BERR{ E}         FPU_CS{ H}
               : inst_AS_030_D0{ H}       un8_ciin{ E}
  RN_AS_030{ I}:         AS_030{ H}         DS_030{ A} inst_CLK_030_H{ A}
     RW_000{ I}:AMIGA_BUS_DATA_DIR{ E}         DS_030{ A}             RW{ G}
  RN_RW_000{ I}:         RW_000{ H}
     DS_030{ B}:        UDS_000{ D}        LDS_000{ D} inst_DS_030_D0{ D}
  RN_DS_030{ B}:         DS_030{ A}
         A0{ H}:inst_UDS_000_INT{ G}inst_LDS_000_INT{ B}
  RN_BG_000{ E}:         BG_000{ D}
RN_BGACK_030{ I}:        SIZE_1_{ H}         AS_000{ E}        UDS_000{ D}
               :        LDS_000{ D}AMIGA_BUS_DATA_DIR{ E}AMIGA_BUS_ENABLE_LOW{ C}
               :AMIGA_BUS_ENABLE_HIGH{ D}        SIZE_0_{ G}         AS_030{ H}
               :         RW_000{ H}         DS_030{ A}             A0{ G}
               :      BGACK_030{ H}             RW{ G}AMIGA_ADDR_ENABLE{ D}
               :inst_AMIGA_BUS_ENABLE_DMA_LOW{ B}inst_BGACK_030_INT_D{ H}    SIZE_DMA_0_{ B}
               :    SIZE_DMA_1_{ H}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ A} inst_CLK_030_H{ A}
  RN_DSACK1{ I}:         DSACK1{ H}
       RN_E{ H}:              E{ G}            VMA{ D}     cpu_est_1_{ C}
               :     cpu_est_2_{ G}    SM_AMIGA_3_{ C}   RESET_DLY_0_{ D}
               :   RESET_DLY_1_{ D}   RESET_DLY_2_{ A}   RESET_DLY_3_{ A}
               :   RESET_DLY_4_{ A}   RESET_DLY_5_{ A}   RESET_DLY_6_{ A}
               :   RESET_DLY_7_{ A}    SM_AMIGA_2_{ C}state_machine_un15_clk_000_ne_i_n{ C}
     RN_VMA{ E}:            VMA{ D}    SM_AMIGA_3_{ C}    SM_AMIGA_2_{ C}
               :state_machine_un15_clk_000_ne_i_n{ C}
   RN_RESET{ C}:          RESET{ B}
         RW{ H}:         RW_000{ H}inst_DS_000_ENABLE{ F}
RN_AMIGA_ADDR_ENABLE{ E}:AMIGA_ADDR_ENABLE{ D}
 cpu_est_0_{ B}:              E{ G}            VMA{ D}     cpu_est_0_{ A}
               :     cpu_est_1_{ C}     cpu_est_2_{ G}    SM_AMIGA_3_{ C}
               :   RESET_DLY_0_{ D}   RESET_DLY_1_{ D}   RESET_DLY_2_{ A}
               :   RESET_DLY_3_{ A}   RESET_DLY_4_{ A}   RESET_DLY_5_{ A}
               :   RESET_DLY_6_{ A}   RESET_DLY_7_{ A}    SM_AMIGA_2_{ C}
               :state_machine_un15_clk_000_ne_i_n{ C}
 cpu_est_1_{ D}:              E{ G}            VMA{ D}     cpu_est_1_{ C}
               :     cpu_est_2_{ G}    SM_AMIGA_3_{ C}   RESET_DLY_0_{ D}
               :   RESET_DLY_1_{ D}   RESET_DLY_2_{ A}   RESET_DLY_3_{ A}
               :   RESET_DLY_4_{ A}   RESET_DLY_5_{ A}   RESET_DLY_6_{ A}
               :   RESET_DLY_7_{ A}    SM_AMIGA_2_{ C}state_machine_un15_clk_000_ne_i_n{ C}
inst_AS_000_INT{ D}:         AS_000{ E}inst_AS_000_INT{ C}
inst_AMIGA_BUS_ENABLE_DMA_LOW{ C}:AMIGA_BUS_ENABLE_LOW{ C}
inst_AS_030_D0{ I}:           CIIN{ E}         RW_000{ H}         BG_000{ D}
               :         DSACK1{ H}inst_AS_000_INT{ C}inst_AS_030_000_SYNC{ F}
               :inst_DS_000_ENABLE{ F}         CIIN_0{ E}
inst_nEXP_SPACE_D0reg{ D}:        SIZE_1_{ H}AMIGA_BUS_DATA_DIR{ E}        SIZE_0_{ G}
               :         AS_030{ H}         DS_030{ A}             A0{ G}
               :         BG_000{ D}         DSACK1{ H}AMIGA_ADDR_ENABLE{ D}
               :inst_AS_030_000_SYNC{ F}    SM_AMIGA_7_{ F}    SM_AMIGA_6_{ F}
               :         CIIN_0{ E}
inst_DS_030_D0{ E}:inst_UDS_000_INT{ G}inst_LDS_000_INT{ B}
inst_AS_030_000_SYNC{ G}:AMIGA_ADDR_ENABLE{ D}inst_AS_030_000_SYNC{ F}    SM_AMIGA_7_{ F}
               :    SM_AMIGA_6_{ F}
inst_BGACK_030_INT_D{ I}:AMIGA_ADDR_ENABLE{ D}
SIZE_DMA_0_{ C}:        SIZE_1_{ H}        SIZE_0_{ G}
SIZE_DMA_1_{ I}:        SIZE_1_{ H}        SIZE_0_{ G}
 inst_VPA_D{ D}:            VMA{ D}    SM_AMIGA_3_{ C}    SM_AMIGA_2_{ C}
               :state_machine_un15_clk_000_ne_i_n{ C}
inst_UDS_000_INT{ H}:        UDS_000{ D}inst_UDS_000_INT{ G}
inst_LDS_000_INT{ C}:        LDS_000{ D}inst_LDS_000_INT{ B}
inst_DTACK_D0{ H}:    SM_AMIGA_3_{ C}    SM_AMIGA_2_{ C}state_machine_un15_clk_000_ne_i_n{ C}
inst_CLK_OUT_PRE_50{ F}:inst_CLK_OUT_PRE_50{ E}inst_CLK_OUT_PRE{ E}
inst_CLK_000_D1{ E}:AMIGA_ADDR_ENABLE{ D}    SM_AMIGA_7_{ F}    SM_AMIGA_6_{ F}
               :CLK_000_P_SYNC_0_{ D}CLK_000_N_SYNC_0_{ D}
inst_CLK_000_D0{ H}:         BG_000{ D}AMIGA_ADDR_ENABLE{ D}inst_CLK_000_D1{ D}
               :    SM_AMIGA_7_{ F}    SM_AMIGA_6_{ F}CLK_000_P_SYNC_0_{ D}
               :CLK_000_N_SYNC_0_{ D}
inst_CLK_000_PE{ H}:         RW_000{ H}      BGACK_030{ H}            VMA{ D}
               :    SM_AMIGA_7_{ F}    SM_AMIGA_5_{ F}    SM_AMIGA_3_{ C}
               :    SM_AMIGA_0_{ F}    SM_AMIGA_6_{ F}    SM_AMIGA_1_{ F}
               :    SM_AMIGA_4_{ F}    SM_AMIGA_2_{ C}
SM_AMIGA_7_{ G}:AMIGA_BUS_ENABLE_HIGH{ D}         RW_000{ H}AMIGA_ADDR_ENABLE{ D}
               :inst_AS_030_000_SYNC{ F}    SM_AMIGA_6_{ F}
SM_AMIGA_5_{ G}:         RW_000{ H}inst_AS_000_INT{ C}    SM_AMIGA_7_{ F}
               :    SM_AMIGA_5_{ F}inst_DS_000_ENABLE{ F}    SM_AMIGA_4_{ F}
inst_CLK_OUT_PRE{ F}:CLK_OUT_PRE_Dreg{ G}
inst_CLK_000_NE{ F}:     IPL_030_2_{ B}     IPL_030_1_{ B}     IPL_030_0_{ B}
               :            VMA{ D}    SM_AMIGA_7_{ F}    SM_AMIGA_5_{ F}
               :inst_CLK_000_NE_D0{ C}    SM_AMIGA_3_{ C}    SM_AMIGA_0_{ F}
               :    SM_AMIGA_1_{ F}    SM_AMIGA_4_{ F}    SM_AMIGA_2_{ C}
CLK_000_N_SYNC_11_{ C}:inst_CLK_000_NE{ E}
CLK_000_P_SYNC_9_{ D}:inst_CLK_000_PE{ G}
 cpu_est_2_{ H}:              E{ G}            VMA{ D}     cpu_est_1_{ C}
               :     cpu_est_2_{ G}    SM_AMIGA_3_{ C}   RESET_DLY_0_{ D}
               :   RESET_DLY_1_{ D}   RESET_DLY_2_{ A}   RESET_DLY_3_{ A}
               :   RESET_DLY_4_{ A}   RESET_DLY_5_{ A}   RESET_DLY_6_{ A}
               :   RESET_DLY_7_{ A}    SM_AMIGA_2_{ C}state_machine_un15_clk_000_ne_i_n{ C}
inst_CLK_000_NE_D0{ D}:              E{ G}     cpu_est_0_{ A}     cpu_est_1_{ C}
               :     cpu_est_2_{ G}   RESET_DLY_0_{ D}   RESET_DLY_1_{ D}
               :   RESET_DLY_2_{ A}   RESET_DLY_3_{ A}   RESET_DLY_4_{ A}
               :   RESET_DLY_5_{ A}   RESET_DLY_6_{ A}   RESET_DLY_7_{ A}
SM_AMIGA_3_{ D}:    SM_AMIGA_7_{ F}    SM_AMIGA_3_{ C}inst_DS_000_ENABLE{ F}
               :    SM_AMIGA_2_{ C}
SM_AMIGA_0_{ G}:         RW_000{ H}    SM_AMIGA_7_{ F}    SM_AMIGA_0_{ F}
inst_AMIGA_BUS_ENABLE_DMA_HIGH{ B}:AMIGA_BUS_ENABLE_HIGH{ D}
SM_AMIGA_6_{ G}:inst_UDS_000_INT{ G}inst_LDS_000_INT{ B}    SM_AMIGA_7_{ F}
               :    SM_AMIGA_5_{ F}    SM_AMIGA_6_{ F}
RESET_DLY_0_{ E}:          RESET{ B}   RESET_DLY_1_{ D}   RESET_DLY_2_{ A}
               :   RESET_DLY_3_{ A}   RESET_DLY_4_{ A}   RESET_DLY_5_{ A}
               :   RESET_DLY_6_{ A}   RESET_DLY_7_{ A}
RESET_DLY_1_{ E}:          RESET{ B}   RESET_DLY_2_{ A}   RESET_DLY_3_{ A}
               :   RESET_DLY_4_{ A}   RESET_DLY_5_{ A}   RESET_DLY_6_{ A}
               :   RESET_DLY_7_{ A}
RESET_DLY_2_{ B}:          RESET{ B}   RESET_DLY_3_{ A}   RESET_DLY_4_{ A}
               :   RESET_DLY_5_{ A}   RESET_DLY_6_{ A}   RESET_DLY_7_{ A}
RESET_DLY_3_{ B}:          RESET{ B}   RESET_DLY_4_{ A}   RESET_DLY_5_{ A}
               :   RESET_DLY_6_{ A}   RESET_DLY_7_{ A}
RESET_DLY_4_{ B}:          RESET{ B}   RESET_DLY_5_{ A}   RESET_DLY_6_{ A}
               :   RESET_DLY_7_{ A}
RESET_DLY_5_{ B}:          RESET{ B}   RESET_DLY_6_{ A}   RESET_DLY_7_{ A}
RESET_DLY_6_{ B}:          RESET{ B}   RESET_DLY_7_{ A}
RESET_DLY_7_{ B}:          RESET{ B}
CLK_000_P_SYNC_0_{ E}:CLK_000_P_SYNC_1_{ F}
CLK_000_P_SYNC_1_{ G}:CLK_000_P_SYNC_2_{ D}
CLK_000_P_SYNC_2_{ E}:CLK_000_P_SYNC_3_{ C}
CLK_000_P_SYNC_3_{ D}:CLK_000_P_SYNC_4_{ A}
CLK_000_P_SYNC_4_{ B}:CLK_000_P_SYNC_5_{ C}
CLK_000_P_SYNC_5_{ D}:CLK_000_P_SYNC_6_{ C}
CLK_000_P_SYNC_6_{ D}:CLK_000_P_SYNC_7_{ A}
CLK_000_P_SYNC_7_{ B}:CLK_000_P_SYNC_8_{ A}
CLK_000_P_SYNC_8_{ B}:CLK_000_P_SYNC_9_{ C}
CLK_000_N_SYNC_0_{ E}:CLK_000_N_SYNC_1_{ C}
CLK_000_N_SYNC_1_{ D}:CLK_000_N_SYNC_2_{ G}
CLK_000_N_SYNC_2_{ H}:CLK_000_N_SYNC_3_{ D}
CLK_000_N_SYNC_3_{ E}:CLK_000_N_SYNC_4_{ A}
CLK_000_N_SYNC_4_{ B}:CLK_000_N_SYNC_5_{ G}
CLK_000_N_SYNC_5_{ H}:CLK_000_N_SYNC_6_{ C}
CLK_000_N_SYNC_6_{ D}:CLK_000_N_SYNC_7_{ F}
CLK_000_N_SYNC_7_{ G}:CLK_000_N_SYNC_8_{ G}
CLK_000_N_SYNC_8_{ H}:CLK_000_N_SYNC_9_{ G}
CLK_000_N_SYNC_9_{ H}:         DSACK1{ H}CLK_000_N_SYNC_10_{ B}
CLK_000_N_SYNC_10_{ C}:         DSACK1{ H}CLK_000_N_SYNC_11_{ B}
inst_CLK_030_H{ B}:         DS_030{ A} inst_CLK_030_H{ A}
inst_DS_000_ENABLE{ G}:        UDS_000{ D}        LDS_000{ D}inst_DS_000_ENABLE{ F}
SM_AMIGA_1_{ G}:         DSACK1{ H}    SM_AMIGA_7_{ F}    SM_AMIGA_0_{ F}
               :    SM_AMIGA_1_{ F}
SM_AMIGA_4_{ G}:    SM_AMIGA_7_{ F}    SM_AMIGA_3_{ C}    SM_AMIGA_4_{ F}
SM_AMIGA_2_{ D}:    SM_AMIGA_7_{ F}    SM_AMIGA_1_{ F}    SM_AMIGA_2_{ C}
CLK_OUT_PRE_Dreg{ H}:    CLK_DIV_OUT{ G}        CLK_EXP{ B}         DSACK1{ H}
   un8_ciin{ F}:         CIIN_0{ E}
state_machine_un15_clk_000_ne_i_n{ D}:    SM_AMIGA_7_{ F}
     CIIN_0{ F}:           CIIN{ E}
-----------------------------------------------------------------------------

<Note> {.} : Indicates block location of signal


Set_Reset_Summary
~~~~~~~~~~~~~~~~~

Block  A
block level set pt   : !RST
block level reset pt : 
Equations :
|     |     |Block|Block| Signal
| Reg |Mode |Set  |Reset| Name
+-----+-----+-----+-----+------------------------
|  *  |  S  | BS  | BR  | DS_030
|     |     |     |     | AVEC
|  *  |  S  | BR  | BR  | cpu_est_0_
|  *  |  S  | BR  | BS  | RESET_DLY_6_
|  *  |  S  | BR  | BS  | RESET_DLY_5_
|  *  |  S  | BR  | BS  | RESET_DLY_4_
|  *  |  S  | BR  | BS  | RESET_DLY_3_
|  *  |  S  | BR  | BS  | RESET_DLY_2_
|  *  |  S  | BS  | BR  | RN_DS_030
|  *  |  S  | BR  | BS  | inst_CLK_030_H
|  *  |  S  | BS  | BR  | inst_AMIGA_BUS_ENABLE_DMA_HIGH
|  *  |  S  | BR  | BR  | CLK_000_N_SYNC_4_
|  *  |  S  | BR  | BR  | CLK_000_P_SYNC_8_
|  *  |  S  | BR  | BR  | CLK_000_P_SYNC_7_
|  *  |  S  | BR  | BR  | CLK_000_P_SYNC_4_
|  *  |  S  | BR  | BS  | RESET_DLY_7_
|     |     |     |     | A_19_
|     |     |     |     | A_16_
|     |     |     |     | A_18_
|     |     |     |     | FPU_SENSE
|     |     |     |     | A_21_
|     |     |     |     | A_20_


Block  B
block level set pt   : 
block level reset pt : !RST
Equations :
|     |     |Block|Block| Signal
| Reg |Mode |Set  |Reset| Name
+-----+-----+-----+-----+------------------------
|  *  |  S  | BR  | BS  | IPL_030_2_
|  *  |  S  | BR  | BS  | IPL_030_0_
|  *  |  S  | BR  | BS  | IPL_030_1_
|  *  |  S  | BS  | BR  | RESET
|     |     |     |     | CLK_EXP
|  *  |  S  | BR  | BS  | inst_LDS_000_INT
|  *  |  S  | BR  | BS  | SIZE_DMA_0_
|  *  |  S  | BS  | BS  | CLK_000_N_SYNC_10_
|  *  |  S  | BS  | BR  | RN_RESET
|  *  |  S  | BR  | BS  | RN_IPL_030_0_
|  *  |  S  | BR  | BS  | RN_IPL_030_1_
|  *  |  S  | BR  | BS  | RN_IPL_030_2_
|  *  |  S  | BR  | BS  | inst_AMIGA_BUS_ENABLE_DMA_LOW
|  *  |  S  | BS  | BS  | CLK_000_N_SYNC_11_
|     |     |     |     | A_29_
|     |     |     |     | A_30_
|     |     |     |     | A_31_


Block  C
block level set pt   : 
block level reset pt : !RST
Equations :
|     |     |Block|Block| Signal
| Reg |Mode |Set  |Reset| Name
+-----+-----+-----+-----+------------------------
|     |     |     |     | AMIGA_BUS_ENABLE_LOW
|  *  |  S  | BR  | BS  | inst_nEXP_SPACE_D0reg
|  *  |  S  | BS  | BS  | cpu_est_1_
|  *  |  S  | BS  | BS  | inst_CLK_000_NE_D0
|  *  |  S  | BS  | BR  | SM_AMIGA_3_
|  *  |  S  | BS  | BR  | SM_AMIGA_2_
|  *  |  S  | BR  | BS  | inst_AS_000_INT
|  *  |  S  | BR  | BS  | inst_VPA_D
|     |     |     |     | state_machine_un15_clk_000_ne_i_n
|  *  |  S  | BS  | BS  | CLK_000_N_SYNC_6_
|  *  |  S  | BS  | BS  | CLK_000_N_SYNC_1_
|  *  |  S  | BS  | BS  | CLK_000_P_SYNC_6_
|  *  |  S  | BS  | BS  | CLK_000_P_SYNC_5_
|  *  |  S  | BS  | BS  | CLK_000_P_SYNC_3_
|  *  |  S  | BS  | BS  | CLK_000_P_SYNC_9_
|     |     |     |     | BG_030
|     |     |     |     | A_24_
|     |     |     |     | A_25_
|     |     |     |     | A_26_
|     |     |     |     | A_27_
|     |     |     |     | A_28_


Block  D
block level set pt   : !RST
block level reset pt : 
Equations :
|     |     |Block|Block| Signal
| Reg |Mode |Set  |Reset| Name
+-----+-----+-----+-----+------------------------
|     |     |     |     | UDS_000
|     |     |     |     | LDS_000
|  *  |  S  | BS  | BR  | AMIGA_ADDR_ENABLE
|  *  |  S  | BS  | BR  | VMA
|     |     |     |     | AMIGA_BUS_ENABLE_HIGH
|  *  |  S  | BS  | BR  | BG_000
|  *  |  S  | BR  | BS  | RESET_DLY_0_
|  *  |  S  | BS  | BR  | RN_VMA
|  *  |  S  | BR  | BS  | RESET_DLY_1_
|  *  |  S  | BR  | BR  | inst_CLK_000_D1
|  *  |  S  | BS  | BR  | inst_DS_030_D0
|  *  |  S  | BS  | BR  | RN_AMIGA_ADDR_ENABLE
|  *  |  S  | BS  | BR  | RN_BG_000
|  *  |  S  | BR  | BR  | CLK_000_N_SYNC_3_
|  *  |  S  | BR  | BR  | CLK_000_N_SYNC_0_
|  *  |  S  | BR  | BR  | CLK_000_P_SYNC_2_
|  *  |  S  | BR  | BR  | CLK_000_P_SYNC_0_
|     |     |     |     | BGACK_000
|     |     |     |     | DTACK


Block  E
block level set pt   : 
block level reset pt : 
Equations :
|     |     |Block|Block| Signal
| Reg |Mode |Set  |Reset| Name
+-----+-----+-----+-----+------------------------
|     |     |     |     | AS_000
|     |     |     |     | BERR
|     |     |     |     | AMIGA_BUS_DATA_DIR
|     |     |     |     | CIIN
|  *  |  S  | BS  | BR  | inst_CLK_000_NE
|     |     |     |     | CIIN_0
|     |     |     |     | un8_ciin
|  *  |  S  | BS  | BR  | inst_CLK_OUT_PRE
|  *  |  S  | BS  | BR  | inst_CLK_OUT_PRE_50


Block  F
block level set pt   : !RST
block level reset pt : 
Equations :
|     |     |Block|Block| Signal
| Reg |Mode |Set  |Reset| Name
+-----+-----+-----+-----+------------------------
|  *  |  S  | BS  | BR  | SM_AMIGA_7_
|  *  |  S  | BR  | BS  | SM_AMIGA_6_
|  *  |  S  | BR  | BS  | SM_AMIGA_5_
|  *  |  S  | BS  | BR  | inst_AS_030_000_SYNC
|  *  |  S  | BR  | BS  | inst_DS_000_ENABLE
|  *  |  S  | BR  | BS  | SM_AMIGA_4_
|  *  |  S  | BR  | BS  | SM_AMIGA_1_
|  *  |  S  | BR  | BS  | SM_AMIGA_0_
|  *  |  S  | BR  | BR  | CLK_000_N_SYNC_7_
|  *  |  S  | BR  | BR  | CLK_000_P_SYNC_1_
|     |     |     |     | A_17_
|     |     |     |     | FC_1_
|     |     |     |     | FC_0_
|     |     |     |     | A1
|     |     |     |     | IPL_1_


Block  G
block level set pt   : !RST
block level reset pt : 
Equations :
|     |     |Block|Block| Signal
| Reg |Mode |Set  |Reset| Name
+-----+-----+-----+-----+------------------------
|  *  |  S  | BS  | BR  | RW
|  *  |  S  | BS  | BR  | A0
|     |     |     |     | SIZE_0_
|  *  |  S  | BR  | BR  | E
|     |     |     |     | CLK_DIV_OUT
|  *  |  S  | BR  | BR  | RN_E
|  *  |  S  | BR  | BR  | cpu_est_2_
|  *  |  S  | BR  | BR  | inst_CLK_000_PE
|  *  |  S  | BR  | BR  | CLK_OUT_PRE_Dreg
|  *  |  S  | BS  | BR  | inst_UDS_000_INT
|  *  |  S  | BR  | BR  | CLK_000_N_SYNC_9_
|  *  |  S  | BR  | BR  | inst_CLK_000_D0
|  *  |  S  | BR  | BR  | CLK_000_N_SYNC_8_
|  *  |  S  | BR  | BR  | CLK_000_N_SYNC_5_
|  *  |  S  | BR  | BR  | CLK_000_N_SYNC_2_
|  *  |  S  | BS  | BR  | inst_DTACK_D0
|     |     |     |     | IPL_2_
|     |     |     |     | IPL_0_


Block  H
block level set pt   : !RST
block level reset pt : 
Equations :
|     |     |Block|Block| Signal
| Reg |Mode |Set  |Reset| Name
+-----+-----+-----+-----+------------------------
|  *  |  S  | BS  | BR  | RW_000
|  *  |  S  | BS  | BR  | AS_030
|     |     |     |     | SIZE_1_
|  *  |  S  | BS  | BR  | DSACK1
|  *  |  S  | BS  | BR  | BGACK_030
|     |     |     |     | FPU_CS
|  *  |  S  | BS  | BR  | RN_BGACK_030
|  *  |  S  | BS  | BR  | inst_AS_030_D0
|  *  |  S  | BS  | BR  | RN_AS_030
|  *  |  S  | BS  | BR  | SIZE_DMA_1_
|  *  |  S  | BS  | BR  | RN_DSACK1
|  *  |  S  | BS  | BR  | RN_RW_000
|  *  |  S  | BS  | BR  | inst_BGACK_030_INT_D
|     |     |     |     | A_23_
|     |     |     |     | A_22_


<Note> (S) means the macrocell is configured in synchronous mode
       i.e. it uses the block-level set and reset pt.
       (A) means the macrocell is configured in asynchronous mode
       i.e. it can have its independant set or reset pt.
       (BS) means the block-level set pt is selected.
       (BR) means the block-level reset pt is selected.




BLOCK_A_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM             Signal    Source        CSM             Signal    Source
------------------------------------    ------------------------------------
mx A0             RST        pin 86     mx A17             ...           ...
mx A1    RESET_DLY_1_    mcell  D13     mx A18    RESET_DLY_4_     mcell  A5
mx A2CLK_000_N_SYNC_3_    mcell  D10     mx A19    RESET_DLY_3_     mcell  A9
mx A3              A1        pin 60     mx A20    RN_BGACK_030     mcell  H4
mx A4         CLK_030        pin 64     mx A21          RW_000        pin 80
mx A5             ...           ...     mx A22  inst_CLK_030_H     mcell  A2
mx A6CLK_000_P_SYNC_3_     mcell  C7     mx A23inst_CLK_000_NE_D0    mcell  C12
mx A7CLK_000_P_SYNC_6_    mcell  C14     mx A24    RESET_DLY_6_    mcell  A12
mx A8         UDS_000        pin 32     mx A25CLK_000_P_SYNC_7_     mcell  A3
mx A9    RESET_DLY_5_     mcell  A1     mx A26          AS_000        pin 42
mx A10             ...           ...     mx A27         LDS_000        pin 31
mx A11            RN_E     mcell  G4     mx A28    RESET_DLY_2_    mcell  A13
mx A12    RESET_DLY_0_     mcell  D9     mx A29             ...           ...
mx A13       RN_AS_030     mcell  H8     mx A30      cpu_est_0_     mcell  A8
mx A14inst_nEXP_SPACE_D0reg     mcell  C4     mx A31             ...           ...
mx A15       RN_DS_030     mcell  A0     mx A32      cpu_est_2_     mcell  G5
mx A16      cpu_est_1_     mcell  C8
----------------------------------------------------------------------------


BLOCK_B_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM             Signal    Source        CSM             Signal    Source
------------------------------------    ------------------------------------
mx B0          IPL_0_        pin 67     mx B17   RN_IPL_030_0_     mcell  B8
mx B1   RN_IPL_030_1_    mcell  B12     mx B18              A0        pin 69
mx B2          AS_000        pin 42     mx B19    RESET_DLY_3_     mcell  A9
mx B3          IPL_1_        pin 56     mx B20    RN_BGACK_030     mcell  H4
mx B4  inst_DS_030_D0     mcell  D6     mx B21CLK_000_N_SYNC_10_    mcell  B13
mx B5CLK_000_N_SYNC_9_     mcell  G6     mx B22          IPL_2_        pin 68
mx B6         SIZE_1_        pin 79     mx B23             ...           ...
mx B7    RESET_DLY_0_     mcell  D9     mx B24             RST        pin 86
mx B8         UDS_000        pin 32     mx B25    RESET_DLY_2_    mcell  A13
mx B9    RESET_DLY_5_     mcell  A1     mx B26        RN_RESET     mcell  B0
mx B10     SM_AMIGA_6_     mcell  F4     mx B27         LDS_000        pin 31
mx B11              A1        pin 60     mx B28    RESET_DLY_4_     mcell  A5
mx B12CLK_OUT_PRE_Dreg    mcell  G13     mx B29    RESET_DLY_1_    mcell  D13
mx B13    RESET_DLY_7_    mcell  A11     mx B30   RN_IPL_030_2_     mcell  B4
mx B14         SIZE_0_        pin 70     mx B31inst_LDS_000_INT     mcell  B5
mx B15    RESET_DLY_6_    mcell  A12     mx B32             ...           ...
mx B16 inst_CLK_000_NE     mcell  E8
----------------------------------------------------------------------------


BLOCK_C_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM             Signal    Source        CSM             Signal    Source
------------------------------------    ------------------------------------
mx C0             RST        pin 86     mx C17CLK_000_N_SYNC_0_    mcell  D14
mx C1CLK_000_P_SYNC_4_     mcell  A7     mx C18inst_AMIGA_BUS_ENABLE_DMA_LOW     mcell  B2
mx C2     SM_AMIGA_5_     mcell  F8     mx C19             ...           ...
mx C3CLK_000_P_SYNC_8_    mcell  A14     mx C20    RN_BGACK_030     mcell  H4
mx C4CLK_000_P_SYNC_5_     mcell  C3     mx C21            RN_E     mcell  G4
mx C5      nEXP_SPACE        pin 14     mx C22     SM_AMIGA_3_     mcell  C1
mx C6             ...           ...     mx C23 inst_AS_000_INT     mcell  C9
mx C7     SM_AMIGA_2_     mcell  C5     mx C24CLK_000_N_SYNC_5_     mcell  G3
mx C8 inst_CLK_000_NE     mcell  E8     mx C25            BERR        pin 41
mx C9   inst_DTACK_D0    mcell  G11     mx C26          RN_VMA     mcell  D0
mx C10             VPA        pin 36     mx C27  inst_AS_030_D0     mcell  H5
mx C11      inst_VPA_D    mcell  C13     mx C28             ...           ...
mx C12 inst_CLK_000_PE     mcell  G9     mx C29             ...           ...
mx C13CLK_000_P_SYNC_2_     mcell  D3     mx C30      cpu_est_0_     mcell  A8
mx C14     SM_AMIGA_4_     mcell  F5     mx C31             ...           ...
mx C15inst_CLK_000_NE_D0    mcell  C12     mx C32      cpu_est_2_     mcell  G5
mx C16      cpu_est_1_     mcell  C8
----------------------------------------------------------------------------


BLOCK_D_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM             Signal    Source        CSM             Signal    Source
------------------------------------    ------------------------------------
mx D0      inst_VPA_D    mcell  C13     mx D17       RN_BG_000     mcell  D1
mx D1inst_AS_030_000_SYNC    mcell  F12     mx D18      cpu_est_0_     mcell  A8
mx D2            RN_E     mcell  G4     mx D19             ...           ...
mx D3      cpu_est_2_     mcell  G5     mx D20    RN_BGACK_030     mcell  H4
mx D4          BG_030        pin 21     mx D21             RST        pin 86
mx D5          DS_030        pin 98     mx D22 inst_CLK_000_D0    mcell  G10
mx D6inst_nEXP_SPACE_D0reg     mcell  C4     mx D23inst_CLK_000_NE_D0    mcell  C12
mx D7    RESET_DLY_0_     mcell  D9     mx D24             ...           ...
mx D8 inst_CLK_000_NE     mcell  E8     mx D25     SM_AMIGA_7_     mcell  F0
mx D9             ...           ...     mx D26          RN_VMA     mcell  D0
mx D10RN_AMIGA_ADDR_ENABLE     mcell  D4     mx D27 inst_CLK_000_PE     mcell  G9
mx D11CLK_000_P_SYNC_1_     mcell  F6     mx D28inst_LDS_000_INT     mcell  B5
mx D12CLK_000_N_SYNC_2_     mcell  G7     mx D29      cpu_est_1_     mcell  C8
mx D13  inst_AS_030_D0     mcell  H5     mx D30inst_DS_000_ENABLE     mcell  F1
mx D14inst_BGACK_030_INT_D     mcell  H2     mx D31inst_UDS_000_INT     mcell  G2
mx D15inst_AMIGA_BUS_ENABLE_DMA_HIGH     mcell  A6     mx D32             ...           ...
mx D16 inst_CLK_000_D1     mcell  D2
----------------------------------------------------------------------------


BLOCK_E_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM             Signal    Source        CSM             Signal    Source
------------------------------------    ------------------------------------
mx E0    RN_BGACK_030     mcell  H4     mx E17           FC_0_        pin 57
mx E1           FC_1_        pin 58     mx E18           A_23_        pin 85
mx E2CLK_000_N_SYNC_11_     mcell  B6     mx E19           A_30_         pin 5
mx E3           A_27_        pin 16     mx E20           A_22_        pin 84
mx E4       BGACK_000        pin 28     mx E21           A_29_         pin 6
mx E5           A_21_        pin 94     mx E22           A_25_        pin 18
mx E6inst_nEXP_SPACE_D0reg     mcell  C4     mx E23 inst_AS_000_INT     mcell  C9
mx E7           A_28_        pin 15     mx E24        un8_ciin     mcell  E9
mx E8       FPU_SENSE        pin 91     mx E25           A_31_         pin 4
mx E9           A_26_        pin 17     mx E26          CIIN_0     mcell  E5
mx E10             ...           ...     mx E27           A_17_        pin 59
mx E11           A_16_        pin 96     mx E28          RW_000        pin 80
mx E12           A_19_        pin 97     mx E29           A_20_        pin 93
mx E13  inst_AS_030_D0     mcell  H5     mx E30             ...           ...
mx E14           A_24_        pin 19     mx E31           A_18_        pin 95
mx E15inst_CLK_OUT_PRE_50     mcell  E2     mx E32          AS_030        pin 82
mx E16          AS_000        pin 42
----------------------------------------------------------------------------


BLOCK_F_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM             Signal    Source        CSM             Signal    Source
------------------------------------    ------------------------------------
mx F0             RST        pin 86     mx F17           A_18_        pin 95
mx F1            BERR        pin 41     mx F18     SM_AMIGA_1_     mcell  F9
mx F2     SM_AMIGA_5_     mcell  F8     mx F19             ...           ...
mx F3 inst_CLK_000_D1     mcell  D2     mx F20           FC_1_        pin 58
mx F4       BGACK_000        pin 28     mx F21             ...           ...
mx F5 inst_CLK_000_D0    mcell  G10     mx F22     SM_AMIGA_0_    mcell  F13
mx F6inst_nEXP_SPACE_D0reg     mcell  C4     mx F23             ...           ...
mx F7     SM_AMIGA_2_     mcell  C5     mx F24           FC_0_        pin 57
mx F8CLK_000_P_SYNC_0_     mcell  D7     mx F25     SM_AMIGA_7_     mcell  F0
mx F9CLK_000_N_SYNC_6_     mcell  C6     mx F26           A_16_        pin 96
mx F10 inst_CLK_000_PE     mcell  G9     mx F27           A_17_        pin 59
mx F11              RW        pin 71     mx F28             ...           ...
mx F12           A_19_        pin 97     mx F29     SM_AMIGA_6_     mcell  F4
mx F13  inst_AS_030_D0     mcell  H5     mx F30     SM_AMIGA_3_     mcell  C1
mx F14     SM_AMIGA_4_     mcell  F5     mx F31inst_AS_030_000_SYNC    mcell  F12
mx F15inst_DS_000_ENABLE     mcell  F1     mx F32state_machine_un15_clk_000_ne_i_n     mcell  C2
mx F16 inst_CLK_000_NE     mcell  E8
----------------------------------------------------------------------------


BLOCK_G_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM             Signal    Source        CSM             Signal    Source
------------------------------------    ------------------------------------
mx G0CLK_000_P_SYNC_9_    mcell  C11     mx G17             ...           ...
mx G1             ...           ...     mx G18CLK_000_N_SYNC_1_    mcell  C10
mx G2            RN_E     mcell  G4     mx G19     SIZE_DMA_1_    mcell  H13
mx G3      cpu_est_0_     mcell  A8     mx G20    RN_BGACK_030     mcell  H4
mx G4inst_CLK_000_NE_D0    mcell  C12     mx G21             RST        pin 86
mx G5             ...           ...     mx G22CLK_000_N_SYNC_4_    mcell  A10
mx G6     SIZE_DMA_0_     mcell  B9     mx G23           DTACK        pin 30
mx G7      cpu_est_1_     mcell  C8     mx G24         LDS_000        pin 31
mx G8         UDS_000        pin 32     mx G25             ...           ...
mx G9CLK_000_N_SYNC_7_     mcell  F2     mx G26          AS_000        pin 42
mx G10     SM_AMIGA_6_     mcell  F4     mx G27             ...           ...
mx G11CLK_000_N_SYNC_8_    mcell  G14     mx G28          RW_000        pin 80
mx G12CLK_OUT_PRE_Dreg    mcell  G13     mx G29inst_nEXP_SPACE_D0reg     mcell  C4
mx G13inst_CLK_OUT_PRE    mcell  E13     mx G30             ...           ...
mx G14         CLK_000        pin 11     mx G31inst_UDS_000_INT     mcell  G2
mx G15              A0        pin 69     mx G32      cpu_est_2_     mcell  G5
mx G16  inst_DS_030_D0     mcell  D6
----------------------------------------------------------------------------


BLOCK_H_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM             Signal    Source        CSM             Signal    Source
------------------------------------    ------------------------------------
mx H0         LDS_000        pin 31     mx H17            BERR        pin 41
mx H1           FC_1_        pin 58     mx H18       BGACK_000        pin 28
mx H2     SM_AMIGA_5_     mcell  F8     mx H19          AS_030        pin 82
mx H3       RN_AS_030     mcell  H8     mx H20         CLK_030        pin 64
mx H4           A_18_        pin 95     mx H21             RST        pin 86
mx H5       RN_DSACK1     mcell  H9     mx H22             ...           ...
mx H6           A_16_        pin 96     mx H23    RN_BGACK_030     mcell  H4
mx H7     SIZE_DMA_1_    mcell  H13     mx H24           FC_0_        pin 57
mx H8         UDS_000        pin 32     mx H25              RW        pin 71
mx H9CLK_OUT_PRE_Dreg    mcell  G13     mx H26          AS_000        pin 42
mx H10 inst_CLK_000_PE     mcell  G9     mx H27           A_17_        pin 59
mx H11       FPU_SENSE        pin 91     mx H28CLK_000_N_SYNC_10_    mcell  B13
mx H12           A_19_        pin 97     mx H29CLK_000_N_SYNC_9_     mcell  G6
mx H13  inst_AS_030_D0     mcell  H5     mx H30       RN_RW_000     mcell  H0
mx H14inst_nEXP_SPACE_D0reg     mcell  C4     mx H31     SM_AMIGA_7_     mcell  F0
mx H15     SM_AMIGA_0_    mcell  F13     mx H32     SM_AMIGA_1_     mcell  F9
mx H16     SIZE_DMA_0_     mcell  B9
----------------------------------------------------------------------------

<Note> CSM indicates the mux inputs from the Central Switch Matrix.
<Note> Source indicates where the signal comes from (pin or macrocell). 




PostFit_Equations
~~~~~~~~~~~~~~~~~


 P-Terms   Fan-in  Fan-out  Type  Name (attributes)
---------  ------  -------  ----  -----------------
   1          2        1    Pin   SIZE_1_ 
   1          2        1    Pin   SIZE_1_.OE 
   1          2        1    Pin   AS_000- 
   1          1        1    Pin   AS_000.OE 
   1          3        1    Pin   UDS_000- 
   1          1        1    Pin   UDS_000.OE 
   1          3        1    Pin   LDS_000- 
   1          1        1    Pin   LDS_000.OE 
   0          0        1    Pin   BERR 
   1          9        1    Pin   BERR.OE 
   1          1        1    Pin   CLK_DIV_OUT 
   1          1        1    Pin   CLK_EXP 
   1          9        1    Pin   FPU_CS- 
   1          0        1    Pin   AVEC 
   2          4        1    Pin   AMIGA_BUS_DATA_DIR 
   1          2        1    Pin   AMIGA_BUS_ENABLE_LOW- 
   2          3        1    Pin   AMIGA_BUS_ENABLE_HIGH 
   1         13        1    Pin   CIIN 
   1          1        1    Pin   CIIN.OE 
   1          2        1    Pin   SIZE_0_ 
   1          2        1    Pin   SIZE_0_.OE 
   2          3        1    Pin   IPL_030_2_.D 
   1          1        1    Pin   IPL_030_2_.AP 
   1          1        1    Pin   IPL_030_2_.C 
   2          3        1    Pin   IPL_030_1_.D 
   1          1        1    Pin   IPL_030_1_.AP 
   1          1        1    Pin   IPL_030_1_.C 
   2          3        1    Pin   IPL_030_0_.D 
   1          1        1    Pin   IPL_030_0_.AP 
   1          1        1    Pin   IPL_030_0_.C 
   1          2        1    Pin   AS_030.OE 
   4          6        1    Pin   AS_030.D 
   1          1        1    Pin   AS_030.AP 
   1          1        1    Pin   AS_030.C 
   1          1        1    Pin   RW_000.OE 
   3          8        1    Pin   RW_000.D- 
   1          1        1    Pin   RW_000.AP 
   1          1        1    Pin   RW_000.C 
   1          2        1    Pin   DS_030.OE 
   6          9        1    Pin   DS_030.D 
   1          1        1    Pin   DS_030.AP 
   1          1        1    Pin   DS_030.C 
   1          2        1    Pin   A0.OE 
   1          4        1    Pin   A0.D 
   1          1        1    Pin   A0.AP 
   1          1        1    Pin   A0.C 
   2          5        1    Pin   BG_000.D- 
   1          1        1    Pin   BG_000.AP 
   1          1        1    Pin   BG_000.C 
   2          3        1    Pin   BGACK_030.D 
   1          1        1    Pin   BGACK_030.AP 
   1          1        1    Pin   BGACK_030.C 
   1          1        1    Pin   DSACK1.OE 
   4          8        1    Pin   DSACK1.D- 
   1          1        1    Pin   DSACK1.AP 
   1          1        1    Pin   DSACK1.C 
   5          5        1    Pin   E.D 
   1          1        1    Pin   E.C 
   1          1        1    Pin   VMA.AP 
   2          8        1    Pin   VMA.T 
   1          1        1    Pin   VMA.C 
   1          1        1    Pin   RESET.AR 
   2          9        1    Pin   RESET.D 
   1          1        1    Pin   RESET.C 
   1          1        1    Pin   RW.OE 
   2          5        1    Pin   RW.D- 
   1          1        1    Pin   RW.AP 
   1          1        1    Pin   RW.C 
   3          8        1    Pin   AMIGA_ADDR_ENABLE.D- 
   1          1        1    Pin   AMIGA_ADDR_ENABLE.AP 
   1          1        1    Pin   AMIGA_ADDR_ENABLE.C 
   2          2        1    Node  cpu_est_0_.D 
   1          1        1    Node  cpu_est_0_.C 
   5          5        1    Node  cpu_est_1_.D- 
   1          1        1    Node  cpu_est_1_.C 
   2          4        1    Node  inst_AS_000_INT.D- 
   1          1        1    Node  inst_AS_000_INT.AP 
   1          1        1    Node  inst_AS_000_INT.C 
   2          5        1    Node  inst_AMIGA_BUS_ENABLE_DMA_LOW.D- 
   1          1        1    Node  inst_AMIGA_BUS_ENABLE_DMA_LOW.AP 
   1          1        1    Node  inst_AMIGA_BUS_ENABLE_DMA_LOW.C 
   1          1        1    Node  inst_AS_030_D0.D 
   1          1        1    Node  inst_AS_030_D0.AP 
   1          1        1    Node  inst_AS_030_D0.C 
   1          1        1    Node  inst_nEXP_SPACE_D0reg.D 
   1          1        1    Node  inst_nEXP_SPACE_D0reg.AP 
   1          1        1    Node  inst_nEXP_SPACE_D0reg.C 
   1          1        1    Node  inst_DS_030_D0.D 
   1          1        1    Node  inst_DS_030_D0.AP 
   1          1        1    Node  inst_DS_030_D0.C 
   6         12        1    Node  inst_AS_030_000_SYNC.D 
   1          1        1    Node  inst_AS_030_000_SYNC.AP 
   1          1        1    Node  inst_AS_030_000_SYNC.C 
   1          1        1    Node  inst_BGACK_030_INT_D.D 
   1          1        1    Node  inst_BGACK_030_INT_D.AP 
   1          1        1    Node  inst_BGACK_030_INT_D.C 
   2          4        1    Node  SIZE_DMA_0_.D 
   1          1        1    Node  SIZE_DMA_0_.AP 
   1          1        1    Node  SIZE_DMA_0_.C 
   1          4        1    Node  SIZE_DMA_1_.D 
   1          1        1    Node  SIZE_DMA_1_.AP 
   1          1        1    Node  SIZE_DMA_1_.C 
   1          1        1    Node  inst_VPA_D.D 
   1          1        1    Node  inst_VPA_D.AP 
   1          1        1    Node  inst_VPA_D.C 
   3          4        1    Node  inst_UDS_000_INT.D 
   1          1        1    Node  inst_UDS_000_INT.AP 
   1          1        1    Node  inst_UDS_000_INT.C 
   3          6        1    Node  inst_LDS_000_INT.D 
   1          1        1    Node  inst_LDS_000_INT.AP 
   1          1        1    Node  inst_LDS_000_INT.C 
   1          1        1    Node  inst_DTACK_D0.D 
   1          1        1    Node  inst_DTACK_D0.AP 
   1          1        1    Node  inst_DTACK_D0.C 
   1          1        1    Node  inst_CLK_OUT_PRE_50.D 
   1          1        1    Node  inst_CLK_OUT_PRE_50.C 
   1          1        1    Node  inst_CLK_000_D1.D 
   1          1        1    Node  inst_CLK_000_D1.C 
   1          1        1    Node  inst_CLK_000_D0.D 
   1          1        1    Node  inst_CLK_000_D0.C 
   1          1        1    Node  inst_CLK_000_PE.D 
   1          1        1    Node  inst_CLK_000_PE.C 
  13         15        1    Node  SM_AMIGA_7_.D 
   1          1        1    Node  SM_AMIGA_7_.AP 
   1          1        1    Node  SM_AMIGA_7_.C 
   1          1        1    Node  SM_AMIGA_5_.AR 
   2          5        1    Node  SM_AMIGA_5_.D 
   1          1        1    Node  SM_AMIGA_5_.C 
   1          1        1    Node  inst_CLK_OUT_PRE.D 
   1          1        1    Node  inst_CLK_OUT_PRE.C 
   1          1        1    Node  inst_CLK_000_NE.D 
   1          1        1    Node  inst_CLK_000_NE.C 
   1          1        1    Node  CLK_000_N_SYNC_11_.D 
   1          1        1    Node  CLK_000_N_SYNC_11_.C 
   1          1        1    Node  CLK_000_P_SYNC_9_.D 
   1          1        1    Node  CLK_000_P_SYNC_9_.C 
   4          5        1    Node  cpu_est_2_.D 
   1          1        1    Node  cpu_est_2_.C 
   1          1        1    Node  inst_CLK_000_NE_D0.D 
   1          1        1    Node  inst_CLK_000_NE_D0.C 
   6         12        1    NodeX1  SM_AMIGA_3_.D.X1 
   1          2        1    NodeX2  SM_AMIGA_3_.D.X2 
   1          1        1    Node  SM_AMIGA_3_.AR 
   1          1        1    Node  SM_AMIGA_3_.C 
   1          1        1    Node  SM_AMIGA_0_.AR 
   2          5        1    Node  SM_AMIGA_0_.D 
   1          1        1    Node  SM_AMIGA_0_.C 
   2          5        1    Node  inst_AMIGA_BUS_ENABLE_DMA_HIGH.D- 
   1          1        1    Node  inst_AMIGA_BUS_ENABLE_DMA_HIGH.AP 
   1          1        1    Node  inst_AMIGA_BUS_ENABLE_DMA_HIGH.C 
   1          1        1    Node  SM_AMIGA_6_.AR 
   2          8        1    Node  SM_AMIGA_6_.D 
   1          1        1    Node  SM_AMIGA_6_.C 
   1          1        1    Node  RESET_DLY_0_.AR 
   1          5        1    Node  RESET_DLY_0_.T 
   1          1        1    Node  RESET_DLY_0_.C 
   1          1        1    Node  RESET_DLY_1_.AR 
   1          6        1    Node  RESET_DLY_1_.T 
   1          1        1    Node  RESET_DLY_1_.C 
   1          1        1    Node  RESET_DLY_2_.AR 
   1          7        1    Node  RESET_DLY_2_.T 
   1          1        1    Node  RESET_DLY_2_.C 
   1          1        1    Node  RESET_DLY_3_.AR 
   1          8        1    Node  RESET_DLY_3_.T 
   1          1        1    Node  RESET_DLY_3_.C 
   1          1        1    Node  RESET_DLY_4_.AR 
   1          9        1    Node  RESET_DLY_4_.T 
   1          1        1    Node  RESET_DLY_4_.C 
   1          1        1    Node  RESET_DLY_5_.AR 
   1         10        1    Node  RESET_DLY_5_.T 
   1          1        1    Node  RESET_DLY_5_.C 
   1          1        1    Node  RESET_DLY_6_.AR 
   1         11        1    Node  RESET_DLY_6_.T 
   1          1        1    Node  RESET_DLY_6_.C 
   1          1        1    Node  RESET_DLY_7_.AR 
   1         12        1    Node  RESET_DLY_7_.T 
   1          1        1    Node  RESET_DLY_7_.C 
   1          2        1    Node  CLK_000_P_SYNC_0_.D 
   1          1        1    Node  CLK_000_P_SYNC_0_.C 
   1          1        1    Node  CLK_000_P_SYNC_1_.D 
   1          1        1    Node  CLK_000_P_SYNC_1_.C 
   1          1        1    Node  CLK_000_P_SYNC_2_.D 
   1          1        1    Node  CLK_000_P_SYNC_2_.C 
   1          1        1    Node  CLK_000_P_SYNC_3_.D 
   1          1        1    Node  CLK_000_P_SYNC_3_.C 
   1          1        1    Node  CLK_000_P_SYNC_4_.D 
   1          1        1    Node  CLK_000_P_SYNC_4_.C 
   1          1        1    Node  CLK_000_P_SYNC_5_.D 
   1          1        1    Node  CLK_000_P_SYNC_5_.C 
   1          1        1    Node  CLK_000_P_SYNC_6_.D 
   1          1        1    Node  CLK_000_P_SYNC_6_.C 
   1          1        1    Node  CLK_000_P_SYNC_7_.D 
   1          1        1    Node  CLK_000_P_SYNC_7_.C 
   1          1        1    Node  CLK_000_P_SYNC_8_.D 
   1          1        1    Node  CLK_000_P_SYNC_8_.C 
   1          2        1    Node  CLK_000_N_SYNC_0_.D 
   1          1        1    Node  CLK_000_N_SYNC_0_.C 
   1          1        1    Node  CLK_000_N_SYNC_1_.D 
   1          1        1    Node  CLK_000_N_SYNC_1_.C 
   1          1        1    Node  CLK_000_N_SYNC_2_.D 
   1          1        1    Node  CLK_000_N_SYNC_2_.C 
   1          1        1    Node  CLK_000_N_SYNC_3_.D 
   1          1        1    Node  CLK_000_N_SYNC_3_.C 
   1          1        1    Node  CLK_000_N_SYNC_4_.D 
   1          1        1    Node  CLK_000_N_SYNC_4_.C 
   1          1        1    Node  CLK_000_N_SYNC_5_.D 
   1          1        1    Node  CLK_000_N_SYNC_5_.C 
   1          1        1    Node  CLK_000_N_SYNC_6_.D 
   1          1        1    Node  CLK_000_N_SYNC_6_.C 
   1          1        1    Node  CLK_000_N_SYNC_7_.D 
   1          1        1    Node  CLK_000_N_SYNC_7_.C 
   1          1        1    Node  CLK_000_N_SYNC_8_.D 
   1          1        1    Node  CLK_000_N_SYNC_8_.C 
   1          1        1    Node  CLK_000_N_SYNC_9_.D 
   1          1        1    Node  CLK_000_N_SYNC_9_.C 
   1          1        1    Node  CLK_000_N_SYNC_10_.D 
   1          1        1    Node  CLK_000_N_SYNC_10_.C 
   1          1        1    Node  inst_CLK_030_H.AR 
   4          7        1    Node  inst_CLK_030_H.D 
   1          1        1    Node  inst_CLK_030_H.C 
   1          1        1    Node  inst_DS_000_ENABLE.AR 
   3          6        1    Node  inst_DS_000_ENABLE.D 
   1          1        1    Node  inst_DS_000_ENABLE.C 
   1          1        1    Node  SM_AMIGA_1_.AR 
   2          5        1    Node  SM_AMIGA_1_.D 
   1          1        1    Node  SM_AMIGA_1_.C 
   1          1        1    Node  SM_AMIGA_4_.AR 
   2          5        1    Node  SM_AMIGA_4_.D 
   1          1        1    Node  SM_AMIGA_4_.C 
   1          1        1    Node  SM_AMIGA_2_.AR 
   3         12        1    Node  SM_AMIGA_2_.D 
   1          1        1    Node  SM_AMIGA_2_.C 
   1          1        1    Node  CLK_OUT_PRE_Dreg.D 
   1          1        1    Node  CLK_OUT_PRE_Dreg.C 
   2          9        1    Node  un8_ciin- 
   2          7        1    Node  state_machine_un15_clk_000_ne_i_n- 
   2         15        1    Node  CIIN_0 
=========
 318                 P-Term Total: 318
                       Total Pins: 61
                      Total Nodes: 68
            Average P-Term/Output: 1


Equations:

SIZE_1_ = (!SIZE_DMA_0_.Q & SIZE_DMA_1_.Q);

SIZE_1_.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q);

!AS_000 = (!inst_AS_000_INT.Q & !AS_030.PIN);

AS_000.OE = (BGACK_030.Q);

!UDS_000 = (!inst_UDS_000_INT.Q & inst_DS_000_ENABLE.Q & !DS_030.PIN);

UDS_000.OE = (BGACK_030.Q);

!LDS_000 = (!inst_LDS_000_INT.Q & inst_DS_000_ENABLE.Q & !DS_030.PIN);

LDS_000.OE = (BGACK_030.Q);

BERR = (0);

BERR.OE = (FC_1_ & BGACK_000 & FPU_SENSE & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & !AS_030.PIN);

CLK_DIV_OUT = (CLK_OUT_PRE_Dreg.Q);

CLK_EXP = (CLK_OUT_PRE_Dreg.Q);

!FPU_CS = (FC_1_ & BGACK_000 & !FPU_SENSE & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & !AS_030.PIN);

AVEC = (1);

AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW_000.PIN
     # !BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q & !AS_000.PIN & RW_000.PIN);

!AMIGA_BUS_ENABLE_LOW = (!BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_LOW.Q);

AMIGA_BUS_ENABLE_HIGH = (BGACK_030.Q & SM_AMIGA_7_.Q
     # !BGACK_030.Q & inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q);

CIIN = (!A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_ & A_23_ & A_22_ & A_21_ & A_20_ & !inst_AS_030_D0.Q);

CIIN.OE = (CIIN_0);

SIZE_0_ = (SIZE_DMA_0_.Q & !SIZE_DMA_1_.Q);

SIZE_0_.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q);

IPL_030_2_.D = (IPL_2_ & inst_CLK_000_NE.Q
     # !inst_CLK_000_NE.Q & IPL_030_2_.Q);

IPL_030_2_.AP = (!RST);

IPL_030_2_.C = (CLK_OSZI);

IPL_030_1_.D = (IPL_1_ & inst_CLK_000_NE.Q
     # !inst_CLK_000_NE.Q & IPL_030_1_.Q);

IPL_030_1_.AP = (!RST);

IPL_030_1_.C = (CLK_OSZI);

IPL_030_0_.D = (IPL_0_ & inst_CLK_000_NE.Q
     # !inst_CLK_000_NE.Q & IPL_030_0_.Q);

IPL_030_0_.AP = (!RST);

IPL_030_0_.C = (CLK_OSZI);

AS_030.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q);

AS_030.D = (BGACK_030.Q
     # AS_000.PIN
     # !CLK_030 & AS_030.Q
     # UDS_000.PIN & LDS_000.PIN);

AS_030.AP = (!RST);

AS_030.C = (CLK_OSZI);

RW_000.OE = (BGACK_030.Q);

!RW_000.D = (SM_AMIGA_5_.Q & !RW.PIN
     # !inst_AS_030_D0.Q & !inst_CLK_000_PE.Q & !SM_AMIGA_7_.Q & !SM_AMIGA_5_.Q & !RW_000.Q & BERR.PIN
     # !inst_AS_030_D0.Q & !SM_AMIGA_7_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !RW_000.Q & BERR.PIN);

RW_000.AP = (!RST);

RW_000.C = (CLK_OSZI);

DS_030.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q);

DS_030.D = (BGACK_030.Q
     # AS_000.PIN
     # UDS_000.PIN & LDS_000.PIN
     # !CLK_030 & DS_030.Q & !RW_000.PIN
     # DS_030.Q & !inst_CLK_030_H.Q & !RW_000.PIN
     # CLK_030 & AS_030.Q & inst_CLK_030_H.Q & !RW_000.PIN);

DS_030.AP = (!RST);

DS_030.C = (CLK_OSZI);

A0.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q);

A0.D = (!BGACK_030.Q & !AS_000.PIN & UDS_000.PIN & !LDS_000.PIN);

A0.AP = (!RST);

A0.C = (CLK_OSZI);

!BG_000.D = (!BG_030 & !BG_000.Q
     # !BG_030 & inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_CLK_000_D0.Q);

BG_000.AP = (!RST);

BG_000.C = (CLK_OSZI);

BGACK_030.D = (BGACK_000 & BGACK_030.Q
     # BGACK_000 & inst_CLK_000_PE.Q);

BGACK_030.AP = (!RST);

BGACK_030.C = (CLK_OSZI);

DSACK1.OE = (inst_nEXP_SPACE_D0reg.Q);

!DSACK1.D = (CLK_000_N_SYNC_10_.Q & SM_AMIGA_1_.Q
     # !CLK_030 & CLK_000_N_SYNC_9_.Q & SM_AMIGA_1_.Q
     # CLK_000_N_SYNC_9_.Q & SM_AMIGA_1_.Q & CLK_OUT_PRE_Dreg.Q
     # !inst_AS_030_D0.Q & !DSACK1.Q & BERR.PIN);

DSACK1.AP = (!RST);

DSACK1.C = (CLK_OSZI);

E.D = (E.Q & !cpu_est_0_.Q
     # E.Q & !cpu_est_1_.Q
     # E.Q & !inst_CLK_000_NE_D0.Q
     # cpu_est_0_.Q & cpu_est_1_.Q & !cpu_est_2_.Q & inst_CLK_000_NE_D0.Q
     # !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & inst_CLK_000_NE_D0.Q);

E.C = (CLK_OSZI);

VMA.AP = (!RST);

VMA.T = (!E.Q & !VMA.Q & !cpu_est_0_.Q & cpu_est_1_.Q & inst_CLK_000_PE.Q & cpu_est_2_.Q
     # !E.Q & VMA.Q & cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_NE.Q & cpu_est_2_.Q);

VMA.C = (CLK_OSZI);

RESET.AR = (!RST);

RESET.D = (RESET.Q
     # RESET_DLY_0_.Q & RESET_DLY_1_.Q & RESET_DLY_2_.Q & RESET_DLY_3_.Q & RESET_DLY_4_.Q & RESET_DLY_5_.Q & RESET_DLY_6_.Q & RESET_DLY_7_.Q);

RESET.C = (CLK_OSZI);

RW.OE = (!BGACK_030.Q);

!RW.D = (!BGACK_030.Q & !AS_000.PIN & !RW_000.PIN & !UDS_000.PIN
     # !BGACK_030.Q & !AS_000.PIN & !RW_000.PIN & !LDS_000.PIN);

RW.AP = (!RST);

RW.C = (CLK_OSZI);

!AMIGA_ADDR_ENABLE.D = (!BGACK_030.Q
     # !AMIGA_ADDR_ENABLE.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_7_.Q
     # inst_nEXP_SPACE_D0reg.Q & !inst_AS_030_000_SYNC.Q & inst_BGACK_030_INT_D.Q & inst_CLK_000_D1.Q & !inst_CLK_000_D0.Q & SM_AMIGA_7_.Q);

AMIGA_ADDR_ENABLE.AP = (!RST);

AMIGA_ADDR_ENABLE.C = (CLK_OSZI);

cpu_est_0_.D = (!cpu_est_0_.Q & inst_CLK_000_NE_D0.Q
     # cpu_est_0_.Q & !inst_CLK_000_NE_D0.Q);

cpu_est_0_.C = (CLK_OSZI);

!cpu_est_1_.D = (!cpu_est_1_.Q & !inst_CLK_000_NE_D0.Q
     # E.Q & cpu_est_0_.Q & !cpu_est_1_.Q
     # !E.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & cpu_est_2_.Q
     # E.Q & cpu_est_0_.Q & !cpu_est_2_.Q & inst_CLK_000_NE_D0.Q
     # !E.Q & cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q);

cpu_est_1_.C = (CLK_OSZI);

!inst_AS_000_INT.D = (SM_AMIGA_5_.Q
     # !inst_AS_000_INT.Q & !inst_AS_030_D0.Q & BERR.PIN);

inst_AS_000_INT.AP = (!RST);

inst_AS_000_INT.C = (CLK_OSZI);

!inst_AMIGA_BUS_ENABLE_DMA_LOW.D = (A1 & !BGACK_030.Q & !AS_000.PIN & !UDS_000.PIN
     # A1 & !BGACK_030.Q & !AS_000.PIN & !LDS_000.PIN);

inst_AMIGA_BUS_ENABLE_DMA_LOW.AP = (!RST);

inst_AMIGA_BUS_ENABLE_DMA_LOW.C = (CLK_OSZI);

inst_AS_030_D0.D = (AS_030.PIN);

inst_AS_030_D0.AP = (!RST);

inst_AS_030_D0.C = (CLK_OSZI);

inst_nEXP_SPACE_D0reg.D = (nEXP_SPACE);

inst_nEXP_SPACE_D0reg.AP = (!RST);

inst_nEXP_SPACE_D0reg.C = (CLK_OSZI);

inst_DS_030_D0.D = (DS_030.PIN);

inst_DS_030_D0.AP = (!RST);

inst_DS_030_D0.C = (CLK_OSZI);

inst_AS_030_000_SYNC.D = (inst_AS_030_D0.Q
     # !BERR.PIN
     # !BGACK_000 & inst_AS_030_000_SYNC.Q
     # !inst_nEXP_SPACE_D0reg.Q & inst_AS_030_000_SYNC.Q
     # inst_AS_030_000_SYNC.Q & !SM_AMIGA_7_.Q
     # FC_1_ & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & inst_AS_030_000_SYNC.Q);

inst_AS_030_000_SYNC.AP = (!RST);

inst_AS_030_000_SYNC.C = (CLK_OSZI);

inst_BGACK_030_INT_D.D = (BGACK_030.Q);

inst_BGACK_030_INT_D.AP = (!RST);

inst_BGACK_030_INT_D.C = (CLK_OSZI);

SIZE_DMA_0_.D = (!BGACK_030.Q & !AS_000.PIN & !UDS_000.PIN & LDS_000.PIN
     # !BGACK_030.Q & !AS_000.PIN & UDS_000.PIN & !LDS_000.PIN);

SIZE_DMA_0_.AP = (!RST);

SIZE_DMA_0_.C = (CLK_OSZI);

SIZE_DMA_1_.D = (!BGACK_030.Q & !AS_000.PIN & !UDS_000.PIN & !LDS_000.PIN);

SIZE_DMA_1_.AP = (!RST);

SIZE_DMA_1_.C = (CLK_OSZI);

inst_VPA_D.D = (VPA);

inst_VPA_D.AP = (!RST);

inst_VPA_D.C = (CLK_OSZI);

inst_UDS_000_INT.D = (inst_DS_030_D0.Q & inst_UDS_000_INT.Q
     # inst_UDS_000_INT.Q & !SM_AMIGA_6_.Q
     # !inst_DS_030_D0.Q & SM_AMIGA_6_.Q & A0.PIN);

inst_UDS_000_INT.AP = (!RST);

inst_UDS_000_INT.C = (CLK_OSZI);

inst_LDS_000_INT.D = (inst_DS_030_D0.Q & inst_LDS_000_INT.Q
     # inst_LDS_000_INT.Q & !SM_AMIGA_6_.Q
     # !inst_DS_030_D0.Q & SM_AMIGA_6_.Q & SIZE_0_.PIN & !SIZE_1_.PIN & !A0.PIN);

inst_LDS_000_INT.AP = (!RST);

inst_LDS_000_INT.C = (CLK_OSZI);

inst_DTACK_D0.D = (DTACK);

inst_DTACK_D0.AP = (!RST);

inst_DTACK_D0.C = (CLK_OSZI);

inst_CLK_OUT_PRE_50.D = (!inst_CLK_OUT_PRE_50.Q);

inst_CLK_OUT_PRE_50.C = (CLK_OSZI);

inst_CLK_000_D1.D = (inst_CLK_000_D0.Q);

inst_CLK_000_D1.C = (CLK_OSZI);

inst_CLK_000_D0.D = (CLK_000);

inst_CLK_000_D0.C = (CLK_OSZI);

inst_CLK_000_PE.D = (CLK_000_P_SYNC_9_.Q);

inst_CLK_000_PE.C = (CLK_OSZI);

SM_AMIGA_7_.D = (inst_CLK_000_PE.Q & SM_AMIGA_0_.Q
     # SM_AMIGA_0_.Q & !BERR.PIN
     # SM_AMIGA_5_.Q & !inst_CLK_000_NE.Q & !BERR.PIN
     # !inst_CLK_000_NE.Q & SM_AMIGA_3_.Q & !BERR.PIN
     # !inst_CLK_000_PE.Q & SM_AMIGA_6_.Q & !BERR.PIN
     # !inst_CLK_000_NE.Q & SM_AMIGA_1_.Q & !BERR.PIN
     # !inst_CLK_000_PE.Q & SM_AMIGA_4_.Q & !BERR.PIN
     # !inst_CLK_000_PE.Q & SM_AMIGA_2_.Q & !BERR.PIN
     # SM_AMIGA_3_.Q & state_machine_un15_clk_000_ne_i_n & !BERR.PIN
     # !inst_nEXP_SPACE_D0reg.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q
     # inst_AS_030_000_SYNC.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q
     # !inst_CLK_000_D1.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q
     # inst_CLK_000_D0.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q);

SM_AMIGA_7_.AP = (!RST);

SM_AMIGA_7_.C = (CLK_OSZI);

SM_AMIGA_5_.AR = (!RST);

SM_AMIGA_5_.D = (inst_CLK_000_PE.Q & SM_AMIGA_6_.Q
     # SM_AMIGA_5_.Q & !inst_CLK_000_NE.Q & BERR.PIN);

SM_AMIGA_5_.C = (CLK_OSZI);

inst_CLK_OUT_PRE.D = (inst_CLK_OUT_PRE_50.Q);

inst_CLK_OUT_PRE.C = (CLK_OSZI);

inst_CLK_000_NE.D = (CLK_000_N_SYNC_11_.Q);

inst_CLK_000_NE.C = (CLK_OSZI);

CLK_000_N_SYNC_11_.D = (CLK_000_N_SYNC_10_.Q);

CLK_000_N_SYNC_11_.C = (CLK_OSZI);

CLK_000_P_SYNC_9_.D = (CLK_000_P_SYNC_8_.Q);

CLK_000_P_SYNC_9_.C = (CLK_OSZI);

cpu_est_2_.D = (cpu_est_1_.Q & cpu_est_2_.Q
     # cpu_est_2_.Q & !inst_CLK_000_NE_D0.Q
     # E.Q & cpu_est_0_.Q & inst_CLK_000_NE_D0.Q
     # !cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_NE_D0.Q);

cpu_est_2_.C = (CLK_OSZI);

inst_CLK_000_NE_D0.D = (inst_CLK_000_NE.Q);

inst_CLK_000_NE_D0.C = (CLK_OSZI);

SM_AMIGA_3_.D.X1 = (inst_CLK_000_PE.Q & !SM_AMIGA_3_.Q & SM_AMIGA_4_.Q
     # inst_CLK_000_PE.Q & SM_AMIGA_4_.Q & !BERR.PIN
     # inst_VPA_D.Q & !inst_DTACK_D0.Q & !inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & SM_AMIGA_3_.Q & BERR.PIN
     # inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_NE.Q & SM_AMIGA_3_.Q & !SM_AMIGA_4_.Q & BERR.PIN
     # E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & !inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & cpu_est_2_.Q & SM_AMIGA_3_.Q & BERR.PIN
     # E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_NE.Q & cpu_est_2_.Q & SM_AMIGA_3_.Q & !SM_AMIGA_4_.Q & BERR.PIN);

SM_AMIGA_3_.D.X2 = (SM_AMIGA_3_.Q & BERR.PIN);

SM_AMIGA_3_.AR = (!RST);

SM_AMIGA_3_.C = (CLK_OSZI);

SM_AMIGA_0_.AR = (!RST);

SM_AMIGA_0_.D = (inst_CLK_000_NE.Q & !SM_AMIGA_0_.Q & SM_AMIGA_1_.Q
     # !inst_CLK_000_PE.Q & SM_AMIGA_0_.Q & BERR.PIN);

SM_AMIGA_0_.C = (CLK_OSZI);

!inst_AMIGA_BUS_ENABLE_DMA_HIGH.D = (!A1 & !BGACK_030.Q & !AS_000.PIN & !UDS_000.PIN
     # !A1 & !BGACK_030.Q & !AS_000.PIN & !LDS_000.PIN);

inst_AMIGA_BUS_ENABLE_DMA_HIGH.AP = (!RST);

inst_AMIGA_BUS_ENABLE_DMA_HIGH.C = (CLK_OSZI);

SM_AMIGA_6_.AR = (!RST);

SM_AMIGA_6_.D = (!inst_CLK_000_PE.Q & SM_AMIGA_6_.Q & BERR.PIN
     # inst_nEXP_SPACE_D0reg.Q & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D1.Q & !inst_CLK_000_D0.Q & SM_AMIGA_7_.Q);

SM_AMIGA_6_.C = (CLK_OSZI);

RESET_DLY_0_.AR = (!RST);

RESET_DLY_0_.T = (!E.Q & !cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q);

RESET_DLY_0_.C = (CLK_OSZI);

RESET_DLY_1_.AR = (!RST);

RESET_DLY_1_.T = (!E.Q & !cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & RESET_DLY_0_.Q);

RESET_DLY_1_.C = (CLK_OSZI);

RESET_DLY_2_.AR = (!RST);

RESET_DLY_2_.T = (!E.Q & !cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & RESET_DLY_0_.Q & RESET_DLY_1_.Q);

RESET_DLY_2_.C = (CLK_OSZI);

RESET_DLY_3_.AR = (!RST);

RESET_DLY_3_.T = (!E.Q & !cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & RESET_DLY_0_.Q & RESET_DLY_1_.Q & RESET_DLY_2_.Q);

RESET_DLY_3_.C = (CLK_OSZI);

RESET_DLY_4_.AR = (!RST);

RESET_DLY_4_.T = (!E.Q & !cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & RESET_DLY_0_.Q & RESET_DLY_1_.Q & RESET_DLY_2_.Q & RESET_DLY_3_.Q);

RESET_DLY_4_.C = (CLK_OSZI);

RESET_DLY_5_.AR = (!RST);

RESET_DLY_5_.T = (!E.Q & !cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & RESET_DLY_0_.Q & RESET_DLY_1_.Q & RESET_DLY_2_.Q & RESET_DLY_3_.Q & RESET_DLY_4_.Q);

RESET_DLY_5_.C = (CLK_OSZI);

RESET_DLY_6_.AR = (!RST);

RESET_DLY_6_.T = (!E.Q & !cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & RESET_DLY_0_.Q & RESET_DLY_1_.Q & RESET_DLY_2_.Q & RESET_DLY_3_.Q & RESET_DLY_4_.Q & RESET_DLY_5_.Q);

RESET_DLY_6_.C = (CLK_OSZI);

RESET_DLY_7_.AR = (!RST);

RESET_DLY_7_.T = (!E.Q & !cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & RESET_DLY_0_.Q & RESET_DLY_1_.Q & RESET_DLY_2_.Q & RESET_DLY_3_.Q & RESET_DLY_4_.Q & RESET_DLY_5_.Q & RESET_DLY_6_.Q);

RESET_DLY_7_.C = (CLK_OSZI);

CLK_000_P_SYNC_0_.D = (!inst_CLK_000_D1.Q & inst_CLK_000_D0.Q);

CLK_000_P_SYNC_0_.C = (CLK_OSZI);

CLK_000_P_SYNC_1_.D = (CLK_000_P_SYNC_0_.Q);

CLK_000_P_SYNC_1_.C = (CLK_OSZI);

CLK_000_P_SYNC_2_.D = (CLK_000_P_SYNC_1_.Q);

CLK_000_P_SYNC_2_.C = (CLK_OSZI);

CLK_000_P_SYNC_3_.D = (CLK_000_P_SYNC_2_.Q);

CLK_000_P_SYNC_3_.C = (CLK_OSZI);

CLK_000_P_SYNC_4_.D = (CLK_000_P_SYNC_3_.Q);

CLK_000_P_SYNC_4_.C = (CLK_OSZI);

CLK_000_P_SYNC_5_.D = (CLK_000_P_SYNC_4_.Q);

CLK_000_P_SYNC_5_.C = (CLK_OSZI);

CLK_000_P_SYNC_6_.D = (CLK_000_P_SYNC_5_.Q);

CLK_000_P_SYNC_6_.C = (CLK_OSZI);

CLK_000_P_SYNC_7_.D = (CLK_000_P_SYNC_6_.Q);

CLK_000_P_SYNC_7_.C = (CLK_OSZI);

CLK_000_P_SYNC_8_.D = (CLK_000_P_SYNC_7_.Q);

CLK_000_P_SYNC_8_.C = (CLK_OSZI);

CLK_000_N_SYNC_0_.D = (inst_CLK_000_D1.Q & !inst_CLK_000_D0.Q);

CLK_000_N_SYNC_0_.C = (CLK_OSZI);

CLK_000_N_SYNC_1_.D = (CLK_000_N_SYNC_0_.Q);

CLK_000_N_SYNC_1_.C = (CLK_OSZI);

CLK_000_N_SYNC_2_.D = (CLK_000_N_SYNC_1_.Q);

CLK_000_N_SYNC_2_.C = (CLK_OSZI);

CLK_000_N_SYNC_3_.D = (CLK_000_N_SYNC_2_.Q);

CLK_000_N_SYNC_3_.C = (CLK_OSZI);

CLK_000_N_SYNC_4_.D = (CLK_000_N_SYNC_3_.Q);

CLK_000_N_SYNC_4_.C = (CLK_OSZI);

CLK_000_N_SYNC_5_.D = (CLK_000_N_SYNC_4_.Q);

CLK_000_N_SYNC_5_.C = (CLK_OSZI);

CLK_000_N_SYNC_6_.D = (CLK_000_N_SYNC_5_.Q);

CLK_000_N_SYNC_6_.C = (CLK_OSZI);

CLK_000_N_SYNC_7_.D = (CLK_000_N_SYNC_6_.Q);

CLK_000_N_SYNC_7_.C = (CLK_OSZI);

CLK_000_N_SYNC_8_.D = (CLK_000_N_SYNC_7_.Q);

CLK_000_N_SYNC_8_.C = (CLK_OSZI);

CLK_000_N_SYNC_9_.D = (CLK_000_N_SYNC_8_.Q);

CLK_000_N_SYNC_9_.C = (CLK_OSZI);

CLK_000_N_SYNC_10_.D = (CLK_000_N_SYNC_9_.Q);

CLK_000_N_SYNC_10_.C = (CLK_OSZI);

inst_CLK_030_H.AR = (!RST);

inst_CLK_030_H.D = (!BGACK_030.Q & inst_CLK_030_H.Q & !AS_000.PIN & !UDS_000.PIN
     # !BGACK_030.Q & inst_CLK_030_H.Q & !AS_000.PIN & !LDS_000.PIN
     # !CLK_030 & !BGACK_030.Q & !AS_030.Q & !AS_000.PIN & !UDS_000.PIN
     # !CLK_030 & !BGACK_030.Q & !AS_030.Q & !AS_000.PIN & !LDS_000.PIN);

inst_CLK_030_H.C = (CLK_OSZI);

inst_DS_000_ENABLE.AR = (!RST);

inst_DS_000_ENABLE.D = (!SM_AMIGA_5_.Q & SM_AMIGA_3_.Q
     # SM_AMIGA_5_.Q & RW.PIN
     # !inst_AS_030_D0.Q & inst_DS_000_ENABLE.Q & BERR.PIN);

inst_DS_000_ENABLE.C = (CLK_OSZI);

SM_AMIGA_1_.AR = (!RST);

SM_AMIGA_1_.D = (inst_CLK_000_PE.Q & SM_AMIGA_2_.Q
     # !inst_CLK_000_NE.Q & SM_AMIGA_1_.Q & BERR.PIN);

SM_AMIGA_1_.C = (CLK_OSZI);

SM_AMIGA_4_.AR = (!RST);

SM_AMIGA_4_.D = (SM_AMIGA_5_.Q & inst_CLK_000_NE.Q
     # !inst_CLK_000_PE.Q & SM_AMIGA_4_.Q & BERR.PIN);

SM_AMIGA_4_.C = (CLK_OSZI);

SM_AMIGA_2_.AR = (!RST);

SM_AMIGA_2_.D = (!inst_CLK_000_PE.Q & SM_AMIGA_2_.Q & BERR.PIN
     # inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_NE.Q & SM_AMIGA_3_.Q
     # E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_NE.Q & cpu_est_2_.Q & SM_AMIGA_3_.Q);

SM_AMIGA_2_.C = (CLK_OSZI);

CLK_OUT_PRE_Dreg.D = (inst_CLK_OUT_PRE.Q);

CLK_OUT_PRE_Dreg.C = (CLK_OSZI);

!un8_ciin = (AS_030.PIN
     # !A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_);

!state_machine_un15_clk_000_ne_i_n = (inst_VPA_D.Q & !inst_DTACK_D0.Q
     # E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & cpu_est_2_.Q);

CIIN_0 = (inst_nEXP_SPACE_D0reg.Q & !un8_ciin
     # !A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_ & A_23_ & A_22_ & A_21_ & A_20_ & !inst_AS_030_D0.Q);


Reverse-Polarity Equations:

