@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:61:134:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ...
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ...
@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Register bit BGACK_030_INT_PRE is always 1, optimizing ...