2014-05-15 21:05:08 +00:00
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@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":106:7:106:15|Signal clk_030_d is undriven
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@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":176:2:176:3|Pruning register CLK_REF(1 downto 0)
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@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":108:32:108:34|Pruning register cpu_est_d(3 downto 0)
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@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":108:32:108:34|Pruning register CLK_000_CNT(3 downto 0)
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@W: CL190 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":102:52:102:55|Optimizing register bit DSACK_INT(0) to a constant 1
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@W: CL260 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":102:52:102:55|Pruning register bit 0 of DSACK_INT(1 downto 0)
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@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":117:2:117:3|Register bit CLK_CNT(1) is always 0, optimizing ...
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@W: CL260 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":117:2:117:3|Pruning register bit 1 of CLK_CNT(1 downto 0)
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@W: CL249 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":176:2:176:3|Initial value is not supported on state machine SM_AMIGA
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2014-05-15 19:16:29 +00:00
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