68030tk/Logic/68030_TK.syn

JDF B
// Created by Version 1.7 
PROJECT 68030_TK
DESIGN 68030_tk Normal
DEVKIT M4A5-128/64-10VC
ENTRY Pure VHDL
MODULE 2to3divider.vhd
MODSTYLE clk_div_2by3 Normal
MODULE 68030-68000-bus.vhd
MODSTYLE BUS68030 Normal
SYNTHESIS_TOOL Synplify
SIMULATOR_TOOL ActiveHDL
TOPMODULE BUS68030
Initial push First VErsion after I decided to use version controll ;) 2014-05-15 21:16:29 +02:00			`JDF B`
			`// Created by Version 1.7`
			`PROJECT 68030_TK`
			`DESIGN 68030_tk Normal`
			`DEVKIT M4A5-128/64-10VC`
			`ENTRY Pure VHDL`
Caching for mem enabled 2014-06-09 20:27:37 +02:00			`MODULE 2to3divider.vhd`
			`MODSTYLE clk_div_2by3 Normal`
Initial push First VErsion after I decided to use version controll ;) 2014-05-15 21:16:29 +02:00			`MODULE 68030-68000-bus.vhd`
			`MODSTYLE BUS68030 Normal`
			`SYNTHESIS_TOOL Synplify`
			`SIMULATOR_TOOL ActiveHDL`
			`TOPMODULE BUS68030`